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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-18 06:57:07 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-20 14:45:35 +0000
commitbd96a8430046601dfa2ffbd31636dfd49a41e2ca (patch)
tree1a61b6d360ac983e3e1d8ef916b2a5d6f10c2598 /util/romcc/tests/simple_test54.c
parentcc8665eacc389318191aa6fe1b04b29580cc84ae (diff)
util: Fix typo on plural form of index
Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Diffstat (limited to 'util/romcc/tests/simple_test54.c')
-rw-r--r--util/romcc/tests/simple_test54.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/util/romcc/tests/simple_test54.c b/util/romcc/tests/simple_test54.c
index 37dce795c5..b7dee66bcf 100644
--- a/util/romcc/tests/simple_test54.c
+++ b/util/romcc/tests/simple_test54.c
@@ -569,7 +569,7 @@ static const struct mem_param *spd_set_memclk(void)
unsigned device;
uint32_t value;
- static const int latency_indicies[] = { 26, 23, 9 };
+ static const int latency_indices[] = { 26, 23, 9 };
static const unsigned char min_cycle_times[] = {
[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
@@ -637,7 +637,7 @@ static const struct mem_param *spd_set_memclk(void)
continue;
}
debug('D');
- value = smbus_read_byte(device, latency_indicies[index]);
+ value = smbus_read_byte(device, latency_indices[index]);
if (value < 0) continue;
debug('E');
@@ -723,7 +723,7 @@ static const struct mem_param *spd_set_memclk(void)
}
/* Read the min_cycle_time for this latency */
- value = smbus_read_byte(device, latency_indicies[index]);
+ value = smbus_read_byte(device, latency_indices[index]);
/* All is good if the selected clock speed
* is what I need or slower.