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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-01-14 21:27:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-16 08:40:01 +0000 |
| commit | fb19c8aae088eb36808c1988538229feb2c45691 (patch) | |
| tree | 567bc3d2cd0fa83ef80445251af3a1c3cd9b474b /util/riscv | |
| parent | 283b446612ac4c1d38a9a719fb6dddb71223545a (diff) | |
nb/intel/sandybridge: add macros for byte lane register offsets
This patch doesn't change the resulting binary of a timeless build.
Change-Id: Ife0e70699df3efa162f8f6c0fd8c2928887fda2d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions