diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-13 14:07:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-28 16:30:55 +0000 |
| commit | 48167b18a52915f03fff4e8f30aefc48d0e78a97 (patch) | |
| tree | b2d803e763448acfd09c863fad20d08bc241b24f /util/riscv | |
| parent | c5c35ce238e2ce032db7bc5e0addba1c2d46ef53 (diff) | |
soc/amd/genoa: Add timer & tsc support
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76501
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions