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| author | Jeremy Soller <jeremy@system76.com> | 2021-08-12 10:49:58 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-24 14:48:12 +0000 |
| commit | 21d7c477a45cef879669d436003c5834d3078dae (patch) | |
| tree | 93f480e1cb259ff5a2a2cb353cb858ec25b87ff8 /util/riscv | |
| parent | 657f7db769160fd99764883215d329e286f38dc0 (diff) | |
soc/intel/tigerlake: Add PCH-H GPIO definitions
Add TGL-H GPIO definitions, based on existing TGL definitions and how
CNP/CNP-H handles the split.
Reference:
- Intel doc 619207
- TigerLake FSP
- linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions