diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2020-02-06 14:20:57 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-18 16:51:57 +0000 |
| commit | 11637452cc093a64e078edebe1d6e18b462c3757 (patch) | |
| tree | f982350f69813939d97b8caf8f8fe326b51fdcac /util/riscv | |
| parent | 31b081a48d1cd654624c17b32265bd1e079e3912 (diff) | |
soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT
FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every Tiger Lake board.
BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci
Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions