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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-02-01 17:28:43 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-02 20:38:28 +0000 |
| commit | 0b76f02892ba37eceff4340c2ca8c4da3f721f9f (patch) | |
| tree | 80a9054926c56f35e2a206d4dd18b9d38f420e3d /util/riscv | |
| parent | 09ea3499e7f5647aebc408e49fb346d06222b0c0 (diff) | |
mb/amd/birman: add Phoenix with openSIL mainboard option
Introduce BOARD_AMD_BIRMAN_PHOENIX_OPENSIL which selects the openSIL
based Phoenix SoC code. Since the Phoenix chip.c is different due to
some FSP-specific data structures in there that are guarded in the
openSIL case, a separate devicetree for the openSIL case is added.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions