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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-04-19 17:07:36 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-22 18:36:56 +0000 |
| commit | d7427c6dc84a808611886f582d8aded467b50abc (patch) | |
| tree | 8ae7f0447f71340805583905e9fa987574fbfb0e /util/riscv/spike-elf.ld | |
| parent | 62535b66e64ff72229645931a7f5a08147095fc7 (diff) | |
vc/amd/opensil/stub/ramstage: add acpi_add_opensil_tables stub
In the non-stub openSIL coreboot glue code, this can be used to add the
ALIB SSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3ccd2e81211417ad4ac94f208572e0fa4e1cf97c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82012
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/riscv/spike-elf.ld')
0 files changed, 0 insertions, 0 deletions