diff options
| author | zhixingma <zhixing.ma@intel.com> | 2021-09-21 10:39:52 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-23 16:40:47 +0000 |
| commit | ef8654554f07f4c51130781dee3becbad1d2c618 (patch) | |
| tree | adb0f8152ad706c1ff88643942305e123b96825c /util/post | |
| parent | 7011fa1135009897a8fee5d96ade0f9fa9c960cc (diff) | |
mb/intel/adlrvp_m: Enable HECI1 communication
The patch enables HECI1 interface to allow OS applications to communicate
with CSE.
TEST=Verify PCI device 0:16.0 exposed in the lspci output
Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: Ifd338345caa183f03097f1003080992da70296ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'util/post')
0 files changed, 0 insertions, 0 deletions