diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-11-08 18:45:07 +0530 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-11-15 09:57:35 +0000 |
| commit | a2610581a58dd74670013ea3bf5eb6df54bff621 (patch) | |
| tree | f5bb2e9e95af501958cc9a9027a70df25f254d99 /util/post | |
| parent | 53075c720b3031798980797ec5d14bac93f9424e (diff) | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01
The headers added are generated as per FSP v2422_01.
Previous FSP version was v2374_01.
Changes Include:
- Add CnviDdrRfim UPD in FspmUpd.h
- UPDs description update in FspmUpd.h
BUG=b:205512463
BRANCH=None
TEST=Build and boot brya
Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/post')
0 files changed, 0 insertions, 0 deletions