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| author | Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> | 2024-08-26 11:14:56 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-29 12:31:10 +0000 |
| commit | 00610d57fa853c4f5f1c7e50fca6ad3ecbbc08e9 (patch) | |
| tree | a9efded4a142e2bad2692d41c8e027ff3113f176 /util/nvramtool/cmos_lowlevel.h | |
| parent | 40867e7b47077511f4d24585fd4f5d4a8d8de5d7 (diff) | |
mb/google/brya/var/nova: Configure scaler I2C GPIOs
According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL).
BUG=b:358439747
TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C.
Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Diffstat (limited to 'util/nvramtool/cmos_lowlevel.h')
0 files changed, 0 insertions, 0 deletions