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| author | Matt Papageorge <matthewpapa07@gmail.com> | 2021-10-08 13:30:23 -0500 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-10-11 15:59:10 +0000 |
| commit | cc2fa98c586cadc2105172767e0b65cffff4026e (patch) | |
| tree | 6e47e3085c77d632cf5d45c349bee48e9d7c87ce /util/msrtool/intel_pentium4_later.c | |
| parent | 0367c47eb08422c0b7364e5864d4e80199ea3699 (diff) | |
mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
coreboot normally owns PCIe resets for all Cezanne based systems.
However during S0i3 resume coreboot cannot intervene for S0 GPIOs
(S5 carry over fine) so we needed an alternate way to de-assert
this reset on guybrush. This change feeds in the given S0 reset
GPIO (69 in this case) so that SMU may de-assert this reset on
S0i3 resume.
BUG=b:199780346
TEST=With latest FSP verify SD device trains each of 10 cycles
Cq-Depend: chrome-internal:4157948
Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/msrtool/intel_pentium4_later.c')
0 files changed, 0 insertions, 0 deletions