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| author | Sean Rhodes <sean@starlabs.systems> | 2022-07-19 13:50:09 +0100 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-17 19:48:41 +0000 |
| commit | 03f6820194218ce32cc5497eec0c02c74b67bf6e (patch) | |
| tree | c8ae2e99c8d7de7cbb540d36f19ef6ddd0d89ab4 /util/mainboard/google/waddledee/template/include/variant | |
| parent | b660f4ee47ac2eab478a541af5f0e9217236ae22 (diff) | |
soc/intel/apollolake: Add the remaining CSE Firmware Status Registers
Add the Shadow Registers from 2 through 5 and print information
from them accordingly. All values were taken from Intel document
number 571993.
Tested on the StarLite Mk III and the correct values are
shown:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: Actual IBB Size : 88
[DEBUG] CSE: Verified Boot Valid : FAIL
[DEBUG] CSE: Verified Boot Test : NO
[DEBUG] CSE: FPF status : FUSED
Please note, the values shown are in an error state.
This replaces the Fuse check that is done via Heci, as this will only
work whilst the CSE is in a normal state.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'util/mainboard/google/waddledee/template/include/variant')
0 files changed, 0 insertions, 0 deletions