diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-13 02:36:02 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-01 20:37:04 +0000 |
| commit | c4eb45fa85d9860ce94829c6c977b9e28a297bf9 (patch) | |
| tree | 4b1f29ce8cf52e878ee54e16127f685e53ac7f31 /util/mainboard/google/trembyle | |
| parent | db4b21a1d04678041fae73be4a700f393cee879d (diff) | |
soc/amd/picasso: introduce and use chipset device tree
The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'util/mainboard/google/trembyle')
| -rw-r--r-- | util/mainboard/google/trembyle/template/overridetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/util/mainboard/google/trembyle/template/overridetree.cb b/util/mainboard/google/trembyle/template/overridetree.cb index 6f545b2402..d09c942296 100644 --- a/util/mainboard/google/trembyle/template/overridetree.cb +++ b/util/mainboard/google/trembyle/template/overridetree.cb @@ -37,9 +37,7 @@ chip soc/amd/picasso # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 1.6 off end # GPP Bridge 5 device pci 1.7 on end # GPP Bridge 6 - NVME - device pci 14.6 off end # Non-Functional SDHCI end # domain device mmio 0xfedc4000 on end |