diff options
| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2024-05-02 09:23:34 +0900 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-06 10:36:31 +0000 |
| commit | a053bca6adcbe625e1cdff2b85c9f35da3e445b4 (patch) | |
| tree | 0f8be9f8f4ac44a2ec8ed969f0528de89fce3d91 /util/kconfig/README.md | |
| parent | 7f0a7f65e6704c3ce050edd79c257f010535a366 (diff) | |
mb/google/brya/var/xol: Override TDP PL1 value
Update TDP PL1 value for the DTT optimization. The new value 18W is from
internal thermal/performance team.
- tdp_pl1_override: 15 -> 18 (W)
BUG=b:336684032
BRANCH=brya
TEST=built and verified MSR PL1 value.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
After this patch:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/kconfig/README.md')
0 files changed, 0 insertions, 0 deletions