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authorShreesh Chhabbi <shreesh.chhabbi@intel.com>2020-06-18 09:50:47 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-08-31 06:45:04 +0000
commit8fadf5aabfa62e35c6de511a9688cf20d8b94f24 (patch)
tree94c64c503661e6947242a18e05cc16c2f0d7d53f /util/inteltool/pcr.c
parent64c363b1a3d8a59ca27557b041f4170b95a509bc (diff)
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
These changes are according to spd_binary_optimization_volteer_v0.4 sheet. Offset Current value Updated value Analysis 1 0x10 0x11 As per SPD spec rev 1.1 5 0x19 0x21 16 bits for Row addrs, 10 bits for Column addrs 6 0x95 0xB5 4 die, 2 ch per pkg, Byte 16 signal matrix 12 0x02 0x0A 2 ranks per ch, 16 bits device data width 18 0x05 0x04 4267MHz support 29 0x90 0xC0 HW specific 30 0x06 0x68 HW specific 31 0xD0 0x60 HW specific 32 0x02 0x04 HW specific 125 0x00 0xE1 4267MHz support BUG=b:159319534 TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42524 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/inteltool/pcr.c')
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