diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-12-18 17:38:32 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2024-06-14 15:41:26 +0000 |
| commit | cb125d6f941fb764e865f4ac937f569397ffc118 (patch) | |
| tree | 1e04102126696eaebe533cc228f1e84b06dbad85 /util/inteltool/pcie.c | |
| parent | d20cc994ba78fa3b40b09ca6b6e21688a850ef01 (diff) | |
util/inteltool: Add more Westmere/Ironlake device IDs
The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.
For the sake of completeness, add the PCI device IDs for Clarkdale.
Though coreboot only supports Arrandale, both of them are Ironlake.
It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.
Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'util/inteltool/pcie.c')
| -rw-r--r-- | util/inteltool/pcie.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 7303811b67..32afa714fc 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -378,7 +378,9 @@ int print_dmibar(struct pci_dev *nb) dmi_registers = nehalem_dmi_registers; size = ARRAY_SIZE(nehalem_dmi_registers); break; - case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */ |