diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-07-06 12:54:48 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-14 12:41:50 +0000 |
| commit | e54a8fd43247d767f16a37f3e3150b2915d809bc (patch) | |
| tree | 06a147447038c3cc4f8b2df0cf835e6cb9acf01f /util/inteltool/ivy_memory.c | |
| parent | f9a179a66d4d01652b1d21afce8c0473ebf1950b (diff) | |
soc/intel/meteorlake: Add entry for GSPI2 device
This patch adds GSPI2 (PCI device B0:D18:F6) entry into the chipset.cb.
Additionally, increases `CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX` value
to include GSPI2 as well.
BUG=b:224325352
TEST=Able to build and boot Google/Rex platform.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I901128a1773fc6d2ba87e3e4972f45ad4a754d35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65675
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'util/inteltool/ivy_memory.c')
0 files changed, 0 insertions, 0 deletions