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authorAngel Pons <th3fanbus@gmail.com>2020-09-14 18:42:12 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-09-17 19:59:04 +0000
commitd02f3303d9e30880697d6f5101dd8a10ef23fe6b (patch)
tree7db1d7f16923313138a0e21757c580ec041ff412 /util/crossgcc
parent122e4ebd7dc7d063513a71d5a03b0443d0caf706 (diff)
nb/intel/ironlake: Drop `heci_bar` field from raminit
This field is only written to, never read. Drop it from raminfo. Also, bump MRC_CACHE_VERSION as the saved data layout has changed. Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'util/crossgcc')
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