crossgcc: Update toolchain

New tools: * mpfr 3.1.4 * binutils 2.26 * gcc 5.3.0 * llvm/clang 3.8.0 Patch changes: * binutils-2.25_fix-aarch64.patch: fixed in 2.26 * binutils-2.25_host-clang.patch: the positions of header file includes have been adjusted * binutils-2.25_no-bfd-doc.patch: update to 2.26 * binutils-2.25_riscv.patch: update from riscv-gnu-toolchain * gcc-5.2.0_elf_biarch.patch: update to 5.3.0 * gcc-5.2.0_gnat.patch: update to 5.3.0 * gcc-5.2.0_libgcc.patch: update to 5.3.0 * gcc-5.2.0_nds32.patch: update to 5.3.0 * gcc-5.2.0_riscv.patch: update from riscv-gnu-toolchain * cfe-3.7.1.src_frontend.patch: update to 3.8.0 In the latest code of riscv-gnu-toolchain project, the patch for {binutils,gcc}/config.sub has been removed, and the target is renamed as riscv32 and riscv64. The `riscv' to `riscv64' change in xcompile is in another commit. Test results: All GCC and LLVM/clang toolchain build successfully. x86,arm: qemu boots power8: firmware fails to boot aarch64,mips: not tested riscv: firmware fails to build with new binutils clang: firmware fails to boot Signed-off-by: Iru Cai <mytbk920423@gmail.com> Change-Id: I42ce89c29263d768d161c28199994f17d0389633 Reviewed-on: https://review.coreboot.org/14227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
author: Iru Cai <mytbk920423@gmail.com> 2016-04-02 10:50:59 +0800
committer: Stefan Reinauer <stefan.reinauer@coreboot.org> 2016-05-04 20:21:11 +0200
commit: ae8e3a0bbb1d028e9d18572304ec93e1495976f5 (patch)
tree: ae98bf3fb77548fdb16eb0f7d40c2a5cc4fdbf04 /util/crossgcc
parent: 2da008afa622e5469a34cd9d9712d498e84e4ea8 (diff)
24 files changed, 3802 insertions, 6198 deletions
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 3cee8f6a81..316e539547 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -18,8 +18,8 @@
 
 cd $(dirname $0)
 
-CROSSGCC_DATE="April 3rd, 2016"
-CROSSGCC_VERSION="1.38"
+CROSSGCC_DATE="April 16th, 2016"
+CROSSGCC_VERSION="1.39"
 CROSSGCC_COMMIT=$( git describe )
 
 # default settings
@@ -33,18 +33,18 @@ SKIPPYTHON=1
 
 # GCC toolchain version numbers
 GMP_VERSION=6.1.0
-MPFR_VERSION=3.1.3
+MPFR_VERSION=3.1.4
 MPC_VERSION=1.0.3
 LIBELF_VERSION=0.8.13
-GCC_VERSION=5.2.0
+GCC_VERSION=5.3.0
 GCC_AUTOCONF_VERSION=2.69
-BINUTILS_VERSION=2.25
+BINUTILS_VERSION=2.26
 GDB_VERSION=7.9.1
 IASL_VERSION=20160318
 PYTHON_VERSION=3.4.3
 EXPAT_VERSION=2.1.0
 # CLANG version number
-CLANG_VERSION=3.7.1
+CLANG_VERSION=3.8.0
 MAKE_VERSION=4.1
 
 # GCC toolchain archive locations
@@ -674,7 +674,7 @@ case "$TARGETARCH" in
 	i386-elf)		;;
 	i386-mingw32)		;;
 	mipsel-elf)		;;
-	riscv-elf)		;;
+	riscv-elf)		TARGETARCH=riscv64-elf;;
 	powerpc64*-linux*)	;;
 	i386*)			TARGETARCH=i386-elf;;
 	arm*)			TARGETARCH=arm-eabi;;
diff --git a/util/crossgcc/patches/binutils-2.25_fix-aarch64.patch b/util/crossgcc/patches/binutils-2.25_fix-aarch64.patch
deleted file mode 100644
index de6b9f23d4..0000000000
--- a/util/crossgcc/patches/binutils-2.25_fix-aarch64.patch
+++ /dev/null
@@ -1,14 +0,0 @@
-Taken from https://sourceware.org/ml/binutils/2014-10/msg00099.html
-Authored by Andreas Schwab <schwab@linux-m68k.org>
-diff --git a/gold/configure.tgt b/gold/configure.tgt
-index 9a75070..59a681e 100644
---- binutils-2.25/gold/configure.tgt
-+++ binutils-2.25/gold/configure.tgt
-@@ -146,6 +146,7 @@ arm*-*-*)
-  ;;
- aarch64*-*)
-  targ_obj=aarch64
-+ targ_extra_obj=aarch64-reloc-property
-  targ_machine=EM_AARCH64
-  targ_size=64
-  targ_extra_size=32
diff --git a/util/crossgcc/patches/binutils-2.25_host-clang.patch b/util/crossgcc/patches/binutils-2.25_host-clang.patch
deleted file mode 100644
index b34bacd599..0000000000
--- a/util/crossgcc/patches/binutils-2.25_host-clang.patch
+++ /dev/null
@@ -1,18 +0,0 @@
-This is a known issue on GNU mail list. Please refer
-the link below.
-https://sourceware.org/bugzilla/show_bug.cgi?id=17473
-
---- binutils-2.25/gold/binary.cc	2014-10-14 00:32:04.000000000 -0700
-+++ binutils-2.25.patched/gold/binary.cc	2015-09-15 07:02:40.000000000 -0700
-@@ -24,10 +24,10 @@
- 
- #include <cerrno>
- #include <cstring>
-+#include "stringpool.h"
- #include "safe-ctype.h"
- 
- #include "elfcpp.h"
--#include "stringpool.h"
- #include "fileread.h"
- #include "output.h"
- #include "binary.h"
diff --git a/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.26_no-bfd-doc.patch
index 5ad70da7d3..e73f95a134 100644
--- a/util/crossgcc/patches/binutils-2.25_no-bfd-doc.patch
+++ b/util/crossgcc/patches/binutils-2.26_no-bfd-doc.patch
@@ -1,7 +1,7 @@
-diff -ur binutils-2.25/bfd/Makefile.in binutils-2.25.patched/bfd/Makefile.in
---- binutils-2.25/bfd/Makefile.in	2015-09-15 06:25:42.000000000 -0700
-+++ binutils-2.25.patched/bfd/Makefile.in	2015-09-15 05:51:01.000000000 -0700
-@@ -339,7 +339,7 @@
+diff -ur binutils-2.26/bfd/Makefile.in binutils-2.26.patched/bfd/Makefile.in
+--- binutils-2.26/bfd/Makefile.in	2015-11-13 16:27:40.000000000 +0800
++++ binutils-2.26.patched/bfd/Makefile.in	2016-04-02 11:05:43.398422394 +0800
+@@ -341,7 +341,7 @@
  ACLOCAL_AMFLAGS = -I . -I .. -I ../config
  INCDIR = $(srcdir)/../include
  CSEARCH = -I. -I$(srcdir) -I$(INCDIR)
diff --git a/util/crossgcc/patches/binutils-2.25_riscv.patch b/util/crossgcc/patches/binutils-2.26_riscv.patch
index e4d3a9c876..d916b5661b 100644
--- a/util/crossgcc/patches/binutils-2.25_riscv.patch
+++ b/util/crossgcc/patches/binutils-2.26_riscv.patch
@@ -1,9 +1,9 @@
-diff -urN empty/bfd/cpu-riscv.c binutils-2.25/bfd/cpu-riscv.c
---- binutils-2.25/bfd/cpu-riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/bfd/cpu-riscv.c	2015-07-18 00:02:36.218287546 +0200
-@@ -0,0 +1,80 @@
+diff -urN empty/bfd/cpu-riscv.c binutils-2.26/bfd/cpu-riscv.c
+--- empty/bfd/cpu-riscv.c	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/bfd/cpu-riscv.c	2016-04-03 10:33:12.058793036 +0800
+@@ -0,0 +1,76 @@
 +/* BFD backend for RISC-V
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
 +   Based on MIPS target.
@@ -21,19 +21,15 @@ diff -urN empty/bfd/cpu-riscv.c binutils-2.25/bfd/cpu-riscv.c
 +   GNU General Public License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the Free Software
-+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-+   MA 02110-1301, USA.  */
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +#include "sysdep.h"
 +#include "bfd.h"
 +#include "libbfd.h"
 +
-+static const bfd_arch_info_type *riscv_compatible
-+  (const bfd_arch_info_type *, const bfd_arch_info_type *);
-+
-+/* The default routine tests bits_per_word, which is wrong on RISC-V, as
-+   RISC-V word size doesn't correlate with reloc size.  */
++/* This routine is provided two arch_infos and returns an arch_info
++   that is compatible with both, or NULL if none exists.  */
 +
 +static const bfd_arch_info_type *
 +riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
@@ -74,20 +70,20 @@ diff -urN empty/bfd/cpu-riscv.c binutils-2.25/bfd/cpu-riscv.c
 +
 +static const bfd_arch_info_type arch_info_struct[] =
 +{
-+  N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN(I_riscv64)),
++  N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN (I_riscv64)),
 +  N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0)
 +};
 +
-+/* The default architecture is riscv:rv64. */
++/* The default architecture is riscv:rv64.  */
 +
 +const bfd_arch_info_type bfd_riscv_arch =
-+N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]);
-diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
---- binutils-2.25/bfd/elfnn-riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/bfd/elfnn-riscv.c	2015-07-18 00:02:36.218287546 +0200
-@@ -0,0 +1,2995 @@
++  N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]);
+diff -urN empty/bfd/elfnn-riscv.c binutils-2.26/bfd/elfnn-riscv.c
+--- empty/bfd/elfnn-riscv.c	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/bfd/elfnn-riscv.c	2016-04-03 10:33:12.062126369 +0800
+@@ -0,0 +1,3022 @@
 +/* RISC-V-specific support for NN-bit ELF.
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
 +   Based on TILE-Gx and MIPS targets.
@@ -105,10 +101,8 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +   GNU General Public License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the Free Software
-+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-+   MA 02110-1301, USA.  */
-+
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +/* This file handles RISC-V ELF targets.  */
 +
@@ -136,6 +130,12 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +#define ELF64_DYNAMIC_INTERPRETER "/lib/ld.so.1"
 +#define ELF32_DYNAMIC_INTERPRETER "/lib32/ld.so.1"
 +
++#define ELF_ARCH			bfd_arch_riscv
++#define ELF_TARGET_ID			RISCV_ELF_DATA
++#define ELF_MACHINE_CODE		EM_RISCV
++#define ELF_MAXPAGESIZE			0x1000
++#define ELF_COMMONPAGESIZE		0x1000
++
 +/* The RISC-V linker needs to keep track of the number of relocs that it
 +   decides to copy as dynamic relocs in check_relocs for each symbol.
 +   This is so that it can later discard them if they are found to be
@@ -191,7 +191,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  (_bfd_riscv_elf_tdata (abfd)->local_got_tls_type)
 +
 +#define _bfd_riscv_elf_tls_type(abfd, h, symndx)		\
-+  (*((h) != NULL ? &riscv_elf_hash_entry(h)->tls_type		\
++  (*((h) != NULL ? &riscv_elf_hash_entry (h)->tls_type		\
 +     : &_bfd_riscv_elf_local_got_tls_type (abfd) [symndx]))
 +
 +#define is_riscv_elf(bfd)				\
@@ -266,13 +266,16 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +# define MATCH_LREG MATCH_LD
 +#endif
 +
-+/* The format of the first PLT entry.  */
++/* Generate a PLT header.  */
 +
 +static void
-+riscv_make_plt0_entry(bfd_vma gotplt_addr, bfd_vma addr, uint32_t *entry)
++riscv_make_plt_header (bfd_vma gotplt_addr, bfd_vma addr, uint32_t *entry)
 +{
++  bfd_vma gotplt_offset_high = RISCV_PCREL_HIGH_PART (gotplt_addr, addr);
++  bfd_vma gotplt_offset_low = RISCV_PCREL_LOW_PART (gotplt_addr, addr);
++
 +  /* auipc  t2, %hi(.got.plt)
-+     sub    t1, t1, t0               # shifted .got.plt offset + hdr size + 12
++     sub    t1, t1, t3               # shifted .got.plt offset + hdr size + 12
 +     l[w|d] t3, %lo(.got.plt)(t2)    # _dl_runtime_resolve
 +     addi   t1, t1, -(hdr size + 12) # shifted .got.plt offset
 +     addi   t0, t2, %lo(.got.plt)    # &.got.plt
@@ -280,29 +283,29 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +     l[w|d] t0, PTRSIZE(t0)          # link map
 +     jr     t3 */
 +
-+  entry[0] = RISCV_UTYPE (AUIPC, X_T2, RISCV_PCREL_HIGH_PART (gotplt_addr, addr));
-+  entry[1] = RISCV_RTYPE (SUB, X_T1, X_T1, X_T0);
-+  entry[2] = RISCV_ITYPE (LREG, X_T3, X_T2, RISCV_PCREL_LOW_PART (gotplt_addr, addr));
++  entry[0] = RISCV_UTYPE (AUIPC, X_T2, gotplt_offset_high);
++  entry[1] = RISCV_RTYPE (SUB, X_T1, X_T1, X_T3);
++  entry[2] = RISCV_ITYPE (LREG, X_T3, X_T2, gotplt_offset_low);
 +  entry[3] = RISCV_ITYPE (ADDI, X_T1, X_T1, -(PLT_HEADER_SIZE + 12));
-+  entry[4] = RISCV_ITYPE (ADDI, X_T0, X_T2, RISCV_PCREL_LOW_PART (gotplt_addr, addr));
++  entry[4] = RISCV_ITYPE (ADDI, X_T0, X_T2, gotplt_offset_low);
 +  entry[5] = RISCV_ITYPE (SRLI, X_T1, X_T1, 4 - RISCV_ELF_LOG_WORD_BYTES);
 +  entry[6] = RISCV_ITYPE (LREG, X_T0, X_T0, RISCV_ELF_WORD_BYTES);
 +  entry[7] = RISCV_ITYPE (JALR, 0, X_T3, 0);
 +}
 +
-+/* The format of subsequent PLT entries.  */
++/* Generate a PLT entry.  */
 +
 +static void
-+riscv_make_plt_entry(bfd_vma got_address, bfd_vma addr, uint32_t *entry)
++riscv_make_plt_entry (bfd_vma got, bfd_vma addr, uint32_t *entry)
 +{
-+  /* auipc  t1, %hi(.got.plt entry)
-+     l[w|d] t0, %lo(.got.plt entry)(t1)
-+     jalr   t1, t0
++  /* auipc  t3, %hi(.got.plt entry)
++     l[w|d] t3, %lo(.got.plt entry)(t3)
++     jalr   t1, t3
 +     nop */
 +
-+  entry[0] = RISCV_UTYPE (AUIPC, X_T1, RISCV_PCREL_HIGH_PART (got_address, addr));
-+  entry[1] = RISCV_ITYPE (LREG,  X_T0, X_T1, RISCV_PCREL_LOW_PART(got_address, addr));
-+  entry[2] = RISCV_ITYPE (JALR, X_T1, X_T0, 0);
++  entry[0] = RISCV_UTYPE (AUIPC, X_T3, RISCV_PCREL_HIGH_PART (got, addr));
++  entry[1] = RISCV_ITYPE (LREG,  X_T3, X_T3, RISCV_PCREL_LOW_PART(got, addr));
++  entry[2] = RISCV_ITYPE (JALR, X_T1, X_T3, 0);
 +  entry[3] = RISCV_NOP;
 +}
 +
@@ -446,7 +449,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +    return FALSE;
 +
 +  htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
-+  if (!info->shared)
++  if (!bfd_link_pic (info))
 +    {
 +      htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
 +      htab->sdyntdata =
@@ -455,7 +458,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +    }
 +
 +  if (!htab->elf.splt || !htab->elf.srelplt || !htab->sdynbss
-+      || (!info->shared && (!htab->srelbss || !htab->sdyntdata)))
++      || (!bfd_link_pic (info) && (!htab->srelbss || !htab->sdyntdata)))
 +    abort ();
 +
 +  return TRUE;
@@ -539,7 +542,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  if (htab->elf.sgot == NULL)
 +    {
 +      if (!riscv_elf_create_got_section (htab->elf.dynobj, info))
-+        return FALSE;
++	return FALSE;
 +    }
 +
 +  if (h != NULL)
@@ -566,7 +569,8 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +bad_static_reloc (bfd *abfd, unsigned r_type, struct elf_link_hash_entry *h)
 +{
 +  (*_bfd_error_handler)
-+    (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
++    (_("%B: relocation %s against `%s' can not be used when making a shared "
++       "object; recompile with -fPIC"),
 +      abfd, riscv_elf_rtype_to_howto (r_type)->name,
 +      h != NULL ? h->root.root.string : "a local symbol");
 +  bfd_set_error (bfd_error_bad_value);
@@ -586,7 +590,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  const Elf_Internal_Rela *rel;
 +  asection *sreloc = NULL;
 +
-+  if (info->relocatable)
++  if (bfd_link_relocatable (info))
 +    return TRUE;
 +
 +  htab = riscv_elf_hash_table (info);
@@ -635,7 +639,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	  break;
 +
 +	case R_RISCV_TLS_GOT_HI20:
-+	  if (info->shared)
++	  if (bfd_link_pic (info))
 +	    info->flags |= DF_STATIC_TLS;
 +	  if (!riscv_elf_record_got_reference (abfd, info, h, r_symndx)
 +	      || !riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_IE))
@@ -668,20 +672,20 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	case R_RISCV_RVC_BRANCH:
 +	case R_RISCV_RVC_JUMP:
 +	case R_RISCV_PCREL_HI20:
-+	  /* In shared libs, these relocs are known to bind locally.  */
-+	  if (info->shared)
++	  /* In shared libraries, these relocs are known to bind locally.  */
++	  if (bfd_link_pic (info))
 +	    break;
 +	  goto static_reloc;
 +
 +	case R_RISCV_TPREL_HI20:
-+	  if (!info->executable)
++	  if (!bfd_link_executable (info))
 +	    return bad_static_reloc (abfd, r_type, h);
 +	  if (h != NULL)
 +	    riscv_elf_record_tls_type (abfd, h, r_symndx, GOT_TLS_LE);
 +	  goto static_reloc;
 +
 +	case R_RISCV_HI20:
-+	  if (info->shared)
++	  if (bfd_link_pic (info))
 +	    return bad_static_reloc (abfd, r_type, h);
 +	  /* Fall through.  */
 +
@@ -693,10 +697,11 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	  /* Fall through.  */
 +
 +	static_reloc:
++	  /* This reloc might not bind locally.  */
 +	  if (h != NULL)
 +	    h->non_got_ref = 1;
 +
-+	  if (h != NULL && !info->shared)
++	  if (h != NULL && !bfd_link_pic (info))
 +	    {
 +	      /* We may need a .plt entry if the function this reloc
 +		 refers to is in a shared lib.  */
@@ -724,14 +729,14 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	     may need to keep relocations for symbols satisfied by a
 +	     dynamic library if we manage to avoid copy relocs for the
 +	     symbol.  */
-+	  if ((info->shared
++	  if ((bfd_link_pic (info)
 +	       && (sec->flags & SEC_ALLOC) != 0
 +	       && (! riscv_elf_rtype_to_howto (r_type)->pc_relative
 +		   || (h != NULL
 +		       && (! info->symbolic
 +			   || h->root.type == bfd_link_hash_defweak
 +			   || !h->def_regular))))
-+	      || (!info->shared
++	      || (!bfd_link_pic (info)
 +		  && (sec->flags & SEC_ALLOC) != 0
 +		  && h != NULL
 +		  && (h->root.type == bfd_link_hash_defweak
@@ -847,7 +852,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (abfd);
 +  bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd);
 +
-+  if (info->relocatable)
++  if (bfd_link_relocatable (info))
 +    return TRUE;
 +
 +  elf_section_data (sec)->local_dynrel = NULL;
@@ -908,7 +913,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	case R_RISCV_JAL:
 +	case R_RISCV_RVC_BRANCH:
 +	case R_RISCV_RVC_JUMP:
-+	  if (info->shared)
++	  if (bfd_link_pic (info))
 +	    break;
 +	  /* Fall through.  */
 +
@@ -1000,7 +1005,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +     only references to the symbol are via the global offset table.
 +     For such cases we need not do anything here; the relocations will
 +     be handled correctly by relocate_section.  */
-+  if (info->shared)
++  if (bfd_link_pic (info))
 +    return TRUE;
 +
 +  /* If there are no references to this symbol that do not use the
@@ -1052,9 +1057,9 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +    }
 +
 +  if (eh->tls_type & ~GOT_NORMAL)
-+    return _bfd_elf_adjust_dynamic_copy (h, htab->sdyntdata);
++    return _bfd_elf_adjust_dynamic_copy (info, h, htab->sdyntdata);
 +
-+  return _bfd_elf_adjust_dynamic_copy (h, htab->sdynbss);
++  return _bfd_elf_adjust_dynamic_copy (info, h, htab->sdynbss);
 +}
 +
 +/* Allocate space in .plt, .got and associated reloc sections for
@@ -1087,7 +1092,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	    return FALSE;
 +	}
 +
-+      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, info->shared, h))
++      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h))
 +	{
 +	  asection *s = htab->elf.splt;
 +
@@ -1110,7 +1115,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	     location in the .plt.  This is required to make function
 +	     pointers compare as equal between the normal executable and
 +	     the shared library.  */
-+	  if (! info->shared
++	  if (! bfd_link_pic (info)
 +	      && !h->def_regular)
 +	    {
 +	      h->root.u.def.section = s;
@@ -1133,7 +1138,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +    {
 +      asection *s;
 +      bfd_boolean dyn;
-+      int tls_type = riscv_elf_hash_entry(h)->tls_type;
++      int tls_type = riscv_elf_hash_entry (h)->tls_type;
 +
 +      /* Make sure this symbol is output as a dynamic symbol.
 +	 Undefined weak syms won't yet be marked as dynamic.  */
@@ -1166,7 +1171,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +      else
 +	{
 +	  s->size += RISCV_ELF_WORD_BYTES;
-+	  if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h))
++	  if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, bfd_link_pic (info), h))
 +	    htab->elf.srelgot->size += sizeof (ElfNN_External_Rela);
 +	}
 +    }
@@ -1183,7 +1188,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +     space for pc-relative relocs that have become local due to symbol
 +     visibility changes.  */
 +
-+  if (info->shared)
++  if (bfd_link_pic (info))
 +    {
 +      if (SYMBOL_CALLS_LOCAL (info, h))
 +	{
@@ -1277,8 +1282,6 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +      if (s != NULL && (s->flags & SEC_READONLY) != 0)
 +	{
 +	  ((struct bfd_link_info *) inf)->flags |= DF_TEXTREL;
-+
-+	  /* Short-circuit the traversal.  */
 +	  return FALSE;
 +	}
 +    }
@@ -1301,7 +1304,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  if (elf_hash_table (info)->dynamic_sections_created)
 +    {
 +      /* Set the contents of the .interp section to the interpreter.  */
-+      if (info->executable)
++      if (bfd_link_executable (info) && !info->nointerp)
 +	{
 +	  s = bfd_get_linker_section (dynobj, ".interp");
 +	  BFD_ASSERT (s != NULL);
@@ -1366,7 +1369,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	      s->size += RISCV_ELF_WORD_BYTES;
 +	      if (*local_tls_type & GOT_TLS_GD)
 +		s->size += RISCV_ELF_WORD_BYTES;
-+	      if (info->shared
++	      if (bfd_link_pic (info)
 +		  || (*local_tls_type & (GOT_TLS_GD | GOT_TLS_IE)))
 +		srel->size += sizeof (ElfNN_External_Rela);
 +	    }
@@ -1466,7 +1469,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +#define add_dynamic_entry(TAG, VAL) \
 +  _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 +
-+      if (info->executable)
++      if (bfd_link_executable (info))
 +	{
 +	  if (!add_dynamic_entry (DT_DEBUG, 0))
 +	    return FALSE;
@@ -1563,16 +1566,20 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +    case R_RISCV_GOT_HI20:
 +    case R_RISCV_TLS_GOT_HI20:
 +    case R_RISCV_TLS_GD_HI20:
++      if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
++	return bfd_reloc_overflow;
 +      value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
 +      break;
 +
 +    case R_RISCV_LO12_I:
++    case R_RISCV_GPREL_I:
 +    case R_RISCV_TPREL_LO12_I:
 +    case R_RISCV_PCREL_LO12_I:
 +      value = ENCODE_ITYPE_IMM (value);
 +      break;
 +
 +    case R_RISCV_LO12_S:
++    case R_RISCV_GPREL_S:
 +    case R_RISCV_TPREL_LO12_S:
 +    case R_RISCV_PCREL_LO12_S:
 +      value = ENCODE_STYPE_IMM (value);
@@ -1580,7 +1587,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +
 +    case R_RISCV_CALL:
 +    case R_RISCV_CALL_PLT:
-+      if (!VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
++      if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
 +	return bfd_reloc_overflow;
 +      value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))
 +	      | (ENCODE_ITYPE_IMM (value) << 32);
@@ -1610,6 +1617,12 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +      value = ENCODE_RVC_J_IMM (value);
 +      break;
 +
++    case R_RISCV_RVC_LUI:
++      if (!VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value)))
++	return bfd_reloc_overflow;
++      value = ENCODE_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value));
++      break;
++
 +    case R_RISCV_32:
 +    case R_RISCV_64:
 +    case R_RISCV_ADD8:
@@ -1856,7 +1869,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
 +					 rel, 1, relend, howto, 0, contents);
 +
-+      if (info->relocatable)
++      if (bfd_link_relocatable (info))
 +	continue;
 +
 +      if (h != NULL)
@@ -1879,24 +1892,27 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	  /* These require nothing of us at all.  */
 +	  continue;
 +
++	case R_RISCV_HI20:
 +	case R_RISCV_BRANCH:
 +	case R_RISCV_RVC_BRANCH:
-+	case R_RISCV_HI20:
++	case R_RISCV_RVC_LUI:
++	case R_RISCV_LO12_I:
++	case R_RISCV_LO12_S:
 +	  /* These require no special handling beyond perform_relocation.  */
 +	  break;
 +
 +	case R_RISCV_GOT_HI20:
 +	  if (h != NULL)
 +	    {
-+	      bfd_boolean dyn;
++	      bfd_boolean dyn, pic;
 +
 +	      off = h->got.offset;
 +	      BFD_ASSERT (off != (bfd_vma) -1);
 +	      dyn = elf_hash_table (info)->dynamic_sections_created;
++	      pic = bfd_link_pic (info);
 +
-+	      if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h)
-+		  || (info->shared
-+		      && SYMBOL_REFERENCES_LOCAL (info, h)))
++	      if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, pic, h)
++		  || (pic && SYMBOL_REFERENCES_LOCAL (info, h)))
 +		{
 +		  /* This is actually a static link, or it is a
 +		     -Bsymbolic link and the symbol is defined
@@ -1929,14 +1945,14 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +
 +	      off = local_got_offsets[r_symndx];
 +
-+	      /* The offset must always be a multiple of 8 on 64-bit.
-+		 We use the least significant bit to record
++	      /* The offset must always be a multiple of the word size.
++		 So, we can use the least significant bit to record
 +		 whether we have already processed this entry.  */
 +	      if ((off & 1) != 0)
 +		off &= ~1;
 +	      else
 +		{
-+		  if (info->shared)
++		  if (bfd_link_pic (info))
 +		    {
 +		      asection *s;
 +		      Elf_Internal_Rela outrel;
@@ -1990,7 +2006,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	case R_RISCV_CALL:
 +	case R_RISCV_JAL:
 +	case R_RISCV_RVC_JUMP:
-+	  if (info->shared && h != NULL && h->plt.offset != MINUS_ONE)
++	  if (bfd_link_pic (info) && h != NULL && h->plt.offset != MINUS_ONE)
 +	    {
 +	      /* Refer to the PLT entry.  */
 +	      relocation = sec_addr (htab->elf.splt) + h->plt.offset;
@@ -2015,8 +2031,8 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	    }
 +	  break;
 +
-+	case R_RISCV_LO12_I:
-+	case R_RISCV_LO12_S:
++	case R_RISCV_GPREL_I:
++	case R_RISCV_GPREL_S:
 +	  {
 +	    bfd_vma gp = riscv_global_pointer_value (info);
 +	    bfd_boolean x0_base = VALID_ITYPE_IMM (relocation + rel->r_addend);
@@ -2032,6 +2048,8 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +		  }
 +		bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
 +	      }
++	    else
++	      r = bfd_reloc_overflow;
 +	    break;
 +	  }
 +
@@ -2060,13 +2078,13 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	  if ((input_section->flags & SEC_ALLOC) == 0)
 +	    break;
 +
-+	  if ((info->shared
++	  if ((bfd_link_pic (info)
 +	       && (h == NULL
 +		   || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
 +		   || h->root.type != bfd_link_hash_undefweak)
 +	       && (! howto->pc_relative
 +		   || !SYMBOL_CALLS_LOCAL (info, h)))
-+	      || (!info->shared
++	      || (!bfd_link_pic (info)
 +		  && h != NULL
 +		  && h->dynindx != -1
 +		  && !h->non_got_ref
@@ -2092,7 +2110,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	      if (skip_dynamic_relocation)
 +		memset (&outrel, 0, sizeof outrel);
 +	      else if (h != NULL && h->dynindx != -1
-+		       && !(info->shared
++		       && !(bfd_link_pic (info)
 +			    && SYMBOLIC_BIND (info, h)
 +			    && h->def_regular))
 +		{
@@ -2147,21 +2165,19 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +		abort ();
 +
 +	      if (h != NULL)
-+	      {
-+	        bfd_boolean dyn;
-+	        dyn = htab->elf.dynamic_sections_created;
++		{
++		  bfd_boolean dyn, pic;
++		  dyn = htab->elf.dynamic_sections_created;
++		  pic = bfd_link_pic (info);
 +
-+		if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h)
-+		    && (!info->shared
-+			|| !SYMBOL_REFERENCES_LOCAL (info, h)))
-+		  {
++		  if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, pic, h)
++		      && (!pic || !SYMBOL_REFERENCES_LOCAL (info, h)))
 +		    indx = h->dynindx;
-+		  }
-+	      }
++		}
 +
 +	      /* The GOT entries have not been initialized yet.  Do it
 +	         now, and emit any relocations.  */
-+	      if ((info->shared || indx != 0)
++	      if ((bfd_link_pic (info) || indx != 0)
 +		  && (h == NULL
 +		      || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
 +		      || h->root.type != bfd_link_hash_undefweak))
@@ -2178,30 +2194,30 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +				  htab->elf.sgot->contents + off);
 +		      riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
 +		      if (indx == 0)
-+		        {
++			{
 +			  BFD_ASSERT (! unresolved_reloc);
 +			  bfd_put_NN (output_bfd,
 +				      dtpoff (info, relocation),
 +				      (htab->elf.sgot->contents + off +
 +				       RISCV_ELF_WORD_BYTES));
-+		        }
++			}
 +		      else
-+		        {
++			{
 +			  bfd_put_NN (output_bfd, 0,
 +				      (htab->elf.sgot->contents + off +
 +				       RISCV_ELF_WORD_BYTES));
-+		          outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPRELNN);
-+		          outrel.r_offset += RISCV_ELF_WORD_BYTES;
-+		          riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
-+		        }
++			  outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPRELNN);
++			  outrel.r_offset += RISCV_ELF_WORD_BYTES;
++			  riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
++			}
 +		    }
 +		  else
 +		    {
 +		      /* If we are not emitting relocations for a
-+		         general dynamic reference, then we must be in a
-+		         static link or an executable link with the
-+		         symbol binding locally.  Mark it as belonging
-+		         to module 1, the executable.  */
++			 general dynamic reference, then we must be in a
++			 static link or an executable link with the
++			 symbol binding locally.  Mark it as belonging
++			 to module 1, the executable.  */
 +		      bfd_put_NN (output_bfd, 1,
 +				  htab->elf.sgot->contents + off);
 +		      bfd_put_NN (output_bfd,
@@ -2221,7 +2237,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +				       + off + ie_off;
 +		      outrel.r_addend = 0;
 +		      if (indx == 0)
-+		        outrel.r_addend = tpoff (info, relocation);
++			outrel.r_addend = tpoff (info, relocation);
 +		      outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_TPRELNN);
 +		      riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
 +		    }
@@ -2271,36 +2287,36 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	{
 +	case bfd_reloc_ok:
 +	  continue;
-+      
++
 +	case bfd_reloc_overflow:
 +	  r = info->callbacks->reloc_overflow
 +	    (info, (h ? &h->root : NULL), name, howto->name,
 +	     (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
 +	  break;
-+      
++
 +	case bfd_reloc_undefined:
 +	  r = info->callbacks->undefined_symbol
 +	    (info, name, input_bfd, input_section, rel->r_offset,
 +	     TRUE);
 +	  break;
-+      
++
 +	case bfd_reloc_outofrange:
 +	  msg = _("internal error: out of range error");
 +	  break;
-+      
++
 +	case bfd_reloc_notsupported:
 +	  msg = _("internal error: unsupported relocation error");
 +	  break;
-+      
++
 +	case bfd_reloc_dangerous:
 +	  msg = _("internal error: dangerous relocation");
 +	  break;
-+      
++
 +	default:
 +	  msg = _("internal error: unknown error");
 +	  break;
 +	}
-+      
++
 +      if (msg)
 +	r = info->callbacks->warning
 +	  (info, msg, name, input_bfd, input_section, rel->r_offset);
@@ -2400,7 +2416,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	 the symbol was forced to be local because of a version file.
 +	 The entry in the global offset table will already have been
 +	 initialized in the relocate_section function.  */
-+      if (info->shared
++      if (bfd_link_pic (info)
 +	  && (info->symbolic || h->dynindx == -1)
 +	  && h->def_regular)
 +	{
@@ -2517,7 +2533,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	{
 +	  int i;
 +	  uint32_t plt_header[PLT_HEADER_INSNS];
-+	  riscv_make_plt0_entry (sec_addr (htab->elf.sgotplt),
++	  riscv_make_plt_header (sec_addr (htab->elf.sgotplt),
 +				 sec_addr (splt), plt_header);
 +
 +	  for (i = 0; i < PLT_HEADER_INSNS; i++)
@@ -2530,7 +2546,9 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +
 +  if (htab->elf.sgotplt)
 +    {
-+      if (bfd_is_abs_section (htab->elf.sgotplt->output_section))
++      asection *output_section = htab->elf.sgotplt->output_section;
++
++      if (bfd_is_abs_section (output_section))
 +	{
 +	  (*_bfd_error_handler)
 +	    (_("discarded output section: `%A'"), htab->elf.sgotplt);
@@ -2546,12 +2564,13 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +		      htab->elf.sgotplt->contents + GOT_ENTRY_SIZE);
 +	}
 +
-+      elf_section_data (htab->elf.sgotplt->output_section)->this_hdr.sh_entsize =
-+	GOT_ENTRY_SIZE;
++      elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE;
 +    }
 +
 +  if (htab->elf.sgot)
 +    {
++      asection *output_section = htab->elf.sgot->output_section;
++
 +      if (htab->elf.sgot->size > 0)
 +	{
 +	  /* Set the first entry in the global offset table to the address of
@@ -2560,8 +2579,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	  bfd_put_NN (output_bfd, val, htab->elf.sgot->contents);
 +	}
 +
-+      elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize =
-+	GOT_ENTRY_SIZE;
++      elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE;
 +    }
 +
 +  return TRUE;
@@ -2595,22 +2613,14 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +    }
 +}
 +
-+/* Return true if bfd machine EXTENSION is an extension of machine BASE.  */
-+
-+static bfd_boolean
-+riscv_mach_extends_p (unsigned long base, unsigned long extension)
-+{
-+  return extension == base;
-+}
-+
 +/* Merge backend specific data from an object file to the output
 +   object file when linking.  */
 +
 +static bfd_boolean
 +_bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
 +{
-+  flagword old_flags;
-+  flagword new_flags;
++  flagword new_flags = elf_elfheader (ibfd)->e_flags;
++  flagword old_flags = elf_elfheader (obfd)->e_flags;
 +
 +  if (!is_riscv_elf (ibfd) || !is_riscv_elf (obfd))
 +    return TRUE;
@@ -2626,59 +2636,23 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
 +    return FALSE;
 +
-+  new_flags = elf_elfheader (ibfd)->e_flags;
-+  old_flags = elf_elfheader (obfd)->e_flags;
-+
 +  if (! elf_flags_init (obfd))
 +    {
 +      elf_flags_init (obfd) = TRUE;
 +      elf_elfheader (obfd)->e_flags = new_flags;
-+      elf_elfheader (obfd)->e_ident[EI_CLASS]
-+	= elf_elfheader (ibfd)->e_ident[EI_CLASS];
-+
-+      if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
-+	  && (bfd_get_arch_info (obfd)->the_default
-+	      || riscv_mach_extends_p (bfd_get_mach (obfd), 
-+				       bfd_get_mach (ibfd))))
-+	{
-+	  if (! bfd_set_arch_mach (obfd, bfd_get_arch (ibfd),
-+				   bfd_get_mach (ibfd)))
-+	    return FALSE;
-+	}
-+
 +      return TRUE;
 +    }
 +
-+  /* Check flag compatibility.  */
-+
-+  if (new_flags == old_flags)
-+    return TRUE;
-+
-+  /* Don't link RV32 and RV64.  */
-+  if (elf_elfheader (ibfd)->e_ident[EI_CLASS]
-+      != elf_elfheader (obfd)->e_ident[EI_CLASS])
++  /* Disallow linking soft-float and hard-float.  */
++  if ((old_flags ^ new_flags) & EF_RISCV_SOFT_FLOAT)
 +    {
 +      (*_bfd_error_handler)
-+	(_("%B: ELF class mismatch: can't link 32- and 64-bit modules"), ibfd);
++	(_("%B: can't link hard-float modules with soft-float modules"), ibfd);
 +      goto fail;
 +    }
 +
-+  /* Warn about any other mismatches.  */
-+  if (new_flags != old_flags)
-+    {
-+      if (!EF_IS_RISCV_EXT_Xcustom (new_flags) &&
-+	  !EF_IS_RISCV_EXT_Xcustom (old_flags))
-+	{
-+	  (*_bfd_error_handler)
-+	    (_("%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"),
-+	    ibfd, (unsigned long) new_flags,
-+	    (unsigned long) old_flags);
-+	  goto fail;
-+	}
-+      else if (EF_IS_RISCV_EXT_Xcustom(new_flags))
-+	EF_SET_RISCV_EXT (elf_elfheader (obfd)->e_flags,
-+			  EF_GET_RISCV_EXT (old_flags));
-+    }
++  /* Allow linking RVC and non-RVC, and keep the RVC flag.  */
++  elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC;
 +
 +  return TRUE;
 +
@@ -2733,7 +2707,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +    }
 +
 +  /* Now adjust the global symbols defined in this section.  */
-+  symcount = ((symtab_hdr->sh_size / sizeof(ElfNN_External_Sym))
++  symcount = ((symtab_hdr->sh_size / sizeof (ElfNN_External_Sym))
 +	      - symtab_hdr->sh_info);
 +
 +  for (i = 0; i < symcount; i++)
@@ -2763,7 +2737,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +/* Relax AUIPC + JALR into JAL.  */
 +
 +static bfd_boolean
-+_bfd_riscv_relax_call (bfd *abfd, asection *sec,
++_bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
 +		       struct bfd_link_info *link_info,
 +		       Elf_Internal_Rela *rel,
 +		       bfd_vma symval,
@@ -2775,8 +2749,14 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  bfd_vma auipc, jalr;
 +  int rd, r_type, len = 4, rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
 +
++  /* If the call crosses section boundaries, an alignment directive could
++     cause the PC-relative offset to later increase.  Assume at most
++     page-alignment, and account for this by adding some slop.  */
++  if (VALID_UJTYPE_IMM (foff) && sym_sec->output_section != sec->output_section)
++    foff += (foff < 0 ? -ELF_MAXPAGESIZE : ELF_MAXPAGESIZE);
++
 +  /* See if this function call can be shortened.  */
-+  if (!VALID_UJTYPE_IMM (foff) && !(!link_info->shared && near_zero))
++  if (!VALID_UJTYPE_IMM (foff) && !(!bfd_link_pic (link_info) && near_zero))
 +    return TRUE;
 +
 +  /* Shorten the function call.  */
@@ -2785,7 +2765,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  auipc = bfd_get_32 (abfd, contents + rel->r_offset);
 +  jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
 +  rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
-+  rvc = rvc && VALID_RVC_J_IMM (foff);
++  rvc = rvc && VALID_RVC_J_IMM (foff) && ARCH_SIZE == 32;
 +
 +  if (rvc && (rd == 0 || rd == X_RA))
 +    {
@@ -2820,31 +2800,77 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +/* Relax non-PIC global variable references.  */
 +
 +static bfd_boolean
-+_bfd_riscv_relax_lui (bfd *abfd, asection *sec,
++_bfd_riscv_relax_lui (bfd *abfd, asection *sec, asection *sym_sec,
 +		      struct bfd_link_info *link_info,
 +		      Elf_Internal_Rela *rel,
 +		      bfd_vma symval,
 +		      bfd_boolean *again)
 +{
++  bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
 +  bfd_vma gp = riscv_global_pointer_value (link_info);
++  int use_rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
 +
-+  /* Bail out if this symbol isn't in range of either gp or x0.  */
-+  if (!VALID_ITYPE_IMM (symval - gp) && !(symval < RISCV_IMM_REACH/2))
++  /* Mergeable symbols might later move out of range.  */
++  if (sym_sec->flags & SEC_MERGE)
 +    return TRUE;
 +
-+  /* We can delete the unnecessary AUIPC. The corresponding LO12 reloc
-+     will be converted to GPREL during relocation.  */
 +  BFD_ASSERT (rel->r_offset + 4 <= sec->size);
-+  rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
 +
-+  *again = TRUE;
-+  return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4);
++  /* Is the reference in range of x0 or gp?  */
++  if (VALID_ITYPE_IMM (symval) || VALID_ITYPE_IMM (symval - gp))
++    {
++      unsigned sym = ELFNN_R_SYM (rel->r_info);
++      switch (ELFNN_R_TYPE (rel->r_info))
++	{
++	case R_RISCV_LO12_I:
++	  rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
++	  return TRUE;
++
++	case R_RISCV_LO12_S:
++	  rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
++	  return TRUE;
++
++	case R_RISCV_HI20:
++	  /* We can delete the unnecessary LUI and reloc.  */
++	  rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
++	  *again = TRUE;
++	  return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4);
++
++	default:
++	  abort ();
++	}
++    }
++
++  /* Can we relax LUI to C.LUI?  Alignment might move the section forward;
++     account for this assuming page alignment at worst.  */
++  if (use_rvc
++      && ELFNN_R_TYPE (rel->r_info) == R_RISCV_HI20
++      && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval))
++      && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval + ELF_MAXPAGESIZE)))
++    {
++      /* Replace LUI with C.LUI if legal (i.e., rd != x2/sp).  */
++      bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset);
++      if (((lui >> OP_SH_RD) & OP_MASK_RD) == X_SP)
++	return TRUE;
++
++      lui = (lui & (OP_MASK_RD << OP_SH_RD)) | MATCH_C_LUI;
++      bfd_put_32 (abfd, lui, contents + rel->r_offset);
++
++      /* Replace the R_RISCV_HI20 reloc.  */
++      rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), R_RISCV_RVC_LUI);
++
++      *again = TRUE;
++      return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 2, 2);
++    }
++
++  return TRUE;
 +}
 +
 +/* Relax non-PIC TLS references.  */
 +
 +static bfd_boolean
 +_bfd_riscv_relax_tls_le (bfd *abfd, asection *sec,
++			 asection *sym_sec ATTRIBUTE_UNUSED,
 +			 struct bfd_link_info *link_info,
 +			 Elf_Internal_Rela *rel,
 +			 bfd_vma symval,
@@ -2867,6 +2893,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +
 +static bfd_boolean
 +_bfd_riscv_relax_align (bfd *abfd, asection *sec,
++			asection *sym_sec ATTRIBUTE_UNUSED,
 +			struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
 +			Elf_Internal_Rela *rel,
 +			bfd_vma symval,
@@ -2924,7 +2951,7 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +
 +  *again = FALSE;
 +
-+  if (info->relocatable
++  if (bfd_link_relocatable (info)
 +      || sec->sec_flg0
 +      || (sec->flags & SEC_RELOC) == 0
 +      || sec->reloc_count == 0
@@ -2942,8 +2969,9 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  /* Examine and consider relaxing each reloc.  */
 +  for (i = 0; i < sec->reloc_count; i++)
 +    {
++      asection *sym_sec;
 +      Elf_Internal_Rela *rel = relocs + i;
-+      typeof(&_bfd_riscv_relax_call) relax_func = NULL;
++      typeof (&_bfd_riscv_relax_call) relax_func = NULL;
 +      int type = ELFNN_R_TYPE (rel->r_info);
 +      bfd_vma symval;
 +
@@ -2951,7 +2979,9 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +	{
 +	  if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT)
 +	    relax_func = _bfd_riscv_relax_call;
-+	  else if (type == R_RISCV_HI20)
++	  else if (type == R_RISCV_HI20
++		   || type == R_RISCV_LO12_I
++		   || type == R_RISCV_LO12_S)
 +	    relax_func = _bfd_riscv_relax_lui;
 +	  else if (type == R_RISCV_TPREL_HI20 || type == R_RISCV_TPREL_ADD)
 +	    relax_func = _bfd_riscv_relax_tls_le;
@@ -2986,15 +3016,14 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +				    + ELFNN_R_SYM (rel->r_info));
 +
 +	  if (isym->st_shndx == SHN_UNDEF)
-+	    symval = sec_addr (sec) + rel->r_offset;
++	    sym_sec = sec, symval = sec_addr (sec) + rel->r_offset;
 +	  else
 +	    {
-+	      asection *isec;
 +	      BFD_ASSERT (isym->st_shndx < elf_numsections (abfd));
-+	      isec = elf_elfsections (abfd)[isym->st_shndx]->bfd_section;
-+	      if (sec_addr (isec) == 0)
++	      sym_sec = elf_elfsections (abfd)[isym->st_shndx]->bfd_section;
++	      if (sec_addr (sym_sec) == 0)
 +		continue;
-+	      symval = sec_addr (isec) + isym->st_value;
++	      symval = sec_addr (sym_sec) + isym->st_value;
 +	    }
 +	}
 +      else
@@ -3011,19 +3040,19 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +
 +	  if (h->plt.offset != MINUS_ONE)
 +	    symval = sec_addr (htab->elf.splt) + h->plt.offset;
-+	  else if (h->root.type == bfd_link_hash_undefweak)
-+	    symval = 0;
 +	  else if (h->root.u.def.section->output_section == NULL
 +		   || (h->root.type != bfd_link_hash_defined
 +		       && h->root.type != bfd_link_hash_defweak))
 +	    continue;
 +	  else
 +	    symval = sec_addr (h->root.u.def.section) + h->root.u.def.value;
++
++	  sym_sec = h->root.u.def.section;
 +	}
 +
 +      symval += rel->r_addend;
 +
-+      if (!relax_func (abfd, sec, info, rel, symval, again))
++      if (!relax_func (abfd, sec, sym_sec, info, rel, symval, again))
 +	goto fail;
 +    }
 +
@@ -3036,18 +3065,12 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +  return ret;
 +}
 +
-+#define ELF_ARCH			bfd_arch_riscv
-+#define ELF_TARGET_ID			RISCV_ELF_DATA
-+#define ELF_MACHINE_CODE		EM_RISCV
-+#define ELF_MAXPAGESIZE			0x2000
-+#define ELF_COMMONPAGESIZE		0x2000
-+
 +#define TARGET_LITTLE_SYM		riscv_elfNN_vec
 +#define TARGET_LITTLE_NAME		"elfNN-littleriscv"
 +
 +#define elf_backend_reloc_type_class	     riscv_reloc_type_class
 +
-+#define bfd_elfNN_bfd_reloc_name_lookup      riscv_reloc_name_lookup
++#define bfd_elfNN_bfd_reloc_name_lookup	     riscv_reloc_name_lookup
 +#define bfd_elfNN_bfd_link_hash_table_create riscv_elf_link_hash_table_create
 +#define bfd_elfNN_bfd_reloc_type_lookup	     riscv_reloc_type_lookup
 +#define bfd_elfNN_bfd_merge_private_bfd_data \
@@ -3062,31 +3085,31 @@ diff -urN empty/bfd/elfnn-riscv.c binutils-2.25/bfd/elfnn-riscv.c
 +#define elf_backend_finish_dynamic_symbol    riscv_elf_finish_dynamic_symbol
 +#define elf_backend_finish_dynamic_sections  riscv_elf_finish_dynamic_sections
 +#define elf_backend_gc_mark_hook	     riscv_elf_gc_mark_hook
-+#define elf_backend_gc_sweep_hook            riscv_elf_gc_sweep_hook
++#define elf_backend_gc_sweep_hook	     riscv_elf_gc_sweep_hook
 +#define elf_backend_plt_sym_val		     riscv_elf_plt_sym_val
-+#define elf_info_to_howto_rel                NULL
-+#define elf_info_to_howto                    riscv_info_to_howto_rela
-+#define bfd_elfNN_bfd_relax_section          _bfd_riscv_relax_section
-+
-+#define elf_backend_init_index_section	_bfd_elf_init_1_index_section
-+
-+#define elf_backend_can_gc_sections 1
-+#define elf_backend_can_refcount 1
-+#define elf_backend_want_got_plt 1
-+#define elf_backend_plt_readonly 1
-+#define elf_backend_plt_alignment 4
-+#define elf_backend_want_plt_sym 1
-+#define elf_backend_got_header_size (ARCH_SIZE / 8)
-+#define elf_backend_rela_normal 1
-+#define elf_backend_default_execstack 0
++#define elf_info_to_howto_rel		     NULL
++#define elf_info_to_howto		     riscv_info_to_howto_rela
++#define bfd_elfNN_bfd_relax_section	     _bfd_riscv_relax_section
++
++#define elf_backend_init_index_section	     _bfd_elf_init_1_index_section
++
++#define elf_backend_can_gc_sections	1
++#define elf_backend_can_refcount	1
++#define elf_backend_want_got_plt	1
++#define elf_backend_plt_readonly	1
++#define elf_backend_plt_alignment	4
++#define elf_backend_want_plt_sym	1
++#define elf_backend_got_header_size	(ARCH_SIZE / 8)
++#define elf_backend_rela_normal		1
++#define elf_backend_default_execstack	0
 +
 +#include "elfNN-target.h"
-diff -urN empty/bfd/elfxx-riscv.c binutils-2.25/bfd/elfxx-riscv.c
---- binutils-2.25/bfd/elfxx-riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/bfd/elfxx-riscv.c	2015-07-18 00:02:36.218287546 +0200
-@@ -0,0 +1,765 @@
+diff -urN empty/bfd/elfxx-riscv.c binutils-2.26/bfd/elfxx-riscv.c
+--- empty/bfd/elfxx-riscv.c	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/bfd/elfxx-riscv.c	2016-04-03 10:33:12.062126369 +0800
+@@ -0,0 +1,814 @@
 +/* RISC-V-specific support for ELF.
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
 +   Based on TILE-Gx and MIPS targets.
@@ -3104,9 +3127,8 @@ diff -urN empty/bfd/elfxx-riscv.c binutils-2.25/bfd/elfxx-riscv.c
 +   GNU General Public License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the Free Software
-+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-+   MA 02110-1301, USA.  */
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +#include "sysdep.h"
 +#include "bfd.h"
@@ -3125,640 +3147,688 @@ diff -urN empty/bfd/elfxx-riscv.c binutils-2.25/bfd/elfxx-riscv.c
 +static reloc_howto_type howto_table[] =
 +{
 +  /* No relocation.  */
-+  HOWTO (R_RISCV_NONE,		/* type */
-+	 0,			/* rightshift */
-+	 0,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 0,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_NONE",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0,			/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_NONE,			/* type */
++	 0,				/* rightshift */
++	 3,				/* size */
++	 0,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_NONE",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 0,				/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 32 bit relocation.  */
-+  HOWTO (R_RISCV_32,		/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_32",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0xffffffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_32,			/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_32",			/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 0xffffffff,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 64 bit relocation.  */
-+  HOWTO (R_RISCV_64,		/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_64",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_64,			/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 64,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_64",			/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* Relocation against a local symbol in a shared object.  */
-+  HOWTO (R_RISCV_RELATIVE,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_RELATIVE",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0xffffffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+  HOWTO (R_RISCV_COPY,		/* type */
-+	 0,			/* rightshift */
-+	 0,			/* this one is variable size */
-+	 0,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_bitfield, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
++  HOWTO (R_RISCV_RELATIVE,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_RELATIVE",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 0xffffffff,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  HOWTO (R_RISCV_COPY,			/* type */
++	 0,				/* rightshift */
++	 0,				/* this one is variable size */
++	 0,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_bitfield,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
 +	 "R_RISCV_COPY",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0x0,         		/* src_mask */
-+	 0x0,		        /* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+  HOWTO (R_RISCV_JUMP_SLOT,	/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_bitfield, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_JUMP_SLOT",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0x0,         		/* src_mask */
-+	 0x0,		        /* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++	 FALSE,				/* partial_inplace */
++	 0x0,         			/* src_mask */
++	 0x0,		        	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  HOWTO (R_RISCV_JUMP_SLOT,		/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 64,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_bitfield,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_JUMP_SLOT",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0x0,         			/* src_mask */
++	 0x0,		        	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* Dynamic TLS relocations.  */
-+  HOWTO (R_RISCV_TLS_DTPMOD32,	/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_RISCV_TLS_DTPMOD32", /* name */
-+	 FALSE,			/* partial_inplace */
-+	 MINUS_ONE,		/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+  HOWTO (R_RISCV_TLS_DTPMOD64,	/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_RISCV_TLS_DTPMOD64", /* name */
-+	 FALSE,			/* partial_inplace */
-+	 MINUS_ONE,		/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+  HOWTO (R_RISCV_TLS_DTPREL32,	/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
++  HOWTO (R_RISCV_TLS_DTPMOD32,		/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc, 	/* special_function */
++	 "R_RISCV_TLS_DTPMOD32",	/* name */
++	 FALSE,				/* partial_inplace */
++	 MINUS_ONE,			/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  HOWTO (R_RISCV_TLS_DTPMOD64,		/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 64,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc, 	/* special_function */
++	 "R_RISCV_TLS_DTPMOD64",	/* name */
++	 FALSE,				/* partial_inplace */
++	 MINUS_ONE,			/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  HOWTO (R_RISCV_TLS_DTPREL32,		/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc, 	/* special_function */
 +	 "R_RISCV_TLS_DTPREL32",	/* name */
-+	 TRUE,			/* partial_inplace */
-+	 MINUS_ONE,		/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+  HOWTO (R_RISCV_TLS_DTPREL64,	/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
++	 TRUE,				/* partial_inplace */
++	 MINUS_ONE,			/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  HOWTO (R_RISCV_TLS_DTPREL64,		/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 64,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc, 	/* special_function */
 +	 "R_RISCV_TLS_DTPREL64",	/* name */
-+	 TRUE,			/* partial_inplace */
-+	 MINUS_ONE,		/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+  HOWTO (R_RISCV_TLS_TPREL32,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_RISCV_TLS_TPREL32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 MINUS_ONE,		/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+  HOWTO (R_RISCV_TLS_TPREL64,	/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_RISCV_TLS_TPREL64",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 MINUS_ONE,		/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
++	 TRUE,				/* partial_inplace */
++	 MINUS_ONE,			/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  HOWTO (R_RISCV_TLS_TPREL32,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc, 	/* special_function */
++	 "R_RISCV_TLS_TPREL32",		/* name */
++	 FALSE,				/* partial_inplace */
++	 MINUS_ONE,			/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  HOWTO (R_RISCV_TLS_TPREL64,		/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 64,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc, 	/* special_function */
++	 "R_RISCV_TLS_TPREL64",		/* name */
++	 FALSE,				/* partial_inplace */
++	 MINUS_ONE,			/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  /* Reserved for future relocs that the dynamic linker must understand.  */
 +  EMPTY_HOWTO (12),
 +  EMPTY_HOWTO (13),
 +  EMPTY_HOWTO (14),
 +  EMPTY_HOWTO (15),
 +
 +  /* 12-bit PC-relative branch offset.  */
-+  HOWTO (R_RISCV_BRANCH,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_signed, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_BRANCH",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_SBTYPE_IMM(-1U),/* dst_mask */
-+	 TRUE),			/* pcrel_offset */
++  HOWTO (R_RISCV_BRANCH,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_signed,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_BRANCH",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_SBTYPE_IMM (-1U),	/* dst_mask */
++	 TRUE),				/* pcrel_offset */
 +
 +  /* 20-bit PC-relative jump offset.  */
-+  HOWTO (R_RISCV_JAL,		/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+				/* This needs complex overflow
-+				   detection, because the upper 36
-+				   bits must match the PC + 4.  */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_JAL",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UJTYPE_IMM(-1U),	/* dst_mask */
-+	 TRUE),		/* pcrel_offset */
++  HOWTO (R_RISCV_JAL,			/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++					/* This needs complex overflow
++					   detection, because the upper 36
++					   bits must match the PC + 4.  */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_JAL",			/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UJTYPE_IMM (-1U),	/* dst_mask */
++	 TRUE),				/* pcrel_offset */
 +
 +  /* 32-bit PC-relative function call (AUIPC/JALR).  */
-+  HOWTO (R_RISCV_CALL,		/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_CALL",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UTYPE_IMM(-1U) | ((bfd_vma) ENCODE_ITYPE_IMM(-1U) << 32),	/* dst_mask */
-+	 TRUE),			/* pcrel_offset */
++  HOWTO (R_RISCV_CALL,			/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 64,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_CALL",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UTYPE_IMM (-1U) | ((bfd_vma) ENCODE_ITYPE_IMM (-1U) << 32),
++					/* dst_mask */
++	 TRUE),				/* pcrel_offset */
 +
 +  /* 32-bit PC-relative function call (AUIPC/JALR).  */
-+  HOWTO (R_RISCV_CALL_PLT,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_CALL_PLT",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UTYPE_IMM(-1U) | ((bfd_vma) ENCODE_ITYPE_IMM(-1U) << 32),	/* dst_mask */
-+	 TRUE),			/* pcrel_offset */
++  HOWTO (R_RISCV_CALL_PLT,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 64,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_CALL_PLT",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UTYPE_IMM (-1U) | ((bfd_vma) ENCODE_ITYPE_IMM (-1U) << 32),
++					/* dst_mask */
++	 TRUE),				/* pcrel_offset */
 +
 +  /* High 20 bits of 32-bit PC-relative GOT access.  */
-+  HOWTO (R_RISCV_GOT_HI20,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_GOT_HI20",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UTYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_GOT_HI20,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_GOT_HI20",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UTYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* High 20 bits of 32-bit PC-relative TLS IE GOT access.  */
-+  HOWTO (R_RISCV_TLS_GOT_HI20,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
++  HOWTO (R_RISCV_TLS_GOT_HI20,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
 +	 "R_RISCV_TLS_GOT_HI20",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UTYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UTYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* High 20 bits of 32-bit PC-relative TLS GD GOT reference.  */
-+  HOWTO (R_RISCV_TLS_GD_HI20,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_TLS_GD_HI20",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UTYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_TLS_GD_HI20,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_TLS_GD_HI20",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UTYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* High 20 bits of 32-bit PC-relative reference.  */
-+  HOWTO (R_RISCV_PCREL_HI20,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_PCREL_HI20",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UTYPE_IMM(-1U),	/* dst_mask */
-+	 TRUE),			/* pcrel_offset */
++  HOWTO (R_RISCV_PCREL_HI20,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_PCREL_HI20",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UTYPE_IMM (-1U),	/* dst_mask */
++	 TRUE),				/* pcrel_offset */
 +
 +  /* Low 12 bits of a 32-bit PC-relative load or add.  */
-+  HOWTO (R_RISCV_PCREL_LO12_I,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_PCREL_LO12_I",/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_ITYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_PCREL_LO12_I,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_PCREL_LO12_I",	/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_ITYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* Low 12 bits of a 32-bit PC-relative store.  */
-+  HOWTO (R_RISCV_PCREL_LO12_S,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_PCREL_LO12_S",/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_STYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_PCREL_LO12_S,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_PCREL_LO12_S",	/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_STYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* High 20 bits of 32-bit absolute address.  */
-+  HOWTO (R_RISCV_HI20,		/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
++  HOWTO (R_RISCV_HI20,			/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
 +	 "R_RISCV_HI20",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UTYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UTYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* High 12 bits of 32-bit load or add.  */
-+  HOWTO (R_RISCV_LO12_I,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_LO12_I",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_ITYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_LO12_I,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_LO12_I",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_ITYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* High 12 bits of 32-bit store.  */
-+  HOWTO (R_RISCV_LO12_S,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_LO12_S",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_STYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_LO12_S,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_LO12_S",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_STYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* High 20 bits of TLS LE thread pointer offset.  */
-+  HOWTO (R_RISCV_TPREL_HI20,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,	/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_signed, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_RISCV_TPREL_HI20",	/* name */
-+	 TRUE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_UTYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_TPREL_HI20,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_signed,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_TPREL_HI20",		/* name */
++	 TRUE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_UTYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* Low 12 bits of TLS LE thread pointer offset for loads and adds.  */
-+  HOWTO (R_RISCV_TPREL_LO12_I,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_signed, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_RISCV_TPREL_LO12_I",/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_ITYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_TPREL_LO12_I,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_signed,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_TPREL_LO12_I",	/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_ITYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* Low 12 bits of TLS LE thread pointer offset for stores.  */
-+  HOWTO (R_RISCV_TPREL_LO12_S,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_signed, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_RISCV_TPREL_LO12_S",/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_STYPE_IMM(-1U),	/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_TPREL_LO12_S,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_signed,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_TPREL_LO12_S",	/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_STYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* TLS LE thread pointer usage.  */
-+  HOWTO (R_RISCV_TPREL_ADD,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont,/* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_RISCV_TPREL_ADD",	/* name */
-+	 TRUE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0,			/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_TPREL_ADD,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_TPREL_ADD",		/* name */
++	 TRUE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 0,				/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 8-bit in-place addition, for local label subtraction.  */
-+  HOWTO (R_RISCV_ADD8,		/* type */
-+	 0,			/* rightshift */
-+	 0,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_ADD8",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_ADD8,			/* type */
++	 0,				/* rightshift */
++	 0,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_ADD8",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 16-bit in-place addition, for local label subtraction.  */
-+  HOWTO (R_RISCV_ADD16,		/* type */
-+	 0,			/* rightshift */
-+	 1,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 16,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_ADD16",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_ADD16,			/* type */
++	 0,				/* rightshift */
++	 1,				/* size */
++	 16,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_ADD16",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 32-bit in-place addition, for local label subtraction.  */
-+  HOWTO (R_RISCV_ADD32,		/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_ADD32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_ADD32,			/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_ADD32",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 64-bit in-place addition, for local label subtraction.  */
-+  HOWTO (R_RISCV_ADD64,		/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_ADD64",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_ADD64,			/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 64,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_ADD64",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 8-bit in-place addition, for local label subtraction.  */
-+  HOWTO (R_RISCV_SUB8,		/* type */
-+	 0,			/* rightshift */
-+	 0,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 8,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_SUB8",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_SUB8,			/* type */
++	 0,				/* rightshift */
++	 0,				/* size */
++	 8,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_SUB8",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 16-bit in-place addition, for local label subtraction.  */
-+  HOWTO (R_RISCV_SUB16,		/* type */
-+	 0,			/* rightshift */
-+	 1,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 16,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_SUB16",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_SUB16,			/* type */
++	 0,				/* rightshift */
++	 1,				/* size */
++	 16,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_SUB16",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 32-bit in-place addition, for local label subtraction.  */
-+  HOWTO (R_RISCV_SUB32,		/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_SUB32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_SUB32,			/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_SUB32",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* 64-bit in-place addition, for local label subtraction.  */
-+  HOWTO (R_RISCV_SUB64,		/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 64,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_SUB64",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 MINUS_ONE,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_SUB64,			/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 64,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_SUB64",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 MINUS_ONE,			/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* GNU extension to record C++ vtable hierarchy */
-+  HOWTO (R_RISCV_GNU_VTINHERIT, /* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 0,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont,/* complain_on_overflow */
-+	 NULL,			/* special_function */
-+	 "R_RISCV_GNU_VTINHERIT", /* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0,			/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_GNU_VTINHERIT,		/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 0,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 NULL,				/* special_function */
++	 "R_RISCV_GNU_VTINHERIT",	/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 0,				/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* GNU extension to record C++ vtable member usage */
-+  HOWTO (R_RISCV_GNU_VTENTRY,	/* type */
-+	 0,			/* rightshift */
-+	 4,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 0,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont,/* complain_on_overflow */
-+	 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
-+	 "R_RISCV_GNU_VTENTRY",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0,			/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
++  HOWTO (R_RISCV_GNU_VTENTRY,		/* type */
++	 0,				/* rightshift */
++	 4,				/* size */
++	 0,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 _bfd_elf_rel_vtable_reloc_fn,	/* special_function */
++	 "R_RISCV_GNU_VTENTRY",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 0,				/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +
 +  /* Indicates an alignment statement.  The addend field encodes how many
 +     bytes of NOPs follow the statement.  The desired alignment is the
 +     addend rounded up to the next power of two.  */
-+  HOWTO (R_RISCV_ALIGN,		/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 0,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_ALIGN",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0,			/* dst_mask */
-+	 TRUE),			/* pcrel_offset */
++  HOWTO (R_RISCV_ALIGN,			/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 0,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_ALIGN",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 0,				/* dst_mask */
++	 TRUE),				/* pcrel_offset */
 +
 +  /* 8-bit PC-relative branch offset.  */
-+  HOWTO (R_RISCV_RVC_BRANCH,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_signed, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_RVC_BRANCH",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_RVC_B_IMM(-1U),	/* dst_mask */
-+	 TRUE),			/* pcrel_offset */
++  HOWTO (R_RISCV_RVC_BRANCH,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_signed,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_RVC_BRANCH",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_RVC_B_IMM (-1U),	/* dst_mask */
++	 TRUE),				/* pcrel_offset */
 +
 +  /* 11-bit PC-relative jump offset.  */
-+  HOWTO (R_RISCV_RVC_JUMP,	/* type */
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 TRUE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+				/* This needs complex overflow
-+				   detection, because the upper 36
-+				   bits must match the PC + 4.  */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_RISCV_RVC_JUMP",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 ENCODE_RVC_J_IMM(-1U),	/* dst_mask */
-+	 TRUE),		/* pcrel_offset */
++  HOWTO (R_RISCV_RVC_JUMP,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 TRUE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++					/* This needs complex overflow
++					   detection, because the upper 36
++					   bits must match the PC + 4.  */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_RVC_JUMP",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_RVC_J_IMM (-1U),	/* dst_mask */
++	 TRUE),				/* pcrel_offset */
++
++  /* High 6 bits of 18-bit absolute address.  */
++  HOWTO (R_RISCV_RVC_LUI,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_RVC_LUI",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_RVC_IMM (-1U),		/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  /* High 12 bits of 32-bit load or add.  */
++  HOWTO (R_RISCV_GPREL_I,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_GPREL_I",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_ITYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
++
++  /* High 12 bits of 32-bit store.  */
++  HOWTO (R_RISCV_GPREL_S,		/* type */
++	 0,				/* rightshift */
++	 2,				/* size */
++	 32,				/* bitsize */
++	 FALSE,				/* pc_relative */
++	 0,				/* bitpos */
++	 complain_overflow_dont,	/* complain_on_overflow */
++	 bfd_elf_generic_reloc,		/* special_function */
++	 "R_RISCV_GPREL_S",		/* name */
++	 FALSE,				/* partial_inplace */
++	 0,				/* src_mask */
++	 ENCODE_STYPE_IMM (-1U),	/* dst_mask */
++	 FALSE),			/* pcrel_offset */
 +};
 +
 +/* A mapping from BFD reloc types to RISC-V ELF reloc types.  */
@@ -3808,13 +3878,16 @@ diff -urN empty/bfd/elfxx-riscv.c binutils-2.25/bfd/elfxx-riscv.c
 +  { BFD_RELOC_RISCV_ALIGN, R_RISCV_ALIGN },
 +  { BFD_RELOC_RISCV_RVC_BRANCH, R_RISCV_RVC_BRANCH },
 +  { BFD_RELOC_RISCV_RVC_JUMP, R_RISCV_RVC_JUMP },
++  { BFD_RELOC_RISCV_RVC_LUI, R_RISCV_RVC_LUI },
++  { BFD_RELOC_RISCV_GPREL_I, R_RISCV_GPREL_I },
++  { BFD_RELOC_RISCV_GPREL_S, R_RISCV_GPREL_S },
 +};
 +
 +/* Given a BFD reloc type, return a howto structure.  */
 +
 +reloc_howto_type *
 +riscv_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-+				 bfd_reloc_code_real_type code)
++			 bfd_reloc_code_real_type code)
 +{
 +  unsigned int i;
 +
@@ -3827,8 +3900,7 @@ diff -urN empty/bfd/elfxx-riscv.c binutils-2.25/bfd/elfxx-riscv.c
 +}
 +
 +reloc_howto_type *
-+riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-+				 const char *r_name)
++riscv_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
 +{
 +  unsigned int i;
 +
@@ -3842,20 +3914,20 @@ diff -urN empty/bfd/elfxx-riscv.c binutils-2.25/bfd/elfxx-riscv.c
 +reloc_howto_type *
 +riscv_elf_rtype_to_howto (unsigned int r_type)
 +{
-+  if ((unsigned int)r_type >= ARRAY_SIZE (howto_table))
++  if (r_type >= ARRAY_SIZE (howto_table))
 +    {
-+      (*_bfd_error_handler)(_("unrecognized relocation (0x%x)"), r_type);
++      (*_bfd_error_handler) (_("unrecognized relocation (0x%x)"), r_type);
 +      bfd_set_error (bfd_error_bad_value);
 +      return NULL;
 +    }
 +  return &howto_table[r_type];
 +}
-diff -urN empty/bfd/elfxx-riscv.h binutils-2.25/bfd/elfxx-riscv.h
---- binutils-2.25/bfd/elfxx-riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/bfd/elfxx-riscv.h	2015-07-18 00:02:36.218287546 +0200
-@@ -0,0 +1,34 @@
+diff -urN empty/bfd/elfxx-riscv.h binutils-2.26/bfd/elfxx-riscv.h
+--- empty/bfd/elfxx-riscv.h	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/bfd/elfxx-riscv.h	2016-04-03 10:12:57.122276559 +0800
+@@ -0,0 +1,33 @@
 +/* RISC-V ELF specific backend routines.
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
 +   Based on MIPS target.
@@ -3873,9 +3945,8 @@ diff -urN empty/bfd/elfxx-riscv.h binutils-2.25/bfd/elfxx-riscv.h
 +   GNU General Public License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the Free Software
-+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-+   MA 02110-1301, USA.  */
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +#include "elf/common.h"
 +#include "elf/internal.h"
@@ -3888,12 +3959,12 @@ diff -urN empty/bfd/elfxx-riscv.h binutils-2.25/bfd/elfxx-riscv.h
 +
 +extern reloc_howto_type *
 +riscv_elf_rtype_to_howto (unsigned int r_type);
-diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
---- binutils-2.25/gas/config/tc-riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/gas/config/tc-riscv.c	2015-07-18 00:02:36.222287541 +0200
-@@ -0,0 +1,2484 @@
+diff -urN empty/gas/config/tc-riscv.c binutils-2.26/gas/config/tc-riscv.c
+--- empty/gas/config/tc-riscv.c	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/gas/config/tc-riscv.c	2016-04-09 10:50:33.576657106 +0800
+@@ -0,0 +1,2434 @@
 +/* tc-riscv.c -- RISC-V assembler
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
 +   Based on MIPS target.
@@ -3911,9 +3982,8 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +   GNU General Public License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with GAS; see the file COPYING.  If not, write to the Free
-+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-+   02110-1301, USA.  */
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +#include "as.h"
 +#include "config.h"
@@ -3960,7 +4030,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +#define LOAD_ADDRESS_INSN (xlen == 64 ? "ld" : "lw")
 +#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
 +
-+unsigned elf_flags = 0;
++static unsigned elf_flags = 0;
 +
 +/* This is the set of options which the .option pseudo-op may modify.  */
 +
@@ -3976,134 +4046,149 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  0,	/* rvc */
 +};
 +
++static void
++riscv_set_rvc (bfd_boolean rvc_value)
++{
++  if (rvc_value)
++    elf_flags |= EF_RISCV_RVC;
++
++  riscv_opts.rvc = rvc_value;
++}
++
 +struct riscv_subset
 +{
-+  const char* name;
++  const char *name;
 +  int version_major;
 +  int version_minor;
 +
-+  struct riscv_subset* next;
++  struct riscv_subset *next;
 +};
 +
-+static struct riscv_subset* riscv_subsets;
++static struct riscv_subset *riscv_subsets;
 +
-+static int
-+riscv_subset_supports(const char* feature)
++static bfd_boolean
++riscv_subset_supports (const char *feature)
 +{
-+  struct riscv_subset* s;
-+  bfd_boolean rv64_insn;
++  struct riscv_subset *s;
++  char *p;
++  unsigned xlen_required = strtoul (feature, &p, 10);
 +
-+  if ((rv64_insn = !strncmp(feature, "64", 2)) || !strncmp(feature, "32", 2))
-+    {
-+      if ((xlen == 64) != rv64_insn)
-+        return 0;
-+      feature += 2;
-+    }
++  if (xlen_required && xlen != xlen_required)
++    return FALSE;
 +
 +  for (s = riscv_subsets; s != NULL; s = s->next)
-+    if (strcmp(s->name, feature) == 0)
++    if (strcasecmp (s->name, p) == 0)
 +      /* FIXME: once we support version numbers:
-+         return major == s->version_major && minor <= s->version_minor; */
-+      return 1;
++	 return major == s->version_major && minor <= s->version_minor; */
++      return TRUE;
 +
-+  return 0;
++  return FALSE;
 +}
 +
 +static void
-+riscv_add_subset (const char* subset)
++riscv_add_subset (const char *subset)
 +{
-+  struct riscv_subset* s = xmalloc(sizeof(struct riscv_subset));
-+  s->name = xstrdup(subset);
-+  s->version_major = 1;
++  struct riscv_subset *s = xmalloc (sizeof *s);
++  s->name = xstrdup (subset);
++  s->version_major = 2;
 +  s->version_minor = 0;
 +  s->next = riscv_subsets;
 +  riscv_subsets = s;
 +}
 +
++/* Set which ISA and extensions are available.  Formally, ISA strings must
++   begin with RV32 or RV64, but we allow the prefix to be omitted.
++
++   FIXME: Version numbers are not supported yet.  */
 +static void
-+riscv_set_arch (const char* arg)
-+{
-+  /* Formally, ISA subset names begin with RV, RV32, or RV64, but we allow the
-+     prefix to be omitted.  We also allow all-lowercase names if version
-+     numbers and eXtensions are omitted (i.e. only some combination of imafd
-+     is supported in this case).
-+     
-+     FIXME: Version numbers are not supported yet. */
-+  const char* subsets = "IMAFDC";
-+  const char* extension = NULL;
-+  const char* p;
++riscv_set_arch (const char *arg)
++{
++  char *uppercase = xstrdup (arg);
++  char *p = uppercase;
++  const char *all_subsets = "IMAFDC";
++  const char *extension = NULL;
 +  int rvc = 0;
-+  
-+  for (p = arg; *p; p++)
-+    if (!ISLOWER(*p) || strchr(subsets, TOUPPER(*p)) == NULL)
-+      break;
++  int i;
 +
-+  if (!*p)
-+    {
-+      /* Legal all-lowercase name. */
-+      for (p = arg; *p; p++)
-+	{
-+	  char subset[2] = {TOUPPER(*p), 0};
-+	  riscv_add_subset(subset);
-+	}
-+      return;
-+    }
++  for (i = 0; uppercase[i]; i++)
++    uppercase[i] = TOUPPER (uppercase[i]);
 +
-+  if (strncmp(arg, "RV32", 4) == 0)
++  if (strncmp (p, "RV32", 4) == 0)
 +    {
 +      xlen = 32;
-+      arg += 4;
++      p += 4;
 +    }
-+  else if (strncmp(arg, "RV64", 4) == 0)
++  else if (strncmp (p, "RV64", 4) == 0)
 +    {
 +      xlen = 64;
-+      arg += 4;
++      p += 4;
 +    }
-+  else if (strncmp(arg, "RV", 2) == 0)
-+    arg += 2;
++  else if (strncmp (p, "RV", 2) == 0)
++    p += 2;
++
++  switch (*p)
++    {
++      case 'I':
++	break;
 +
-+  if (*arg && *arg != 'I')
-+    as_fatal("`I' must be the first ISA subset name specified (got %c)", *arg);
++      case 'G':
++	p++;
++	/* Fall through.  */
 +
-+  for (p = arg; *p; )
++      case '\0':
++	for (i = 0; all_subsets[i] != '\0'; i++)
++	  {
++	    const char subset[] = {all_subsets[i], '\0'};
++	    riscv_add_subset (subset);
++	  }
++	break;
++
++      default:
++	as_fatal ("`I' must be the first ISA subset name specified (got %c)",
++		  *p);
++    }
++
++  while (*p)
 +    {
 +      if (*p == 'X')
 +	{
-+	  char *subset = xstrdup(p), *q = subset;
++	  char *subset = xstrdup (p), *q = subset;
 +
-+	  do
-+	    q++;
-+	  while (ISLOWER(*q));
-+	  *q = 0;
++	  while (*++q != '\0' && *q != '_')
++	    ;
++	  *q = '\0';
 +
 +	  if (extension)
-+	    as_bad ("only one eXtension is supported (found %s and %s)",
-+		    extension, subset);
++	    as_fatal ("only one eXtension is supported (found %s and %s)",
++		      extension, subset);
 +	  extension = subset;
-+	  EF_SET_RISCV_EXT (elf_flags, riscv_elf_name_to_flag (subset));
-+
 +	  riscv_add_subset (subset);
 +	  p += strlen (subset);
 +	  free (subset);
 +	}
-+      else if (strchr(subsets, *p) != NULL)
++      else if (*p == '_')
++	p++;
++      else if ((all_subsets = strchr (all_subsets, *p)) != NULL)
 +	{
-+	  char subset[2] = {*p, 0};
++	  const char subset[] = {*p, 0};
 +	  riscv_add_subset (subset);
 +	  if (*p == 'C')
 +	    rvc = 1;
++	  all_subsets++;
 +	  p++;
 +	}
 +      else
-+	as_fatal("unsupported ISA subset %c", *p);
++	as_fatal ("unsupported ISA subset %c", *p);
 +    }
 +
 +  if (rvc)
 +    /* Override -m[no-]rvc setting if C was explicitly listed.  */
-+    riscv_opts.rvc = 1;
++    riscv_set_rvc (TRUE);
 +  else
 +    /* Add RVC anyway.  -m[no-]rvc toggles its availability.  */
 +    riscv_add_subset ("C");
++
++  free (uppercase);
 +}
 +
 +/* handle of the OPCODE hash table */
@@ -4133,6 +4218,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +/* or    0d1.2345e12 */
 +const char FLT_CHARS[] = "rRsSfFdDxXpP";
 +
++/* Macros for encoding relaxation state for RVC branches and far jumps.  */
 +#define RELAX_BRANCH_ENCODE(uncond, rvc, length)	\
 +  ((relax_substateT) 					\
 +   (0xc0000000						\
@@ -4149,48 +4235,20 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  (((x) &~ (offsetT) 0x7fffffff) == 0					\
 +   || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
 +
-+#define IS_SEXT_NBIT_NUM(x,n) \
-+  ({ int64_t __tmp = (x); \
-+     __tmp = (__tmp << (64-(n))) >> (64-(n)); \
-+     __tmp == (x); })
-+
 +/* Is the given value a zero-extended 32-bit value?  Or a negated one?  */
 +#define IS_ZEXT_32BIT_NUM(x)						\
 +  (((x) &~ (offsetT) 0xffffffff) == 0					\
 +   || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
 +
-+/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
-+   VALUE << SHIFT.  VALUE is evaluated exactly once.  */
-+#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
-+  (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
-+	      | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
-+
-+/* Extract bits MASK << SHIFT from STRUCT and shift them right
-+   SHIFT places.  */
-+#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
-+  (((STRUCT) >> (SHIFT)) & (MASK))
-+
 +/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
-+   INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
++   INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once.  */
 +#define INSERT_OPERAND(FIELD, INSN, VALUE) \
 +  INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
 +
-+/* Extract the operand given by FIELD from riscv_cl_insn INSN.  */
-+#define EXTRACT_OPERAND(FIELD, INSN) \
-+  EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
-+
-+/* Determine if an instruction matches an opcode. */
++/* Determine if an instruction matches an opcode.  */
 +#define OPCODE_MATCHES(OPCODE, OP) \
 +  (((OPCODE) & MASK_##OP) == MATCH_##OP)
 +
-+#define INSN_MATCHES(INSN, OP) \
-+  (((INSN).insn_opcode & MASK_##OP) == MATCH_##OP)
-+
-+/* Prototypes for static functions.  */
-+
-+#define internalError()							\
-+    as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
-+
 +static char *expr_end;
 +
 +/* The default target format to use.  */
@@ -4227,7 +4285,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +install_insn (const struct riscv_cl_insn *insn)
 +{
 +  char *f = insn->frag->fr_literal + insn->where;
-+  md_number_to_chars (f, insn->insn_opcode, insn_length(insn));
++  md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
 +}
 +
 +/* Move INSN to offset WHERE in FRAG.  Adjust the fixups accordingly
@@ -4266,7 +4324,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +}
 +
 +/* Compute the length of a branch sequence, and adjust the stored length
-+   accordingly.  If FRAGP is NULL, the worst-case length is returned. */
++   accordingly.  If FRAGP is NULL, the worst-case length is returned.  */
 +
 +static int
 +relaxed_branch_length (fragS *fragp, asection *sec, int update)
@@ -4295,6 +4353,8 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	length = 2;
 +      else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
 +	length = 4;
++      else if (!jump && rvc)
++	length = 6;
 +    }
 +
 +  if (update)
@@ -4312,14 +4372,12 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  RCLASS_GPR,
 +  RCLASS_FPR,
 +  RCLASS_CSR,
-+  RCLASS_VEC_GPR,
-+  RCLASS_VEC_FPR,
 +  RCLASS_MAX
 +};
 +
 +static struct hash_control *reg_names_hash = NULL;
 +
-+#define ENCODE_REG_HASH(cls, n) (void*)(uintptr_t)((n)*RCLASS_MAX + (cls) + 1)
++#define ENCODE_REG_HASH(cls, n) (void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)
 +#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
 +#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
 +
@@ -4328,6 +4386,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +{
 +  void *hash = ENCODE_REG_HASH (class, n);
 +  const char *retval = hash_insert (reg_names_hash, name, hash);
++
 +  if (retval != NULL)
 +    as_fatal (_("internal error: can't hash `%s': %s"), name, retval);
 +}
@@ -4336,6 +4395,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
 +{
 +  unsigned i;
++
 +  for (i = 0; i < n; i++)
 +    hash_reg_name (class, names[i], i);
 +}
@@ -4378,17 +4438,17 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +}
 +
 +static int
-+arg_lookup(char **s, const char* const* array, size_t size, unsigned *regnop)
++arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
 +{
-+  const char *p = strchr(*s, ',');
-+  size_t i, len = p ? (size_t)(p - *s) : strlen(*s);
-+  
++  const char *p = strchr (*s, ',');
++  size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
++
 +  for (i = 0; i < size; i++)
-+    if (array[i] != NULL && strncmp(array[i], *s, len) == 0)
++    if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
 +      {
-+        *regnop = i;
-+        *s += len;
-+        return 1;
++	*regnop = i;
++	*s += len;
++	return 1;
 +      }
 +
 +  return 0;
@@ -4403,7 +4463,8 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  const char *p = opc->args;
 +  char c;
 +  insn_t used_bits = opc->mask;
-+  insn_t required_bits = (uint64_t)-1 >> (64 - 8 * riscv_insn_length (opc->match));
++  int insn_width = 8 * riscv_insn_length (opc->match);
++  insn_t required_bits = ~0ULL >> (64 - insn_width);
 +
 +  if ((used_bits & opc->match) != (opc->match & required_bits))
 +    {
@@ -4418,65 +4479,42 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +      {
 +      /* Xcustom */
 +      case '^':
-+      switch (c = *p++)
-+        {
-+        case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
-+        case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
-+        case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
-+        case 'j': USE_BITS (OP_MASK_CUSTOM_IMM, OP_SH_CUSTOM_IMM); break;
-+        }
-+      break;
-+      /* Xhwacha */
-+      case '#':
-+      switch (c = *p++)
-+        {
-+        case 'g': USE_BITS (OP_MASK_IMMNGPR, OP_SH_IMMNGPR); break;
-+        case 'f': USE_BITS (OP_MASK_IMMNFPR, OP_SH_IMMNFPR); break;
-+        case 'n': USE_BITS (OP_MASK_IMMSEGNELM, OP_SH_IMMSEGNELM); break;
-+        case 'd': USE_BITS (OP_MASK_VRD, OP_SH_VRD); break;
-+        case 's': USE_BITS (OP_MASK_VRS, OP_SH_VRS); break;
-+        case 't': USE_BITS (OP_MASK_VRT, OP_SH_VRT); break;
-+        case 'r': USE_BITS (OP_MASK_VRR, OP_SH_VRR); break;
-+        case 'D': USE_BITS (OP_MASK_VFD, OP_SH_VFD); break;
-+        case 'S': USE_BITS (OP_MASK_VFS, OP_SH_VFS); break;
-+        case 'T': USE_BITS (OP_MASK_VFT, OP_SH_VFT); break;
-+        case 'R': USE_BITS (OP_MASK_VFR, OP_SH_VFR); break;
-+
-+        default:
-+          as_bad (_("internal: bad RISC-V opcode (unknown extension operand type `#%c'): %s %s"),
-+                  c, opc->name, opc->args);
-+          return 0;
-+        }
-+      break;
++	switch (c = *p++)
++	  {
++	  case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
++	  case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
++	  case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
++	  case 'j': USE_BITS (OP_MASK_CUSTOM_IMM, OP_SH_CUSTOM_IMM); break;
++	  }
++	break;
 +      case 'C': /* RVC */
 +	switch (c = *p++)
 +	  {
-+	  case 'd': USE_BITS (OP_MASK_CRDS, OP_SH_CRDS); break;
-+	  case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
-+	  case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
-+	  case 'w': break; /* RS1S, constrained to equal RD */
-+	  case 'x': break; /* RS1S, constrained to equal RD */
-+	  case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
-+	  case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
-+	  case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
++	  case 'a': used_bits |= ENCODE_RVC_J_IMM(-1U); break;
 +	  case 'c': break; /* RS1, constrained to equal sp */
-+	  case 'U': break; /* RS2, constrained to equal RD */
-+	  case '<': used_bits |= ENCODE_RVC_IMM(-1U); break;
-+	  case '>': used_bits |= ENCODE_RVC_IMM(-1U); break;
 +	  case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
 +	  case 'j': used_bits |= ENCODE_RVC_IMM(-1U); break;
 +	  case 'k': used_bits |= ENCODE_RVC_LW_IMM(-1U); break;
 +	  case 'l': used_bits |= ENCODE_RVC_LD_IMM(-1U); break;
 +	  case 'm': used_bits |= ENCODE_RVC_LWSP_IMM(-1U); break;
 +	  case 'n': used_bits |= ENCODE_RVC_LDSP_IMM(-1U); break;
++	  case 'p': used_bits |= ENCODE_RVC_B_IMM(-1U); break;
++	  case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
++	  case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
++	  case 'u': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case 'v': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case 'w': break; /* RS1S, constrained to equal RD */
++	  case 'x': break; /* RS2S, constrained to equal RD */
 +	  case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM(-1U); break;
 +	  case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM(-1U); break;
 +	  case 'M': used_bits |= ENCODE_RVC_SWSP_IMM(-1U); break;
 +	  case 'N': used_bits |= ENCODE_RVC_SDSP_IMM(-1U); break;
-+	  case 'u': used_bits |= ENCODE_RVC_IMM(-1U); break;
-+	  case 'v': used_bits |= ENCODE_RVC_IMM(-1U); break;
-+	  case 'a': used_bits |= ENCODE_RVC_J_IMM(-1U); break;
-+	  case 'p': used_bits |= ENCODE_RVC_B_IMM(-1U); break;
++	  case 'U': break; /* RS1, constrained to equal RD */
++	  case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
++	  case '<': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case '>': used_bits |= ENCODE_RVC_IMM(-1U); break;
++	  case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
++	  case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
 +	  default:
 +	    as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
 +		    c, opc->name, opc->args);
@@ -4577,15 +4615,13 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
 +  hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
 +  hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
-+  hash_reg_names (RCLASS_VEC_GPR, riscv_vec_gpr_names, NVGPR);
-+  hash_reg_names (RCLASS_VEC_FPR, riscv_vec_fpr_names, NVFPR);
 +
 +#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
 +#include "opcode/riscv-opc.h"
 +#undef DECLARE_CSR
 +
-+  /* set the default alignment for the text section (2**2) */
-+  record_alignment (text_section, 2);
++  /* Set the default alignment for the text section.  */
++  record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
 +}
 +
 +/* Output an instruction.  IP is the instruction information.
@@ -4626,9 +4662,11 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	      goto append;
 +
 +	    case BFD_RELOC_RISCV_HI20:
-+	      ip->insn_opcode |= ENCODE_UTYPE_IMM (
-+		RISCV_CONST_HIGH_PART (address_expr->X_add_number));
-+	      goto append;
++	      {
++		insn_t imm = RISCV_CONST_HIGH_PART (address_expr->X_add_number);
++		ip->insn_opcode |= ENCODE_UTYPE_IMM (imm);
++		goto append;
++	      }
 +
 +	    case BFD_RELOC_RISCV_LO12_S:
 +	      ip->insn_opcode |= ENCODE_STYPE_IMM (address_expr->X_add_number);
@@ -4650,18 +4688,6 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	ip->fixp = fix_new_exp (ip->frag, ip->where,
 +				bfd_get_reloc_size (howto),
 +				address_expr, FALSE, reloc_type);
-+
-+	/* These relocations can have an addend that won't fit in
-+	   4 octets for 64bit assembly.  */
-+	if (xlen == 64
-+	    && ! howto->partial_inplace
-+	    && (reloc_type == BFD_RELOC_32
-+		|| reloc_type == BFD_RELOC_64
-+		|| reloc_type == BFD_RELOC_CTOR
-+		|| reloc_type == BFD_RELOC_RISCV_HI20
-+		|| reloc_type == BFD_RELOC_RISCV_LO12_I
-+		|| reloc_type == BFD_RELOC_RISCV_LO12_S))
-+	  ip->fixp->fx_no_overflow = 1;
 +    }
 +
 +append:
@@ -4726,7 +4752,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	case ',':
 +	  continue;
 +	default:
-+	  internalError ();
++	  as_fatal (_("internal error: invalid macro"));
 +	}
 +      break;
 +    }
@@ -4736,10 +4762,8 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  append_insn (&insn, ep, r);
 +}
 +
-+/*
-+ * Sign-extend 32-bit mode constants that have bit 31 set and all
-+ * higher bits unset.
-+ */
++/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
++   unset.  */
 +static void
 +normalize_constant_expr (expressionS *ex)
 +{
@@ -4751,6 +4775,19 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +			- 0x80000000);
 +}
 +
++/* Warn if an expression is not a constant.  */
++
++static void
++check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex)
++{
++  if (ex->X_op == O_big)
++    as_bad (_("unsupported large constant"));
++  else if (ex->X_op != O_constant)
++    as_bad (_("Instruction %s requires absolute expression"),
++	    ip->insn_mo->name);
++  normalize_constant_expr (ex);
++}
++
 +static symbolS *
 +make_internal_label (void)
 +{
@@ -4758,10 +4795,10 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +					(valueT) frag_now_fix(), frag_now);
 +}
 +
-+/* Load an entry from the GOT. */
++/* Load an entry from the GOT.  */
 +static void
 +pcrel_access (int destreg, int tempreg, expressionS *ep,
-+	      const char* lo_insn, const char* lo_pattern,
++	      const char *lo_insn, const char *lo_pattern,
 +	      bfd_reloc_code_real_type hi_reloc,
 +	      bfd_reloc_code_real_type lo_reloc)
 +{
@@ -4775,7 +4812,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +}
 +
 +static void
-+pcrel_load (int destreg, int tempreg, expressionS *ep, const char* lo_insn,
++pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
 +	    bfd_reloc_code_real_type hi_reloc,
 +	    bfd_reloc_code_real_type lo_reloc)
 +{
@@ -4783,14 +4820,14 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +}
 +
 +static void
-+pcrel_store (int srcreg, int tempreg, expressionS *ep, const char* lo_insn,
++pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
 +	     bfd_reloc_code_real_type hi_reloc,
 +	     bfd_reloc_code_real_type lo_reloc)
 +{
 +  pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
 +}
 +
-+/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
++/* PC-relative function call using AUIPC/JALR, relaxed to JAL.  */
 +static void
 +riscv_call (int destreg, int tempreg, expressionS *ep,
 +	    bfd_reloc_code_real_type reloc)
@@ -4799,19 +4836,6 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  macro_build (NULL, "jalr", "d,s", destreg, tempreg);
 +}
 +
-+/* Warn if an expression is not a constant.  */
-+
-+static void
-+check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex)
-+{
-+  if (ex->X_op == O_big)
-+    as_bad (_("unsupported large constant"));
-+  else if (ex->X_op != O_constant)
-+    as_bad (_("Instruction %s requires absolute expression"),
-+	    ip->insn_mo->name);
-+  normalize_constant_expr (ex);
-+}
-+
 +/* Load an integer constant into a register.  */
 +
 +static void
@@ -4822,7 +4846,11 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift);
 +  upper.X_add_number -= lower.X_add_number;
 +
-+  gas_assert (ep->X_op == O_constant);
++  if (ep->X_op != O_constant)
++    {
++      as_bad (_("unsupported large constant"));
++      return;
++    }
 +
 +  if (xlen > 32 && !IS_SEXT_32BIT_NUM(ep->X_add_number))
 +    {
@@ -4849,12 +4877,12 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	}
 +
 +      if (lower.X_add_number != 0 || hi_reg == 0)
-+        macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg,
++	macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg,
 +		     BFD_RELOC_RISCV_LO12_I);
 +    }
 +}
 +
-+/* Expand RISC-V assembly macros into one or more instructions. */
++/* Expand RISC-V assembly macros into one or more instructions.  */
 +static void
 +macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
 +       bfd_reloc_code_real_type *imm_reloc)
@@ -4872,7 +4900,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +
 +    case M_LA:
 +    case M_LLA:
-+      /* Load the address of a symbol into a register. */
++      /* Load the address of a symbol into a register.  */
 +      if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
 +	as_bad(_("offset too large"));
 +
@@ -4886,12 +4914,12 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		    BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
-+    case M_LA_TLS_GD: 
++    case M_LA_TLS_GD:
 +      pcrel_load (rd, rd, imm_expr, "addi",
 +		  BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
 +
-+    case M_LA_TLS_IE: 
++    case M_LA_TLS_IE:
 +      pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
 +		  BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
 +      break;
@@ -4971,11 +4999,6 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		   BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
 +      break;
 +
-+    case M_VF:
-+      pcrel_access (0, rs1, imm_expr, "vf", "s,s,q",
-+		    BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
-+      break;
-+
 +    case M_CALL:
 +      riscv_call (rd, rs1, imm_expr, *imm_reloc);
 +      break;
@@ -5172,132 +5195,51 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	  switch (*args)
 +	    {
 +	    case '\0':		/* end of args */
-+	      if (insn->pinfo != INSN_MACRO
-+		  && riscv_insn_length (insn->match) == 2
-+		  && !riscv_opts.rvc)
-+		break;
-+	      if (*s == '\0')
++	      if (insn->pinfo != INSN_MACRO)
 +		{
-+		  error = NULL;
-+		  goto out;
++		  if (!insn->match_func (insn, ip->insn_opcode))
++		    break;
++		  if (riscv_insn_length (insn->match) == 2 && !riscv_opts.rvc)
++		    break;
 +		}
-+	      break;
-+            /* Xcustom */
-+            case '^':
-+            {
-+              unsigned long max = OP_MASK_RD;
-+              my_getExpression (imm_expr, s);
-+              check_absolute_expr (ip, imm_expr);
-+              switch (*++args)
-+                {
-+                case 'j':
-+                  max = OP_MASK_CUSTOM_IMM;
-+                  INSERT_OPERAND (CUSTOM_IMM, *ip, imm_expr->X_add_number);
-+                  break;
-+                case 'd':
-+                  INSERT_OPERAND (RD, *ip, imm_expr->X_add_number);
-+                  break;
-+                case 's':
-+                  INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
-+                  break;
-+                case 't':
-+                  INSERT_OPERAND (RS2, *ip, imm_expr->X_add_number);
-+                  break;
-+                }
-+              imm_expr->X_op = O_absent;
-+              s = expr_end;
-+              if ((unsigned long) imm_expr->X_add_number > max)
-+                  as_warn ("Bad custom immediate (%lu), must be at most %lu",
-+                           (unsigned long)imm_expr->X_add_number, max);
-+              continue;
-+            }
-+
-+            /* Xhwacha */
-+            case '#':
-+              switch ( *++args )
-+                {
-+                case 'g':
-+                  my_getExpression( imm_expr, s );
-+                  /* check_absolute_expr( ip, &imm_expr ); */
-+                  if ((unsigned long) imm_expr->X_add_number > 32 )
-+                    as_warn( _( "Improper ngpr amount (%lu)" ),
-+                             (unsigned long) imm_expr->X_add_number );
-+                  INSERT_OPERAND( IMMNGPR, *ip, imm_expr->X_add_number );
-+                  imm_expr->X_op = O_absent;
-+                  s = expr_end;
-+                  continue;
-+                case 'f':
-+                  my_getExpression( imm_expr, s );
-+                  /* check_absolute_expr( ip, &imm_expr ); */
-+                  if ((unsigned long) imm_expr->X_add_number > 32 )
-+                    as_warn( _( "Improper nfpr amount (%lu)" ),
-+                             (unsigned long) imm_expr->X_add_number );
-+                  INSERT_OPERAND( IMMNFPR, *ip, imm_expr->X_add_number );
-+                  imm_expr->X_op = O_absent;
-+                  s = expr_end;
-+                  continue;
-+                case 'n':
-+                  my_getExpression( imm_expr, s );
-+                  /* check_absolute_expr( ip, &imm_expr ); */
-+                  if ((unsigned long) imm_expr->X_add_number > 8 )
-+                    as_warn( _( "Improper nelm amount (%lu)" ),
-+                             (unsigned long) imm_expr->X_add_number );
-+                  INSERT_OPERAND( IMMSEGNELM, *ip, imm_expr->X_add_number - 1 );
-+                  imm_expr->X_op = O_absent;
-+                  s = expr_end;
-+                  continue;
-+                case 'd':
-+                  if (!reg_lookup( &s, RCLASS_VEC_GPR, &regno ))
-+                    as_bad( _( "Invalid vector register" ) );
-+                  INSERT_OPERAND( VRD, *ip, regno );
-+                  continue;
-+                case 's':
-+                  if (!reg_lookup( &s, RCLASS_VEC_GPR, &regno ))
-+                    as_bad( _( "Invalid vector register" ) );
-+                  INSERT_OPERAND( VRS, *ip, regno );
-+                  continue;
-+                case 't':
-+                  if (!reg_lookup( &s, RCLASS_VEC_GPR, &regno ))
-+                    as_bad( _( "Invalid vector register" ) );
-+                  INSERT_OPERAND( VRT, *ip, regno );
-+                  continue;
-+                case 'r':
-+                  if (!reg_lookup( &s, RCLASS_VEC_GPR, &regno ))
-+                    as_bad( _( "Invalid vector register" ) );
-+                  INSERT_OPERAND( VRR, *ip, regno );
-+                  continue;
-+                case 'D':
-+                  if (!reg_lookup( &s, RCLASS_VEC_FPR, &regno ))
-+                    as_bad( _( "Invalid vector register" ) );
-+                  INSERT_OPERAND( VFD, *ip, regno );
-+                  continue;
-+                case 'S':
-+                  if (!reg_lookup( &s, RCLASS_VEC_FPR, &regno ))
-+                    as_bad( _( "Invalid vector register" ) );
-+                  INSERT_OPERAND( VFS, *ip, regno );
-+                  continue;
-+                case 'T':
-+                  if (!reg_lookup( &s, RCLASS_VEC_FPR, &regno ))
-+                    as_bad( _( "Invalid vector register" ) );
-+                  INSERT_OPERAND( VFT, *ip, regno );
-+                  continue;
-+                case 'R':
-+                  if (!reg_lookup( &s, RCLASS_VEC_FPR, &regno ))
-+                    as_bad( _( "Invalid vector register" ) );
-+                  INSERT_OPERAND( VFR, *ip, regno );
-+                  continue;
-+                }
-+              break;
++	      if (*s != '\0')
++		break;
++	      /* Successful assembly.  */
++	      error = NULL;
++	      goto out;
++	    /* Xcustom */
++	    case '^':
++	      {
++		unsigned long max = OP_MASK_RD;
++		my_getExpression (imm_expr, s);
++		check_absolute_expr (ip, imm_expr);
++		switch (*++args)
++		  {
++		  case 'j':
++		    max = OP_MASK_CUSTOM_IMM;
++		    INSERT_OPERAND (CUSTOM_IMM, *ip, imm_expr->X_add_number);
++		    break;
++		  case 'd':
++		    INSERT_OPERAND (RD, *ip, imm_expr->X_add_number);
++		    break;
++		  case 's':
++		    INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
++		    break;
++		  case 't':
++		    INSERT_OPERAND (RS2, *ip, imm_expr->X_add_number);
++		    break;
++		  }
++		imm_expr->X_op = O_absent;
++		s = expr_end;
++		if ((unsigned long) imm_expr->X_add_number > max)
++		  as_warn ("Bad custom immediate (%lu), must be at most %lu",
++			   (unsigned long)imm_expr->X_add_number, max);
++		continue;
++	      }
 +
 +	    case 'C': /* RVC */
 +	      switch (*++args)
 +		{
-+		case 'd': /* RD x8-x15 */
-+		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
-+		      || !(regno >= 8 && regno <= 15))
-+		    break;
-+		  INSERT_OPERAND (CRDS, *ip, regno % 8);
-+		  continue;
 +		case 's': /* RS1 x8-x15 */
 +		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
 +		      || !(regno >= 8 && regno <= 15))
@@ -5306,7 +5248,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		  continue;
 +		case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15 */
 +		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
-+		      || EXTRACT_OPERAND (CRS1S, *ip) + 8 != regno)
++		      || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
 +		    break;
 +		  continue;
 +		case 't': /* RS2 x8-x15 */
@@ -5317,23 +5259,13 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		  continue;
 +		case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15 */
 +		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
-+		      || EXTRACT_OPERAND (CRS2S, *ip) + 8 != regno)
-+		    break;
-+		  continue;
-+		case 'D': /* RD, nonzero */
-+		  if (!reg_lookup (&s, RCLASS_GPR, &regno) || regno == 0)
++		      || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
 +		    break;
-+		  INSERT_OPERAND (RD, *ip, regno);
 +		  continue;
 +		case 'U': /* RS1, constrained to equal RD */
 +		  if (!reg_lookup (&s, RCLASS_GPR, &regno)
-+		      || EXTRACT_OPERAND (RD, *ip) != regno)
-+		    break;
-+		  continue;
-+		case 'T': /* RS2, nonzero */
-+		  if (!reg_lookup (&s, RCLASS_GPR, &regno) || regno == 0)
++		      || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
 +		    break;
-+		  INSERT_OPERAND (CRS2, *ip, regno);
 +		  continue;
 +		case 'V': /* RS2 */
 +		  if (!reg_lookup (&s, RCLASS_GPR, &regno))
@@ -5354,7 +5286,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
 +rvc_imm_done:
 +		  s = expr_end;
-+                  imm_expr->X_op = O_absent;
++		  imm_expr->X_op = O_absent;
 +		  continue;
 +		case '<':
 +		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
@@ -5400,42 +5332,50 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		      || imm_expr->X_op != O_constant
 +		      || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
 +		    break;
-+		  ip->insn_opcode |= ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
++		  ip->insn_opcode |=
++		    ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
 +		  goto rvc_imm_done;
 +		case 'n':
 +		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 +		      || imm_expr->X_op != O_constant
 +		      || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
 +		    break;
-+		  ip->insn_opcode |= ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
++		  ip->insn_opcode |=
++		    ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
 +		  goto rvc_imm_done;
 +		case 'K':
 +		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 +		      || imm_expr->X_op != O_constant
-+		      || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number))
++		      || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number)
++		      || imm_expr->X_add_number == 0)
 +		    break;
-+		  ip->insn_opcode |= ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
++		  ip->insn_opcode |=
++		    ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
 +		  goto rvc_imm_done;
 +		case 'L':
 +		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 +		      || imm_expr->X_op != O_constant
-+		      || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number))
++		      || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number)
++		      || imm_expr->X_add_number == 0)
 +		    break;
-+		  ip->insn_opcode |= ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
++		  ip->insn_opcode |=
++		    ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
 +		  goto rvc_imm_done;
 +		case 'M':
 +		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 +		      || imm_expr->X_op != O_constant
 +		      || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
 +		    break;
-+		  ip->insn_opcode |= ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
++		  ip->insn_opcode |=
++		    ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
 +		  goto rvc_imm_done;
 +		case 'N':
 +		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 +		      || imm_expr->X_op != O_constant
 +		      || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
 +		    break;
-+		  ip->insn_opcode |= ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
++		  ip->insn_opcode |=
++		    ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
 +		  goto rvc_imm_done;
 +		case 'u':
 +		  p = percent_op_utype;
@@ -5445,25 +5385,36 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		  if (imm_expr->X_op != O_constant
 +		      || imm_expr->X_add_number <= 0
 +		      || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
-+		      || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH/2
++		      || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
 +			  && imm_expr->X_add_number <
-+			      RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH/2))
++			      RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))
 +		    break;
 +		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
 +		  goto rvc_imm_done;
 +		case 'v':
 +		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
-+		      || (imm_expr->X_add_number & (RISCV_IMM_REACH-1))
++		      || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
 +		      || (int32_t)imm_expr->X_add_number
 +			  != imm_expr->X_add_number)
 +		    break;
-+		  imm_expr->X_add_number
-+		    = (uint32_t)imm_expr->X_add_number >> RISCV_IMM_BITS;
++		  imm_expr->X_add_number =
++		    ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
 +		  goto rvc_lui;
 +		case 'p':
 +		  goto branch;
 +		case 'a':
 +		  goto jump;
++		case 'D': /* floating-point RS2 x8-x15 */
++		  if (!reg_lookup (&s, RCLASS_FPR, &regno)
++		      || !(regno >= 8 && regno <= 15))
++		    break;
++		  INSERT_OPERAND (CRS2S, *ip, regno % 8);
++		  continue;
++		case 'T': /* floating-point RS2 */
++		  if (!reg_lookup (&s, RCLASS_FPR, &regno))
++		    break;
++		  INSERT_OPERAND (CRS2, *ip, regno);
++		  continue;
 +		default:
 +		  as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
 +		}
@@ -5519,39 +5470,40 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +
 +	    case 'E':		/* Control register.  */
 +	      if (reg_lookup (&s, RCLASS_CSR, &regno))
-+	        INSERT_OPERAND (CSR, *ip, regno);
++		INSERT_OPERAND (CSR, *ip, regno);
 +	      else
 +		{
-+	          my_getExpression (imm_expr, s);
-+	          check_absolute_expr (ip, imm_expr);
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr);
 +		  if ((unsigned long) imm_expr->X_add_number > 0xfff)
-+	            as_warn(_("Improper CSR address (%lu)"),
-+	                    (unsigned long) imm_expr->X_add_number);
-+	          INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
++		    as_warn(_("Improper CSR address (%lu)"),
++			    (unsigned long) imm_expr->X_add_number);
++		  INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
 +		  imm_expr->X_op = O_absent;
 +		  s = expr_end;
-+	        }
++		}
 +	      continue;
 +
-+            case 'm':		/* rounding mode */
-+              if (arg_lookup (&s, riscv_rm, ARRAY_SIZE(riscv_rm), &regno))
-+                {
-+                  INSERT_OPERAND (RM, *ip, regno);
-+                  continue;
-+                }
-+              break;
++	    case 'm':		/* rounding mode */
++	      if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
++		{
++		  INSERT_OPERAND (RM, *ip, regno);
++		  continue;
++		}
++	      break;
 +
 +	    case 'P':
 +	    case 'Q':		/* fence predecessor/successor */
-+              if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ), &regno))
-+                {
-+	          if (*args == 'P')
-+	            INSERT_OPERAND(PRED, *ip, regno);
-+	          else
-+	            INSERT_OPERAND(SUCC, *ip, regno);
-+	          continue;
-+                }
-+              break;
++	      if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
++			      &regno))
++		{
++		  if (*args == 'P')
++		    INSERT_OPERAND (PRED, *ip, regno);
++		  else
++		    INSERT_OPERAND (SUCC, *ip, regno);
++		  continue;
++		}
++	      break;
 +
 +	    case 'd':		/* destination register */
 +	    case 's':		/* source register */
@@ -5562,8 +5514,8 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		  if (*s == ' ')
 +		    ++s;
 +
-+	/* Now that we have assembled one operand, we use the args string
-+	 * to figure out where it goes in the instruction.  */
++		  /* Now that we have assembled one operand, we use the args
++		     string to figure out where it goes in the instruction.  */
 +		  switch (c)
 +		    {
 +		    case 's':
@@ -5625,6 +5577,9 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	    case 'A':
 +	      my_getExpression (imm_expr, s);
 +	      normalize_constant_expr (imm_expr);
++	      /* The 'A' format specifier must be a symbol. */
++	      if (imm_expr->X_op != O_symbol)
++	        break;
 +	      *imm_reloc = BFD_RELOC_32;
 +	      s = expr_end;
 +	      continue;
@@ -5646,23 +5601,23 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	      *imm_reloc = BFD_RELOC_UNUSED;
 +load_store:
 +	      /* Check whether there is only a single bracketed expression
-+	         left.  If so, it must be the base register and the
-+	         constant must be zero.  */
++		 left.  If so, it must be the base register and the
++		 constant must be zero.  */
 +	      imm_expr->X_op = O_constant;
 +	      imm_expr->X_add_number = 0;
 +	      if (*s == '(' && strchr (s + 1, '(') == 0)
 +		continue;
 +alu_op:
 +	      /* If this value won't fit into a 16 bit offset, then go
-+	         find a macro that will generate the 32 bit offset
-+	         code pattern.  */
++		 find a macro that will generate the 32 bit offset
++		 code pattern.  */
 +	      if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
 +		{
 +		  normalize_constant_expr (imm_expr);
 +		  if (imm_expr->X_op != O_constant
 +		      || (*args == '0' && imm_expr->X_add_number != 0)
-+	              || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
-+	              || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
++		      || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
++		      || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
 +		    break;
 +		}
 +
@@ -5684,7 +5639,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +		  if (imm_expr->X_add_number < 0
 +		      || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
 +		    as_bad (_("lui expression not in range 0..1048575"));
-+	      
++
 +		  *imm_reloc = BFD_RELOC_RISCV_HI20;
 +		  imm_expr->X_add_number <<= RISCV_IMM_BITS;
 +		}
@@ -5707,8 +5662,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	      continue;
 +
 +	    default:
-+	      as_bad (_("bad char = '%c'\n"), *args);
-+	      internalError ();
++	      as_fatal (_("internal error: bad argument type %c"), *args);
 +	    }
 +	  break;
 +	}
@@ -5766,11 +5720,13 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +    OPTION_MARCH,
 +    OPTION_PIC,
 +    OPTION_NO_PIC,
++    OPTION_MSOFT_FLOAT,
++    OPTION_MHARD_FLOAT,
 +    OPTION_MRVC,
 +    OPTION_MNO_RVC,
-+    OPTION_END_OF_ENUM    
++    OPTION_END_OF_ENUM
 +  };
-+  
++
 +struct option md_longopts[] =
 +{
 +  {"m32", no_argument, NULL, OPTION_M32},
@@ -5781,22 +5737,39 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
 +  {"mrvc", no_argument, NULL, OPTION_MRVC},
 +  {"mno-rvc", no_argument, NULL, OPTION_MNO_RVC},
++  {"msoft-float", no_argument, NULL, OPTION_MSOFT_FLOAT},
++  {"mhard-float", no_argument, NULL, OPTION_MHARD_FLOAT},
 +
 +  {NULL, no_argument, NULL, 0}
 +};
 +size_t md_longopts_size = sizeof (md_longopts);
 +
++enum float_mode {
++  FLOAT_MODE_DEFAULT,
++  FLOAT_MODE_SOFT,
++  FLOAT_MODE_HARD
++};
++static enum float_mode marg_float_mode = FLOAT_MODE_DEFAULT;
++
 +int
 +md_parse_option (int c, char *arg)
 +{
 +  switch (c)
 +    {
 +    case OPTION_MRVC:
-+      riscv_opts.rvc = 1;
++      riscv_set_rvc (TRUE);
 +      break;
 +
 +    case OPTION_MNO_RVC:
-+      riscv_opts.rvc = 0;
++      riscv_set_rvc (FALSE);
++      break;
++
++    case OPTION_MSOFT_FLOAT:
++      marg_float_mode = FLOAT_MODE_SOFT;
++      break;
++
++    case OPTION_MHARD_FLOAT:
++      marg_float_mode = FLOAT_MODE_HARD;
 +      break;
 +
 +    case OPTION_M32:
@@ -5829,6 +5802,9 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +void
 +riscv_after_parse_args (void)
 +{
++  struct riscv_subset *subset;
++  enum float_mode isa_float_mode, elf_float_mode;
++
 +  if (riscv_subsets == NULL)
 +    riscv_set_arch ("RVIMAFDXcustom");
 +
@@ -5842,8 +5818,34 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	as_bad ("unknown default architecture `%s'", default_arch);
 +    }
 +
-+  if (riscv_opts.rvc)
-+    elf_flags |= EF_RISCV_RVC;
++  isa_float_mode = FLOAT_MODE_SOFT;
++  for (subset = riscv_subsets; subset != NULL; subset = subset->next)
++    {
++       if (strcasecmp(subset->name, "F") == 0)
++         isa_float_mode = FLOAT_MODE_HARD;
++       if (strcasecmp(subset->name, "D") == 0)
++         isa_float_mode = FLOAT_MODE_HARD;
++    }
++
++  if (marg_float_mode == FLOAT_MODE_HARD && isa_float_mode == FLOAT_MODE_SOFT)
++    as_bad ("Architecture doesn't allow hardfloat ABI");
++
++  elf_float_mode = (marg_float_mode == FLOAT_MODE_DEFAULT) ? isa_float_mode
++                                                           : marg_float_mode;
++
++  switch (elf_float_mode) {
++  case FLOAT_MODE_DEFAULT:
++    as_bad("a specific float mode must be specified for an ELF");
++    break;
++
++  case FLOAT_MODE_SOFT:
++    elf_flags |= EF_RISCV_SOFT_FLOAT;
++    break;
++
++  case FLOAT_MODE_HARD:
++    elf_flags &= ~EF_RISCV_SOFT_FLOAT;
++    break;
++  }
 +}
 +
 +void
@@ -5913,17 +5915,25 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	  fixP->fx_subsy = NULL;
 +
 +	  if (fixP->fx_r_type == BFD_RELOC_64)
-+	    fixP->fx_r_type = BFD_RELOC_RISCV_ADD64,
-+	    fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
++	    {
++	      fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
++	      fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
++	    }
 +	  else if (fixP->fx_r_type == BFD_RELOC_32)
-+	    fixP->fx_r_type = BFD_RELOC_RISCV_ADD32,
-+	    fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
++	    {
++	      fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
++	      fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
++	    }
 +	  else if (fixP->fx_r_type == BFD_RELOC_16)
-+	    fixP->fx_r_type = BFD_RELOC_RISCV_ADD16,
-+	    fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
++	    {
++	      fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
++	      fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
++	    }
 +	  else
-+	    fixP->fx_r_type = BFD_RELOC_RISCV_ADD8,
-+	    fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
++	    {
++	      fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
++	      fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
++	    }
 +	}
 +      /* fall through */
 +
@@ -5943,8 +5953,9 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +      if (fixP->fx_addsy)
 +	{
 +	  /* Fill in a tentative value to improve objdump readability.  */
-+	  bfd_vma delta = ENCODE_UJTYPE_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP - md_pcrel_from (fixP));
-+	  bfd_putl32 (bfd_getl32 (buf) | delta, buf);
++	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
++	  bfd_vma delta = target - md_pcrel_from (fixP);
++	  bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
 +	}
 +      break;
 +
@@ -5952,8 +5963,9 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +      if (fixP->fx_addsy)
 +	{
 +	  /* Fill in a tentative value to improve objdump readability.  */
-+	  bfd_vma delta = ENCODE_SBTYPE_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP - md_pcrel_from (fixP));
-+	  bfd_putl32 (bfd_getl32 (buf) | delta, buf);
++	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
++	  bfd_vma delta = target - md_pcrel_from (fixP);
++	  bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
 +	}
 +      break;
 +
@@ -5961,8 +5973,9 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +      if (fixP->fx_addsy)
 +	{
 +	  /* Fill in a tentative value to improve objdump readability.  */
-+	  bfd_vma delta = ENCODE_RVC_B_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP - md_pcrel_from (fixP));
-+	  bfd_putl16 (bfd_getl16 (buf) | delta, buf);
++	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
++	  bfd_vma delta = target - md_pcrel_from (fixP);
++	  bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
 +	}
 +      break;
 +
@@ -5970,8 +5983,9 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +      if (fixP->fx_addsy)
 +	{
 +	  /* Fill in a tentative value to improve objdump readability.  */
-+	  bfd_vma delta = ENCODE_RVC_J_IMM (S_GET_VALUE (fixP->fx_addsy) + *valP - md_pcrel_from (fixP));
-+	  bfd_putl16 (bfd_getl16 (buf) | delta, buf);
++	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
++	  bfd_vma delta = target - md_pcrel_from (fixP);
++	  bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
 +	}
 +      break;
 +
@@ -5985,7 +5999,7 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +    default:
 +      /* We ignore generic BFD relocations we don't know about.  */
 +      if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
-+	internalError ();
++	as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
 +    }
 +}
 +
@@ -6012,9 +6026,9 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  *input_line_pointer = '\0';
 +
 +  if (strcmp (name, "rvc") == 0)
-+    riscv_opts.rvc = 1;
++    riscv_set_rvc (TRUE);
 +  else if (strcmp (name, "norvc") == 0)
-+    riscv_opts.rvc = 0;
++    riscv_set_rvc (FALSE);
 +  else if (strcmp (name, "push") == 0)
 +    {
 +      struct riscv_option_stack *s;
@@ -6115,12 +6129,13 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +      fill_value_specified = 1;
 +    }
 +
-+  if (!fill_value_specified && subseg_text_p (now_seg)
++  if (!fill_value_specified
++      && subseg_text_p (now_seg)
 +      && bytes > min_text_alignment)
 +    {
 +      /* Emit the worst-case NOP string.  The linker will delete any
-+         unnecessary NOPs.  This allows us to support code alignment
-+         in spite of linker relaxations.  */
++	 unnecessary NOPs.  This allows us to support code alignment
++	 in spite of linker relaxations.  */
 +      bfd_vma i, worst_case_bytes = bytes - min_text_alignment;
 +      char *nops = frag_more (worst_case_bytes);
 +      for (i = 0; i < worst_case_bytes - 2; i += 4)
@@ -6166,9 +6181,9 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +  if (reloc->howto == NULL)
 +    {
 +      if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
-+          && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
++	  && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
 +	{
-+          /* We don't have R_RISCV_8/16, but for this special case,
++	  /* We don't have R_RISCV_8/16, but for this special case,
 +	     we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16.  */
 +	  return reloc;
 +	}
@@ -6231,15 +6246,20 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +	      insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
 +	    else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
 +	      insn = MATCH_BNE | (rs1 << OP_SH_RS1);
-+	    else if ((insn & MASK_C_BLTZ) == MATCH_C_BLTZ)
-+	      insn = MATCH_BLT | (rs1 << OP_SH_RS1);
-+	    else if ((insn & MASK_C_BGEZ) == MATCH_C_BGEZ)
-+	      insn = MATCH_BGE | (rs1 << OP_SH_RS1);
 +	    else
 +	      abort ();
 +	    bfd_putl32 (insn, buf);
 +	    break;
 +
++	  case 6:
++	    /* Invert the branch condition.  Branch over the jump.  */
++	    insn = bfd_getl16 (buf);
++	    insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
++	    insn |= ENCODE_RVC_B_IMM (6);
++	    bfd_putl16 (insn, buf);
++	    buf += 2;
++	    goto jump;
++
 +	  case 2:
 +	    /* Just keep the RVC branch.  */
 +	    reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
@@ -6258,15 +6278,16 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +    {
 +    case 8:
 +      gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
-+      
-+      /* Invert the branch condition.  Branch over the jump. */
++
++      /* Invert the branch condition.  Branch over the jump.  */
 +      insn = bfd_getl32 (buf);
 +      insn ^= MATCH_BEQ ^ MATCH_BNE;
 +      insn |= ENCODE_SBTYPE_IMM (8);
 +      md_number_to_chars ((char *) buf, insn, 4);
 +      buf += 4;
-+      
-+      /* Jump to the target. */
++
++jump:
++      /* Jump to the target.  */
 +      fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
 +			  4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
 +      md_number_to_chars ((char *) buf, MATCH_JAL, 4);
@@ -6376,12 +6397,12 @@ diff -urN empty/gas/config/tc-riscv.c binutils-2.25/gas/config/tc-riscv.c
 +
 +  pop_insert (riscv_pseudo_table);
 +}
-diff -urN empty/gas/config/tc-riscv.h binutils-2.25/gas/config/tc-riscv.h
---- binutils-2.25/gas/config/tc-riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/gas/config/tc-riscv.h	2015-07-18 00:02:36.222287541 +0200
+diff -urN empty/gas/config/tc-riscv.h binutils-2.26/gas/config/tc-riscv.h
+--- empty/gas/config/tc-riscv.h	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/gas/config/tc-riscv.h	2016-04-03 10:33:12.065459702 +0800
 @@ -0,0 +1,102 @@
 +/* tc-riscv.h -- header file for tc-riscv.c.
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
 +   Based on MIPS target.
@@ -6399,9 +6420,8 @@ diff -urN empty/gas/config/tc-riscv.h binutils-2.25/gas/config/tc-riscv.h
 +   GNU General Public License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with GAS; see the file COPYING.  If not, write to the Free
-+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-+   02110-1301, USA.  */
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +#ifndef TC_RISCV
 +#define TC_RISCV
@@ -6416,9 +6436,11 @@ diff -urN empty/gas/config/tc-riscv.h binutils-2.25/gas/config/tc-riscv.h
 +#define TARGET_ARCH bfd_arch_riscv
 +
 +#define WORKING_DOT_WORD	1
-+#define OLD_FLOAT_READS
-+#define REPEAT_CONS_EXPRESSIONS
 +#define LOCAL_LABELS_FB 1
++
++/* Symbols named FAKE_LABEL_NAME are emitted when generating DWARF, so make
++   sure FAKE_LABEL_NAME is printable.  It still must be distinct from any
++   real label name.  So, append a space, which other labels can't contain.  */
 +#define FAKE_LABEL_NAME ".L0 "
 +
 +#define md_relax_frag(segment, fragp, stretch) \
@@ -6429,10 +6451,9 @@ diff -urN empty/gas/config/tc-riscv.h binutils-2.25/gas/config/tc-riscv.h
 +#define md_undefined_symbol(name)	(0)
 +#define md_operand(x)
 +
++/* FIXME: it is unclear if this is used, or if it is even correct.  */
 +#define MAX_MEM_FOR_RS_ALIGN_CODE  (1 + 2)
 +
-+#define TC_SYMFIELD_TYPE int
-+
 +/* The ISA of the target may change based on command-line arguments.  */
 +#define TARGET_FORMAT riscv_target_format()
 +extern const char *riscv_target_format (void);
@@ -6446,7 +6467,7 @@ diff -urN empty/gas/config/tc-riscv.h binutils-2.25/gas/config/tc-riscv.h
 +#define md_parse_long_option(arg) riscv_parse_long_option (arg)
 +extern int riscv_parse_long_option (const char *);
 +
-+/* Let the linker resolve all the relocs due to relaxation. */
++/* Let the linker resolve all the relocs due to relaxation.  */
 +#define tc_fix_adjustable(fixp) 0
 +#define md_allow_local_subtract(l,r,s) 0
 +
@@ -6476,18 +6497,18 @@ diff -urN empty/gas/config/tc-riscv.h binutils-2.25/gas/config/tc-riscv.h
 +
 +extern unsigned xlen;
 +#define DWARF2_DEFAULT_RETURN_COLUMN X_RA
-+#define DWARF2_CIE_DATA_ALIGNMENT (xlen / 8)
++#define DWARF2_CIE_DATA_ALIGNMENT (-(int) (xlen / 8))
 +
 +#define elf_tc_final_processing riscv_elf_final_processing
 +extern void riscv_elf_final_processing (void);
 +
 +#endif /* TC_RISCV */
-diff -urN empty/include/elf/riscv.h binutils-2.25/include/elf/riscv.h
---- binutils-2.25/include/elf/riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/include/elf/riscv.h	2015-07-18 00:02:36.222287541 +0200
-@@ -0,0 +1,143 @@
+diff -urN empty/include/elf/riscv.h binutils-2.26/include/elf/riscv.h
+--- empty/include/elf/riscv.h	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/include/elf/riscv.h	2016-04-03 10:33:12.065459702 +0800
+@@ -0,0 +1,92 @@
 +/* RISC-V ELF support for BFD.
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrw Waterman <waterman@cs.berkeley.edu> at UC Berkeley.
 +   Based on MIPS ELF support for BFD, by Ian Lance Taylor.
@@ -6505,9 +6526,8 @@ diff -urN empty/include/elf/riscv.h binutils-2.25/include/elf/riscv.h
 +   GNU General Public License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the Free Software
-+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-+   MA 02110-1301, USA.  */
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +/* This file holds definitions specific to the RISCV ELF ABI.  Note
 +   that most of this is not actually implemented by BFD.  */
@@ -6516,6 +6536,7 @@ diff -urN empty/include/elf/riscv.h binutils-2.25/include/elf/riscv.h
 +#define _ELF_RISCV_H
 +
 +#include "elf/reloc-macros.h"
++#include "libiberty.h"
 +
 +/* Relocation types.  */
 +START_RELOC_NUMBERS (elf_riscv_reloc_type)
@@ -6564,6 +6585,9 @@ diff -urN empty/include/elf/riscv.h binutils-2.25/include/elf/riscv.h
 +  RELOC_NUMBER (R_RISCV_ALIGN, 43)
 +  RELOC_NUMBER (R_RISCV_RVC_BRANCH, 44)
 +  RELOC_NUMBER (R_RISCV_RVC_JUMP, 45)
++  RELOC_NUMBER (R_RISCV_RVC_LUI, 46)
++  RELOC_NUMBER (R_RISCV_GPREL_I, 47)
++  RELOC_NUMBER (R_RISCV_GPREL_S, 48)
 +END_RELOC_NUMBERS (R_RISCV_max)
 +
 +/* Processor specific flags for the ELF header e_flags field.  */
@@ -6571,1424 +6595,18 @@ diff -urN empty/include/elf/riscv.h binutils-2.25/include/elf/riscv.h
 +/* File may contain compressed instructions.  */
 +#define EF_RISCV_RVC 0x0001
 +
-+/* Custom flag definitions. */
-+
-+#define EF_RISCV_EXT_MASK 0xffff
-+#define EF_RISCV_EXT_SH 16
-+#define E_RISCV_EXT_Xcustom 0x0000
-+#define E_RISCV_EXT_Xhwacha 0x0001
-+#define E_RISCV_EXT_RESERVED 0xffff
-+
-+#define EF_GET_RISCV_EXT(x) \
-+  ((x >> EF_RISCV_EXT_SH) & EF_RISCV_EXT_MASK)
-+
-+#define EF_SET_RISCV_EXT(x, ext) \
-+  do { x |= ((ext & EF_RISCV_EXT_MASK) << EF_RISCV_EXT_SH); } while (0)
-+
-+#define EF_IS_RISCV_EXT_Xcustom(x) \
-+  (EF_GET_RISCV_EXT(x) == E_RISCV_EXT_Xcustom)
-+
-+/* A mapping from extension names to elf flags  */
-+
-+struct riscv_extension_entry
-+{
-+  const char* name;
-+  unsigned int flag;
-+};
-+
-+static const struct riscv_extension_entry riscv_extension_map[] =
-+{
-+  {"Xcustom", E_RISCV_EXT_Xcustom},
-+  {"Xhwacha", E_RISCV_EXT_Xhwacha},
-+};
-+
-+/* Given an extension name, return an elf flag. */
-+
-+static inline const char* riscv_elf_flag_to_name(unsigned int flag)
-+{
-+  unsigned int i;
-+
-+  for (i=0; i<sizeof(riscv_extension_map)/sizeof(riscv_extension_map[0]); i++)
-+    if (riscv_extension_map[i].flag == flag)
-+      return riscv_extension_map[i].name;
-+
-+  return NULL;
-+}
-+
-+/* Given an elf flag, return an extension name. */
-+
-+static inline unsigned int riscv_elf_name_to_flag(const char* name)
-+{
-+  unsigned int i;
-+
-+  for (i=0; i<sizeof(riscv_extension_map)/sizeof(riscv_extension_map[0]); i++)
-+    if (strcmp(riscv_extension_map[i].name, name) == 0)
-+      return riscv_extension_map[i].flag;
-+
-+  return E_RISCV_EXT_Xcustom;
-+}
++/* File uses the soft-float calling convention.  */
++#define EF_RISCV_SOFT_FLOAT 0x0002
 +
 +#endif /* _ELF_RISCV_H */
-diff -urN empty/include/opcode/riscv-opc.h binutils-2.25/include/opcode/riscv-opc.h
---- binutils-2.25/include/opcode/riscv-opc.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/include/opcode/riscv-opc.h	2015-07-18 00:02:36.222287541 +0200
-@@ -0,0 +1,1348 @@
-+/* Automatically generated by parse-opcodes */
-+#ifndef RISCV_ENCODING_H
-+#define RISCV_ENCODING_H
-+#define MATCH_ADD 0x33
-+#define MASK_ADD  0xfe00707f
-+#define MATCH_ADDI 0x13
-+#define MASK_ADDI  0x707f
-+#define MATCH_ADDIW 0x1b
-+#define MASK_ADDIW  0x707f
-+#define MATCH_ADDW 0x3b
-+#define MASK_ADDW  0xfe00707f
-+#define MATCH_AMOADD_D 0x302f
-+#define MASK_AMOADD_D  0xf800707f
-+#define MATCH_AMOADD_W 0x202f
-+#define MASK_AMOADD_W  0xf800707f
-+#define MATCH_AMOAND_D 0x6000302f
-+#define MASK_AMOAND_D  0xf800707f
-+#define MATCH_AMOAND_W 0x6000202f
-+#define MASK_AMOAND_W  0xf800707f
-+#define MATCH_AMOMAX_D 0xa000302f
-+#define MASK_AMOMAX_D  0xf800707f
-+#define MATCH_AMOMAX_W 0xa000202f
-+#define MASK_AMOMAX_W  0xf800707f
-+#define MATCH_AMOMAXU_D 0xe000302f
-+#define MASK_AMOMAXU_D  0xf800707f
-+#define MATCH_AMOMAXU_W 0xe000202f
-+#define MASK_AMOMAXU_W  0xf800707f
-+#define MATCH_AMOMIN_D 0x8000302f
-+#define MASK_AMOMIN_D  0xf800707f
-+#define MATCH_AMOMIN_W 0x8000202f
-+#define MASK_AMOMIN_W  0xf800707f
-+#define MATCH_AMOMINU_D 0xc000302f
-+#define MASK_AMOMINU_D  0xf800707f
-+#define MATCH_AMOMINU_W 0xc000202f
-+#define MASK_AMOMINU_W  0xf800707f
-+#define MATCH_AMOOR_D 0x4000302f
-+#define MASK_AMOOR_D  0xf800707f
-+#define MATCH_AMOOR_W 0x4000202f
-+#define MASK_AMOOR_W  0xf800707f
-+#define MATCH_AMOSWAP_D 0x800302f
-+#define MASK_AMOSWAP_D  0xf800707f
-+#define MATCH_AMOSWAP_W 0x800202f
-+#define MASK_AMOSWAP_W  0xf800707f
-+#define MATCH_AMOXOR_D 0x2000302f
-+#define MASK_AMOXOR_D  0xf800707f
-+#define MATCH_AMOXOR_W 0x2000202f
-+#define MASK_AMOXOR_W  0xf800707f
-+#define MATCH_AND 0x7033
-+#define MASK_AND  0xfe00707f
-+#define MATCH_ANDI 0x7013
-+#define MASK_ANDI  0x707f
-+#define MATCH_AUIPC 0x17
-+#define MASK_AUIPC  0x7f
-+#define MATCH_BEQ 0x63
-+#define MASK_BEQ  0x707f
-+#define MATCH_BGE 0x5063
-+#define MASK_BGE  0x707f
-+#define MATCH_BGEU 0x7063
-+#define MASK_BGEU  0x707f
-+#define MATCH_BLT 0x4063
-+#define MASK_BLT  0x707f
-+#define MATCH_BLTU 0x6063
-+#define MASK_BLTU  0x707f
-+#define MATCH_BNE 0x1063
-+#define MASK_BNE  0x707f
-+#define MATCH_C_ADD 0x1000
-+#define MASK_C_ADD  0xf003
-+#define MATCH_C_ADD3 0xa000
-+#define MASK_C_ADD3  0xe063
-+#define MATCH_C_ADDI 0xc002
-+#define MASK_C_ADDI  0xe003
-+#define MATCH_C_ADDI16SP 0xc002
-+#define MASK_C_ADDI16SP  0xef83
-+#define MATCH_C_ADDI4SPN 0xa001
-+#define MASK_C_ADDI4SPN  0xe003
-+#define MATCH_C_ADDIN 0x8001
-+#define MASK_C_ADDIN  0xe063
-+#define MATCH_C_ADDIW 0xe002
-+#define MASK_C_ADDIW  0xe003
-+#define MATCH_C_ADDW 0x9000
-+#define MASK_C_ADDW  0xf003
-+#define MATCH_C_AND3 0xa060
-+#define MASK_C_AND3  0xe063
-+#define MATCH_C_ANDI 0xe002
-+#define MASK_C_ANDI  0xe003
-+#define MATCH_C_ANDIN 0x8061
-+#define MASK_C_ANDIN  0xe063
-+#define MATCH_C_BEQZ 0x4002
-+#define MASK_C_BEQZ  0xe003
-+#define MATCH_C_BGEZ 0xe001
-+#define MASK_C_BGEZ  0xe003
-+#define MATCH_C_BLTZ 0x6001
-+#define MASK_C_BLTZ  0xe003
-+#define MATCH_C_BNEZ 0x6002
-+#define MASK_C_BNEZ  0xe003
-+#define MATCH_C_EBREAK 0x1000
-+#define MASK_C_EBREAK  0xffff
-+#define MATCH_C_J 0x2
-+#define MASK_C_J  0xe003
-+#define MATCH_C_JAL 0x2002
-+#define MASK_C_JAL  0xe003
-+#define MATCH_C_JALR 0xa002
-+#define MASK_C_JALR  0xf07f
-+#define MATCH_C_JR 0x8002
-+#define MASK_C_JR  0xf07f
-+#define MATCH_C_LD 0xe000
-+#define MASK_C_LD  0xe003
-+#define MATCH_C_LDSP 0xe001
-+#define MASK_C_LDSP  0xe003
-+#define MATCH_C_LI 0x8002
-+#define MASK_C_LI  0xe003
-+#define MATCH_C_LUI 0xa002
-+#define MASK_C_LUI  0xe003
-+#define MATCH_C_LW 0xc000
-+#define MASK_C_LW  0xe003
-+#define MATCH_C_LWSP 0xc001
-+#define MASK_C_LWSP  0xe003
-+#define MATCH_C_MV 0x0
-+#define MASK_C_MV  0xf003
-+#define MATCH_C_OR3 0xa040
-+#define MASK_C_OR3  0xe063
-+#define MATCH_C_ORIN 0x8041
-+#define MASK_C_ORIN  0xe063
-+#define MATCH_C_SD 0x6000
-+#define MASK_C_SD  0xe003
-+#define MATCH_C_SDSP 0x6001
-+#define MASK_C_SDSP  0xe003
-+#define MATCH_C_SLL 0x6400
-+#define MASK_C_SLL  0xfc63
-+#define MATCH_C_SLLI 0x1
-+#define MASK_C_SLLI  0xe003
-+#define MATCH_C_SLLIW 0x8001
-+#define MASK_C_SLLIW  0xe003
-+#define MATCH_C_SLLR 0x6c00
-+#define MASK_C_SLLR  0xfc63
-+#define MATCH_C_SLT 0x6440
-+#define MASK_C_SLT  0xfc63
-+#define MATCH_C_SLTR 0x6c40
-+#define MASK_C_SLTR  0xfc63
-+#define MATCH_C_SLTU 0x6460
-+#define MASK_C_SLTU  0xfc63
-+#define MATCH_C_SLTUR 0x6c60
-+#define MASK_C_SLTUR  0xfc63
-+#define MATCH_C_SRA 0x6020
-+#define MASK_C_SRA  0xfc63
-+#define MATCH_C_SRAI 0x2000
-+#define MASK_C_SRAI  0xe003
-+#define MATCH_C_SRL 0x6420
-+#define MASK_C_SRL  0xfc63
-+#define MATCH_C_SRLI 0x2001
-+#define MASK_C_SRLI  0xe003
-+#define MATCH_C_SRLR 0x6c20
-+#define MASK_C_SRLR  0xfc63
-+#define MATCH_C_SUB 0x8000
-+#define MASK_C_SUB  0xf003
-+#define MATCH_C_SUB3 0xa020
-+#define MASK_C_SUB3  0xe063
-+#define MATCH_C_SW 0x4000
-+#define MASK_C_SW  0xe003
-+#define MATCH_C_SWSP 0x4001
-+#define MASK_C_SWSP  0xe003
-+#define MATCH_C_XOR 0x6000
-+#define MASK_C_XOR  0xfc63
-+#define MATCH_C_XORIN 0x8021
-+#define MASK_C_XORIN  0xe063
-+#define MATCH_CSRRC 0x3073
-+#define MASK_CSRRC  0x707f
-+#define MATCH_CSRRCI 0x7073
-+#define MASK_CSRRCI  0x707f
-+#define MATCH_CSRRS 0x2073
-+#define MASK_CSRRS  0x707f
-+#define MATCH_CSRRSI 0x6073
-+#define MASK_CSRRSI  0x707f
-+#define MATCH_CSRRW 0x1073
-+#define MASK_CSRRW  0x707f
-+#define MATCH_CSRRWI 0x5073
-+#define MASK_CSRRWI  0x707f
-+#define MATCH_CUSTOM0 0xb
-+#define MASK_CUSTOM0  0x707f
-+#define MATCH_CUSTOM0_RD 0x400b
-+#define MASK_CUSTOM0_RD  0x707f
-+#define MATCH_CUSTOM0_RD_RS1 0x600b
-+#define MASK_CUSTOM0_RD_RS1  0x707f
-+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
-+#define MATCH_CUSTOM0_RS1 0x200b
-+#define MASK_CUSTOM0_RS1  0x707f
-+#define MATCH_CUSTOM0_RS1_RS2 0x300b
-+#define MASK_CUSTOM0_RS1_RS2  0x707f
-+#define MATCH_CUSTOM1 0x2b
-+#define MASK_CUSTOM1  0x707f
-+#define MATCH_CUSTOM1_RD 0x402b
-+#define MASK_CUSTOM1_RD  0x707f
-+#define MATCH_CUSTOM1_RD_RS1 0x602b
-+#define MASK_CUSTOM1_RD_RS1  0x707f
-+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
-+#define MATCH_CUSTOM1_RS1 0x202b
-+#define MASK_CUSTOM1_RS1  0x707f
-+#define MATCH_CUSTOM1_RS1_RS2 0x302b
-+#define MASK_CUSTOM1_RS1_RS2  0x707f
-+#define MATCH_CUSTOM2 0x5b
-+#define MASK_CUSTOM2  0x707f
-+#define MATCH_CUSTOM2_RD 0x405b
-+#define MASK_CUSTOM2_RD  0x707f
-+#define MATCH_CUSTOM2_RD_RS1 0x605b
-+#define MASK_CUSTOM2_RD_RS1  0x707f
-+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
-+#define MATCH_CUSTOM2_RS1 0x205b
-+#define MASK_CUSTOM2_RS1  0x707f
-+#define MATCH_CUSTOM2_RS1_RS2 0x305b
-+#define MASK_CUSTOM2_RS1_RS2  0x707f
-+#define MATCH_CUSTOM3 0x7b
-+#define MASK_CUSTOM3  0x707f
-+#define MATCH_CUSTOM3_RD 0x407b
-+#define MASK_CUSTOM3_RD  0x707f
-+#define MATCH_CUSTOM3_RD_RS1 0x607b
-+#define MASK_CUSTOM3_RD_RS1  0x707f
-+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
-+#define MATCH_CUSTOM3_RS1 0x207b
-+#define MASK_CUSTOM3_RS1  0x707f
-+#define MATCH_CUSTOM3_RS1_RS2 0x307b
-+#define MASK_CUSTOM3_RS1_RS2  0x707f
-+#define MATCH_DIV 0x2004033
-+#define MASK_DIV  0xfe00707f
-+#define MATCH_DIVU 0x2005033
-+#define MASK_DIVU  0xfe00707f
-+#define MATCH_DIVUW 0x200503b
-+#define MASK_DIVUW  0xfe00707f
-+#define MATCH_DIVW 0x200403b
-+#define MASK_DIVW  0xfe00707f
-+#define MATCH_EBREAK 0x100073
-+#define MASK_EBREAK  0xffffffff
-+#define MATCH_ECALL 0x73
-+#define MASK_ECALL  0xffffffff
-+#define MATCH_ERET 0x10000073
-+#define MASK_ERET  0xffffffff
-+#define MATCH_FADD_D 0x2000053
-+#define MASK_FADD_D  0xfe00007f
-+#define MATCH_FADD_H 0x4000053
-+#define MASK_FADD_H  0xfe00007f
-+#define MATCH_FADD_S 0x53
-+#define MASK_FADD_S  0xfe00007f
-+#define MATCH_FCLASS_D 0xe2001053
-+#define MASK_FCLASS_D  0xfff0707f
-+#define MATCH_FCLASS_S 0xe0001053
-+#define MASK_FCLASS_S  0xfff0707f
-+#define MATCH_FCVT_D_H 0x8c000053
-+#define MASK_FCVT_D_H  0xfff0007f
-+#define MATCH_FCVT_D_L 0xd2200053
-+#define MASK_FCVT_D_L  0xfff0007f
-+#define MATCH_FCVT_D_LU 0xd2300053
-+#define MASK_FCVT_D_LU  0xfff0007f
-+#define MATCH_FCVT_D_S 0x42000053
-+#define MASK_FCVT_D_S  0xfff0007f
-+#define MATCH_FCVT_D_W 0xd2000053
-+#define MASK_FCVT_D_W  0xfff0007f
-+#define MATCH_FCVT_D_WU 0xd2100053
-+#define MASK_FCVT_D_WU  0xfff0007f
-+#define MATCH_FCVT_H_D 0x92000053
-+#define MASK_FCVT_H_D  0xfff0007f
-+#define MATCH_FCVT_H_L 0x64000053
-+#define MASK_FCVT_H_L  0xfff0007f
-+#define MATCH_FCVT_H_LU 0x6c000053
-+#define MASK_FCVT_H_LU  0xfff0007f
-+#define MATCH_FCVT_H_S 0x90000053
-+#define MASK_FCVT_H_S  0xfff0007f
-+#define MATCH_FCVT_H_W 0x74000053
-+#define MASK_FCVT_H_W  0xfff0007f
-+#define MATCH_FCVT_H_WU 0x7c000053
-+#define MASK_FCVT_H_WU  0xfff0007f
-+#define MATCH_FCVT_L_D 0xc2200053
-+#define MASK_FCVT_L_D  0xfff0007f
-+#define MATCH_FCVT_L_H 0x44000053
-+#define MASK_FCVT_L_H  0xfff0007f
-+#define MATCH_FCVT_L_S 0xc0200053
-+#define MASK_FCVT_L_S  0xfff0007f
-+#define MATCH_FCVT_LU_D 0xc2300053
-+#define MASK_FCVT_LU_D  0xfff0007f
-+#define MATCH_FCVT_LU_H 0x4c000053
-+#define MASK_FCVT_LU_H  0xfff0007f
-+#define MATCH_FCVT_LU_S 0xc0300053
-+#define MASK_FCVT_LU_S  0xfff0007f
-+#define MATCH_FCVT_S_D 0x40100053
-+#define MASK_FCVT_S_D  0xfff0007f
-+#define MATCH_FCVT_S_H 0x84000053
-+#define MASK_FCVT_S_H  0xfff0007f
-+#define MATCH_FCVT_S_L 0xd0200053
-+#define MASK_FCVT_S_L  0xfff0007f
-+#define MATCH_FCVT_S_LU 0xd0300053
-+#define MASK_FCVT_S_LU  0xfff0007f
-+#define MATCH_FCVT_S_W 0xd0000053
-+#define MASK_FCVT_S_W  0xfff0007f
-+#define MATCH_FCVT_S_WU 0xd0100053
-+#define MASK_FCVT_S_WU  0xfff0007f
-+#define MATCH_FCVT_W_D 0xc2000053
-+#define MASK_FCVT_W_D  0xfff0007f
-+#define MATCH_FCVT_W_H 0x54000053
-+#define MASK_FCVT_W_H  0xfff0007f
-+#define MATCH_FCVT_W_S 0xc0000053
-+#define MASK_FCVT_W_S  0xfff0007f
-+#define MATCH_FCVT_WU_D 0xc2100053
-+#define MASK_FCVT_WU_D  0xfff0007f
-+#define MATCH_FCVT_WU_H 0x5c000053
-+#define MASK_FCVT_WU_H  0xfff0007f
-+#define MATCH_FCVT_WU_S 0xc0100053
-+#define MASK_FCVT_WU_S  0xfff0007f
-+#define MATCH_FDIV_D 0x1a000053
-+#define MASK_FDIV_D  0xfe00007f
-+#define MATCH_FDIV_H 0x1c000053
-+#define MASK_FDIV_H  0xfe00007f
-+#define MATCH_FDIV_S 0x18000053
-+#define MASK_FDIV_S  0xfe00007f
-+#define MATCH_FENCE 0xf
-+#define MASK_FENCE  0x707f
-+#define MATCH_FENCE_I 0x100f
-+#define MASK_FENCE_I  0x707f
-+#define MATCH_FEQ_D 0xa2002053
-+#define MASK_FEQ_D  0xfe00707f
-+#define MATCH_FEQ_H 0xac000053
-+#define MASK_FEQ_H  0xfe00707f
-+#define MATCH_FEQ_S 0xa0002053
-+#define MASK_FEQ_S  0xfe00707f
-+#define MATCH_FLD 0x3007
-+#define MASK_FLD  0x707f
-+#define MATCH_FLE_D 0xa2000053
-+#define MASK_FLE_D  0xfe00707f
-+#define MATCH_FLE_H 0xbc000053
-+#define MASK_FLE_H  0xfe00707f
-+#define MATCH_FLE_S 0xa0000053
-+#define MASK_FLE_S  0xfe00707f
-+#define MATCH_FLH 0x1007
-+#define MASK_FLH  0x707f
-+#define MATCH_FLT_D 0xa2001053
-+#define MASK_FLT_D  0xfe00707f
-+#define MATCH_FLT_H 0xb4000053
-+#define MASK_FLT_H  0xfe00707f
-+#define MATCH_FLT_S 0xa0001053
-+#define MASK_FLT_S  0xfe00707f
-+#define MATCH_FLW 0x2007
-+#define MASK_FLW  0x707f
-+#define MATCH_FMADD_D 0x2000043
-+#define MASK_FMADD_D  0x600007f
-+#define MATCH_FMADD_H 0x4000043
-+#define MASK_FMADD_H  0x600007f
-+#define MATCH_FMADD_S 0x43
-+#define MASK_FMADD_S  0x600007f
-+#define MATCH_FMAX_D 0x2a001053
-+#define MASK_FMAX_D  0xfe00707f
-+#define MATCH_FMAX_H 0xcc000053
-+#define MASK_FMAX_H  0xfe00707f
-+#define MATCH_FMAX_S 0x28001053
-+#define MASK_FMAX_S  0xfe00707f
-+#define MATCH_FMIN_D 0x2a000053
-+#define MASK_FMIN_D  0xfe00707f
-+#define MATCH_FMIN_H 0xc4000053
-+#define MASK_FMIN_H  0xfe00707f
-+#define MATCH_FMIN_S 0x28000053
-+#define MASK_FMIN_S  0xfe00707f
-+#define MATCH_FMOVN 0x6007077
-+#define MASK_FMOVN  0xfe00707f
-+#define MATCH_FMOVZ 0x4007077
-+#define MASK_FMOVZ  0xfe00707f
-+#define MATCH_FMSUB_D 0x2000047
-+#define MASK_FMSUB_D  0x600007f
-+#define MATCH_FMSUB_H 0x4000047
-+#define MASK_FMSUB_H  0x600007f
-+#define MATCH_FMSUB_S 0x47
-+#define MASK_FMSUB_S  0x600007f
-+#define MATCH_FMUL_D 0x12000053
-+#define MASK_FMUL_D  0xfe00007f
-+#define MATCH_FMUL_H 0x14000053
-+#define MASK_FMUL_H  0xfe00007f
-+#define MATCH_FMUL_S 0x10000053
-+#define MASK_FMUL_S  0xfe00007f
-+#define MATCH_FMV_D_X 0xf2000053
-+#define MASK_FMV_D_X  0xfff0707f
-+#define MATCH_FMV_H_X 0xf4000053
-+#define MASK_FMV_H_X  0xfff0707f
-+#define MATCH_FMV_S_X 0xf0000053
-+#define MASK_FMV_S_X  0xfff0707f
-+#define MATCH_FMV_X_D 0xe2000053
-+#define MASK_FMV_X_D  0xfff0707f
-+#define MATCH_FMV_X_H 0xe4000053
-+#define MASK_FMV_X_H  0xfff0707f
-+#define MATCH_FMV_X_S 0xe0000053
-+#define MASK_FMV_X_S  0xfff0707f
-+#define MATCH_FNMADD_D 0x200004f
-+#define MASK_FNMADD_D  0x600007f
-+#define MATCH_FNMADD_H 0x400004f
-+#define MASK_FNMADD_H  0x600007f
-+#define MATCH_FNMADD_S 0x4f
-+#define MASK_FNMADD_S  0x600007f
-+#define MATCH_FNMSUB_D 0x200004b
-+#define MASK_FNMSUB_D  0x600007f
-+#define MATCH_FNMSUB_H 0x400004b
-+#define MASK_FNMSUB_H  0x600007f
-+#define MATCH_FNMSUB_S 0x4b
-+#define MASK_FNMSUB_S  0x600007f
-+#define MATCH_FRCSR 0x302073
-+#define MASK_FRCSR  0xfffff07f
-+#define MATCH_FRFLAGS 0x102073
-+#define MASK_FRFLAGS  0xfffff07f
-+#define MATCH_FRRM 0x202073
-+#define MASK_FRRM  0xfffff07f
-+#define MATCH_FSCSR 0x301073
-+#define MASK_FSCSR  0xfff0707f
-+#define MATCH_FSD 0x3027
-+#define MASK_FSD  0x707f
-+#define MATCH_FSFLAGS 0x101073
-+#define MASK_FSFLAGS  0xfff0707f
-+#define MATCH_FSFLAGSI 0x105073
-+#define MASK_FSFLAGSI  0xfff0707f
-+#define MATCH_FSGNJ_D 0x22000053
-+#define MASK_FSGNJ_D  0xfe00707f
-+#define MATCH_FSGNJ_H 0x2c000053
-+#define MASK_FSGNJ_H  0xfe00707f
-+#define MATCH_FSGNJ_S 0x20000053
-+#define MASK_FSGNJ_S  0xfe00707f
-+#define MATCH_FSGNJN_D 0x22001053
-+#define MASK_FSGNJN_D  0xfe00707f
-+#define MATCH_FSGNJN_H 0x34000053
-+#define MASK_FSGNJN_H  0xfe00707f
-+#define MATCH_FSGNJN_S 0x20001053
-+#define MASK_FSGNJN_S  0xfe00707f
-+#define MATCH_FSGNJX_D 0x22002053
-+#define MASK_FSGNJX_D  0xfe00707f
-+#define MATCH_FSGNJX_H 0x3c000053
-+#define MASK_FSGNJX_H  0xfe00707f
-+#define MATCH_FSGNJX_S 0x20002053
-+#define MASK_FSGNJX_S  0xfe00707f
-+#define MATCH_FSH 0x1027
-+#define MASK_FSH  0x707f
-+#define MATCH_FSQRT_D 0x5a000053
-+#define MASK_FSQRT_D  0xfff0007f
-+#define MATCH_FSQRT_H 0x24000053
-+#define MASK_FSQRT_H  0xfff0007f
-+#define MATCH_FSQRT_S 0x58000053
-+#define MASK_FSQRT_S  0xfff0007f
-+#define MATCH_FSRM 0x201073
-+#define MASK_FSRM  0xfff0707f
-+#define MATCH_FSRMI 0x205073
-+#define MASK_FSRMI  0xfff0707f
-+#define MATCH_FSUB_D 0xa000053
-+#define MASK_FSUB_D  0xfe00007f
-+#define MATCH_FSUB_H 0xc000053
-+#define MASK_FSUB_H  0xfe00007f
-+#define MATCH_FSUB_S 0x8000053
-+#define MASK_FSUB_S  0xfe00007f
-+#define MATCH_FSW 0x2027
-+#define MASK_FSW  0x707f
-+#define MATCH_HRTS 0x20500073
-+#define MASK_HRTS  0xffffffff
-+#define MATCH_JAL 0x6f
-+#define MASK_JAL  0x7f
-+#define MATCH_JALR 0x67
-+#define MASK_JALR  0x707f
-+#define MATCH_LB 0x3
-+#define MASK_LB  0x707f
-+#define MATCH_LBU 0x4003
-+#define MASK_LBU  0x707f
-+#define MATCH_LD 0x3003
-+#define MASK_LD  0x707f
-+#define MATCH_LH 0x1003
-+#define MASK_LH  0x707f
-+#define MATCH_LHU 0x5003
-+#define MASK_LHU  0x707f
-+#define MATCH_LR_D 0x1000302f
-+#define MASK_LR_D  0xf9f0707f
-+#define MATCH_LR_W 0x1000202f
-+#define MASK_LR_W  0xf9f0707f
-+#define MATCH_LUI 0x37
-+#define MASK_LUI  0x7f
-+#define MATCH_LW 0x2003
-+#define MASK_LW  0x707f
-+#define MATCH_LWU 0x6003
-+#define MASK_LWU  0x707f
-+#define MATCH_MOVN 0x2007077
-+#define MASK_MOVN  0xfe00707f
-+#define MATCH_MOVZ 0x7077
-+#define MASK_MOVZ  0xfe00707f
-+#define MATCH_MRTH 0x30600073
-+#define MASK_MRTH  0xffffffff
-+#define MATCH_MRTS 0x30500073
-+#define MASK_MRTS  0xffffffff
-+#define MATCH_MUL 0x2000033
-+#define MASK_MUL  0xfe00707f
-+#define MATCH_MULH 0x2001033
-+#define MASK_MULH  0xfe00707f
-+#define MATCH_MULHSU 0x2002033
-+#define MASK_MULHSU  0xfe00707f
-+#define MATCH_MULHU 0x2003033
-+#define MASK_MULHU  0xfe00707f
-+#define MATCH_MULW 0x200003b
-+#define MASK_MULW  0xfe00707f
-+#define MATCH_OR 0x6033
-+#define MASK_OR  0xfe00707f
-+#define MATCH_ORI 0x6013
-+#define MASK_ORI  0x707f
-+#define MATCH_RDCYCLE 0xc0002073
-+#define MASK_RDCYCLE  0xfffff07f
-+#define MATCH_RDCYCLEH 0xc8002073
-+#define MASK_RDCYCLEH  0xfffff07f
-+#define MATCH_RDINSTRET 0xc0202073
-+#define MASK_RDINSTRET  0xfffff07f
-+#define MATCH_RDINSTRETH 0xc8202073
-+#define MASK_RDINSTRETH  0xfffff07f
-+#define MATCH_RDTIME 0xc0102073
-+#define MASK_RDTIME  0xfffff07f
-+#define MATCH_RDTIMEH 0xc8102073
-+#define MASK_RDTIMEH  0xfffff07f
-+#define MATCH_REM 0x2006033
-+#define MASK_REM  0xfe00707f
-+#define MATCH_REMU 0x2007033
-+#define MASK_REMU  0xfe00707f
-+#define MATCH_REMUW 0x200703b
-+#define MASK_REMUW  0xfe00707f
-+#define MATCH_REMW 0x200603b
-+#define MASK_REMW  0xfe00707f
-+#define MATCH_SB 0x23
-+#define MASK_SB  0x707f
-+#define MATCH_SBREAK 0x100073
-+#define MASK_SBREAK  0xffffffff
-+#define MATCH_SC_D 0x1800302f
-+#define MASK_SC_D  0xf800707f
-+#define MATCH_SC_W 0x1800202f
-+#define MASK_SC_W  0xf800707f
-+#define MATCH_SCALL 0x73
-+#define MASK_SCALL  0xffffffff
-+#define MATCH_SD 0x3023
-+#define MASK_SD  0x707f
-+#define MATCH_SFENCE_VM 0x10100073
-+#define MASK_SFENCE_VM  0xfff07fff
-+#define MATCH_SH 0x1023
-+#define MASK_SH  0x707f
-+#define MATCH_SLL 0x1033
-+#define MASK_SLL  0xfe00707f
-+#define MATCH_SLLI 0x1013
-+#define MASK_SLLI  0xfc00707f
-+#define MATCH_SLLI_RV32 0x1013
-+#define MASK_SLLI_RV32  0xfe00707f
-+#define MATCH_SLLIW 0x101b
-+#define MASK_SLLIW  0xfe00707f
-+#define MATCH_SLLW 0x103b
-+#define MASK_SLLW  0xfe00707f
-+#define MATCH_SLT 0x2033
-+#define MASK_SLT  0xfe00707f
-+#define MATCH_SLTI 0x2013
-+#define MASK_SLTI  0x707f
-+#define MATCH_SLTIU 0x3013
-+#define MASK_SLTIU  0x707f
-+#define MATCH_SLTU 0x3033
-+#define MASK_SLTU  0xfe00707f
-+#define MATCH_SRA 0x40005033
-+#define MASK_SRA  0xfe00707f
-+#define MATCH_SRAI 0x40005013
-+#define MASK_SRAI  0xfc00707f
-+#define MATCH_SRAI_RV32 0x40005013
-+#define MASK_SRAI_RV32  0xfe00707f
-+#define MATCH_SRAIW 0x4000501b
-+#define MASK_SRAIW  0xfe00707f
-+#define MATCH_SRAW 0x4000503b
-+#define MASK_SRAW  0xfe00707f
-+#define MATCH_SRET 0x10000073
-+#define MASK_SRET  0xffffffff
-+#define MATCH_SRL 0x5033
-+#define MASK_SRL  0xfe00707f
-+#define MATCH_SRLI 0x5013
-+#define MASK_SRLI  0xfc00707f
-+#define MATCH_SRLI_RV32 0x5013
-+#define MASK_SRLI_RV32  0xfe00707f
-+#define MATCH_SRLIW 0x501b
-+#define MASK_SRLIW  0xfe00707f
-+#define MATCH_SRLW 0x503b
-+#define MASK_SRLW  0xfe00707f
-+#define MATCH_STOP 0x5077
-+#define MASK_STOP  0xffffffff
-+#define MATCH_SUB 0x40000033
-+#define MASK_SUB  0xfe00707f
-+#define MATCH_SUBW 0x4000003b
-+#define MASK_SUBW  0xfe00707f
-+#define MATCH_SW 0x2023
-+#define MASK_SW  0x707f
-+#define MATCH_UTIDX 0x6077
-+#define MASK_UTIDX  0xfffff07f
-+#define MATCH_VENQCMD 0xa00302b
-+#define MASK_VENQCMD  0xfe007fff
-+#define MATCH_VENQCNT 0x1000302b
-+#define MASK_VENQCNT  0xfe007fff
-+#define MATCH_VENQIMM1 0xc00302b
-+#define MASK_VENQIMM1  0xfe007fff
-+#define MATCH_VENQIMM2 0xe00302b
-+#define MASK_VENQIMM2  0xfe007fff
-+#define MATCH_VF 0x10202b
-+#define MASK_VF  0x1f0707f
-+#define MATCH_VFLD 0x1600205b
-+#define MASK_VFLD  0xfff0707f
-+#define MATCH_VFLSEGD 0x1600205b
-+#define MASK_VFLSEGD  0x1ff0707f
-+#define MATCH_VFLSEGSTD 0x1600305b
-+#define MASK_VFLSEGSTD  0x1e00707f
-+#define MATCH_VFLSEGSTW 0x1400305b
-+#define MASK_VFLSEGSTW  0x1e00707f
-+#define MATCH_VFLSEGW 0x1400205b
-+#define MASK_VFLSEGW  0x1ff0707f
-+#define MATCH_VFLSTD 0x1600305b
-+#define MASK_VFLSTD  0xfe00707f
-+#define MATCH_VFLSTW 0x1400305b
-+#define MASK_VFLSTW  0xfe00707f
-+#define MATCH_VFLW 0x1400205b
-+#define MASK_VFLW  0xfff0707f
-+#define MATCH_VFMSV_D 0x1200202b
-+#define MASK_VFMSV_D  0xfff0707f
-+#define MATCH_VFMSV_S 0x1000202b
-+#define MASK_VFMSV_S  0xfff0707f
-+#define MATCH_VFMVV 0x1000002b
-+#define MASK_VFMVV  0xfff0707f
-+#define MATCH_VFSD 0x1600207b
-+#define MASK_VFSD  0xfff0707f
-+#define MATCH_VFSSEGD 0x1600207b
-+#define MASK_VFSSEGD  0x1ff0707f
-+#define MATCH_VFSSEGSTD 0x1600307b
-+#define MASK_VFSSEGSTD  0x1e00707f
-+#define MATCH_VFSSEGSTW 0x1400307b
-+#define MASK_VFSSEGSTW  0x1e00707f
-+#define MATCH_VFSSEGW 0x1400207b
-+#define MASK_VFSSEGW  0x1ff0707f
-+#define MATCH_VFSSTD 0x1600307b
-+#define MASK_VFSSTD  0xfe00707f
-+#define MATCH_VFSSTW 0x1400307b
-+#define MASK_VFSSTW  0xfe00707f
-+#define MATCH_VFSW 0x1400207b
-+#define MASK_VFSW  0xfff0707f
-+#define MATCH_VGETCFG 0x400b
-+#define MASK_VGETCFG  0xfffff07f
-+#define MATCH_VGETVL 0x200400b
-+#define MASK_VGETVL  0xfffff07f
-+#define MATCH_VLB 0x205b
-+#define MASK_VLB  0xfff0707f
-+#define MATCH_VLBU 0x800205b
-+#define MASK_VLBU  0xfff0707f
-+#define MATCH_VLD 0x600205b
-+#define MASK_VLD  0xfff0707f
-+#define MATCH_VLH 0x200205b
-+#define MASK_VLH  0xfff0707f
-+#define MATCH_VLHU 0xa00205b
-+#define MASK_VLHU  0xfff0707f
-+#define MATCH_VLSEGB 0x205b
-+#define MASK_VLSEGB  0x1ff0707f
-+#define MATCH_VLSEGBU 0x800205b
-+#define MASK_VLSEGBU  0x1ff0707f
-+#define MATCH_VLSEGD 0x600205b
-+#define MASK_VLSEGD  0x1ff0707f
-+#define MATCH_VLSEGH 0x200205b
-+#define MASK_VLSEGH  0x1ff0707f
-+#define MATCH_VLSEGHU 0xa00205b
-+#define MASK_VLSEGHU  0x1ff0707f
-+#define MATCH_VLSEGSTB 0x305b
-+#define MASK_VLSEGSTB  0x1e00707f
-+#define MATCH_VLSEGSTBU 0x800305b
-+#define MASK_VLSEGSTBU  0x1e00707f
-+#define MATCH_VLSEGSTD 0x600305b
-+#define MASK_VLSEGSTD  0x1e00707f
-+#define MATCH_VLSEGSTH 0x200305b
-+#define MASK_VLSEGSTH  0x1e00707f
-+#define MATCH_VLSEGSTHU 0xa00305b
-+#define MASK_VLSEGSTHU  0x1e00707f
-+#define MATCH_VLSEGSTW 0x400305b
-+#define MASK_VLSEGSTW  0x1e00707f
-+#define MATCH_VLSEGSTWU 0xc00305b
-+#define MASK_VLSEGSTWU  0x1e00707f
-+#define MATCH_VLSEGW 0x400205b
-+#define MASK_VLSEGW  0x1ff0707f
-+#define MATCH_VLSEGWU 0xc00205b
-+#define MASK_VLSEGWU  0x1ff0707f
-+#define MATCH_VLSTB 0x305b
-+#define MASK_VLSTB  0xfe00707f
-+#define MATCH_VLSTBU 0x800305b
-+#define MASK_VLSTBU  0xfe00707f
-+#define MATCH_VLSTD 0x600305b
-+#define MASK_VLSTD  0xfe00707f
-+#define MATCH_VLSTH 0x200305b
-+#define MASK_VLSTH  0xfe00707f
-+#define MATCH_VLSTHU 0xa00305b
-+#define MASK_VLSTHU  0xfe00707f
-+#define MATCH_VLSTW 0x400305b
-+#define MASK_VLSTW  0xfe00707f
-+#define MATCH_VLSTWU 0xc00305b
-+#define MASK_VLSTWU  0xfe00707f
-+#define MATCH_VLW 0x400205b
-+#define MASK_VLW  0xfff0707f
-+#define MATCH_VLWU 0xc00205b
-+#define MASK_VLWU  0xfff0707f
-+#define MATCH_VMSV 0x200202b
-+#define MASK_VMSV  0xfff0707f
-+#define MATCH_VMVV 0x200002b
-+#define MASK_VMVV  0xfff0707f
-+#define MATCH_VSB 0x207b
-+#define MASK_VSB  0xfff0707f
-+#define MATCH_VSD 0x600207b
-+#define MASK_VSD  0xfff0707f
-+#define MATCH_VSETCFG 0x200b
-+#define MASK_VSETCFG  0x7fff
-+#define MATCH_VSETVL 0x600b
-+#define MASK_VSETVL  0xfff0707f
-+#define MATCH_VSH 0x200207b
-+#define MASK_VSH  0xfff0707f
-+#define MATCH_VSSEGB 0x207b
-+#define MASK_VSSEGB  0x1ff0707f
-+#define MATCH_VSSEGD 0x600207b
-+#define MASK_VSSEGD  0x1ff0707f
-+#define MATCH_VSSEGH 0x200207b
-+#define MASK_VSSEGH  0x1ff0707f
-+#define MATCH_VSSEGSTB 0x307b
-+#define MASK_VSSEGSTB  0x1e00707f
-+#define MATCH_VSSEGSTD 0x600307b
-+#define MASK_VSSEGSTD  0x1e00707f
-+#define MATCH_VSSEGSTH 0x200307b
-+#define MASK_VSSEGSTH  0x1e00707f
-+#define MATCH_VSSEGSTW 0x400307b
-+#define MASK_VSSEGSTW  0x1e00707f
-+#define MATCH_VSSEGW 0x400207b
-+#define MASK_VSSEGW  0x1ff0707f
-+#define MATCH_VSSTB 0x307b
-+#define MASK_VSSTB  0xfe00707f
-+#define MATCH_VSSTD 0x600307b
-+#define MASK_VSSTD  0xfe00707f
-+#define MATCH_VSSTH 0x200307b
-+#define MASK_VSSTH  0xfe00707f
-+#define MATCH_VSSTW 0x400307b
-+#define MASK_VSSTW  0xfe00707f
-+#define MATCH_VSW 0x400207b
-+#define MASK_VSW  0xfff0707f
-+#define MATCH_VXCPTAUX 0x200402b
-+#define MASK_VXCPTAUX  0xfffff07f
-+#define MATCH_VXCPTCAUSE 0x402b
-+#define MASK_VXCPTCAUSE  0xfffff07f
-+#define MATCH_VXCPTEVAC 0x600302b
-+#define MASK_VXCPTEVAC  0xfff07fff
-+#define MATCH_VXCPTHOLD 0x800302b
-+#define MASK_VXCPTHOLD  0xfff07fff
-+#define MATCH_VXCPTKILL 0x400302b
-+#define MASK_VXCPTKILL  0xffffffff
-+#define MATCH_VXCPTRESTORE 0x200302b
-+#define MASK_VXCPTRESTORE  0xfff07fff
-+#define MATCH_VXCPTSAVE 0x302b
-+#define MASK_VXCPTSAVE  0xfff07fff
-+#define MATCH_WFI 0x10200073
-+#define MASK_WFI  0xffffffff
-+#define MATCH_XOR 0x4033
-+#define MASK_XOR  0xfe00707f
-+#define MATCH_XORI 0x4013
-+#define MASK_XORI  0x707f
-+#define CSR_FFLAGS 0x1
-+#define CSR_FRM 0x2
-+#define CSR_FCSR 0x3
-+#define CSR_CYCLE 0xc00
-+#define CSR_TIME 0xc01
-+#define CSR_INSTRET 0xc02
-+#define CSR_STATS 0xc0
-+#define CSR_UARCH0 0xcc0
-+#define CSR_UARCH1 0xcc1
-+#define CSR_UARCH2 0xcc2
-+#define CSR_UARCH3 0xcc3
-+#define CSR_UARCH4 0xcc4
-+#define CSR_UARCH5 0xcc5
-+#define CSR_UARCH6 0xcc6
-+#define CSR_UARCH7 0xcc7
-+#define CSR_UARCH8 0xcc8
-+#define CSR_UARCH9 0xcc9
-+#define CSR_UARCH10 0xcca
-+#define CSR_UARCH11 0xccb
-+#define CSR_UARCH12 0xccc
-+#define CSR_UARCH13 0xccd
-+#define CSR_UARCH14 0xcce
-+#define CSR_UARCH15 0xccf
-+#define CSR_SSTATUS 0x100
-+#define CSR_STVEC 0x101
-+#define CSR_SIE 0x104
-+#define CSR_SSCRATCH 0x140
-+#define CSR_SEPC 0x141
-+#define CSR_SIP 0x144
-+#define CSR_SPTBR 0x180
-+#define CSR_SASID 0x181
-+#define CSR_CYCLEW 0x900
-+#define CSR_TIMEW 0x901
-+#define CSR_INSTRETW 0x902
-+#define CSR_STIME 0xd01
-+#define CSR_SCAUSE 0xd42
-+#define CSR_SBADADDR 0xd43
-+#define CSR_STIMEW 0xa01
-+#define CSR_MSTATUS 0x300
-+#define CSR_MTVEC 0x301
-+#define CSR_MTDELEG 0x302
-+#define CSR_MIE 0x304
-+#define CSR_MTIMECMP 0x321
-+#define CSR_MSCRATCH 0x340
-+#define CSR_MEPC 0x341
-+#define CSR_MCAUSE 0x342
-+#define CSR_MBADADDR 0x343
-+#define CSR_MIP 0x344
-+#define CSR_MTIME 0x701
-+#define CSR_MCPUID 0xf00
-+#define CSR_MIMPID 0xf01
-+#define CSR_MHARTID 0xf10
-+#define CSR_MTOHOST 0x780
-+#define CSR_MFROMHOST 0x781
-+#define CSR_MRESET 0x782
-+#define CSR_SEND_IPI 0x783
-+#define CSR_CYCLEH 0xc80
-+#define CSR_TIMEH 0xc81
-+#define CSR_INSTRETH 0xc82
-+#define CSR_CYCLEHW 0x980
-+#define CSR_TIMEHW 0x981
-+#define CSR_INSTRETHW 0x982
-+#define CSR_STIMEH 0xd81
-+#define CSR_STIMEHW 0xa81
-+#define CSR_MTIMECMPH 0x361
-+#define CSR_MTIMEH 0x741
-+#define CAUSE_MISALIGNED_FETCH 0x0
-+#define CAUSE_FAULT_FETCH 0x1
-+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
-+#define CAUSE_BREAKPOINT 0x3
-+#define CAUSE_MISALIGNED_LOAD 0x4
-+#define CAUSE_FAULT_LOAD 0x5
-+#define CAUSE_MISALIGNED_STORE 0x6
-+#define CAUSE_FAULT_STORE 0x7
-+#define CAUSE_USER_ECALL 0x8
-+#define CAUSE_SUPERVISOR_ECALL 0x9
-+#define CAUSE_HYPERVISOR_ECALL 0xa
-+#define CAUSE_MACHINE_ECALL 0xb
-+#endif
-+#ifdef DECLARE_INSN
-+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
-+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
-+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
-+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
-+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
-+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
-+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
-+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
-+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
-+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
-+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
-+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
-+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
-+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
-+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
-+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
-+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
-+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
-+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
-+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
-+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
-+DECLARE_INSN(and, MATCH_AND, MASK_AND)
-+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
-+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
-+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
-+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
-+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
-+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
-+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
-+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
-+DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
-+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
-+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
-+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
-+DECLARE_INSN(c_addin, MATCH_C_ADDIN, MASK_C_ADDIN)
-+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
-+DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
-+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
-+DECLARE_INSN(c_andin, MATCH_C_ANDIN, MASK_C_ANDIN)
-+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
-+DECLARE_INSN(c_bgez, MATCH_C_BGEZ, MASK_C_BGEZ)
-+DECLARE_INSN(c_bltz, MATCH_C_BLTZ, MASK_C_BLTZ)
-+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
-+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
-+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
-+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
-+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
-+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
-+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
-+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
-+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
-+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
-+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
-+DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
-+DECLARE_INSN(c_orin, MATCH_C_ORIN, MASK_C_ORIN)
-+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
-+DECLARE_INSN(c_sll, MATCH_C_SLL, MASK_C_SLL)
-+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
-+DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
-+DECLARE_INSN(c_sllr, MATCH_C_SLLR, MASK_C_SLLR)
-+DECLARE_INSN(c_slt, MATCH_C_SLT, MASK_C_SLT)
-+DECLARE_INSN(c_sltr, MATCH_C_SLTR, MASK_C_SLTR)
-+DECLARE_INSN(c_sltu, MATCH_C_SLTU, MASK_C_SLTU)
-+DECLARE_INSN(c_sltur, MATCH_C_SLTUR, MASK_C_SLTUR)
-+DECLARE_INSN(c_sra, MATCH_C_SRA, MASK_C_SRA)
-+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
-+DECLARE_INSN(c_srl, MATCH_C_SRL, MASK_C_SRL)
-+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
-+DECLARE_INSN(c_srlr, MATCH_C_SRLR, MASK_C_SRLR)
-+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
-+DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
-+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
-+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
-+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
-+DECLARE_INSN(c_xorin, MATCH_C_XORIN, MASK_C_XORIN)
-+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
-+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
-+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
-+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
-+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
-+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
-+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
-+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
-+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
-+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
-+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
-+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
-+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
-+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
-+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
-+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
-+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
-+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
-+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
-+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
-+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
-+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
-+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
-+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
-+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
-+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
-+DECLARE_INSN(eret, MATCH_ERET, MASK_ERET)
-+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
-+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
-+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
-+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
-+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
-+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
-+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
-+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
-+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
-+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
-+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
-+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
-+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
-+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
-+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
-+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
-+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
-+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
-+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
-+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
-+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
-+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
-+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
-+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
-+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
-+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
-+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
-+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
-+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
-+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
-+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
-+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
-+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
-+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
-+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
-+DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
-+DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
-+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
-+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
-+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
-+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
-+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
-+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
-+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
-+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
-+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
-+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
-+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
-+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
-+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
-+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
-+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
-+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
-+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
-+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
-+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
-+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
-+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
-+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
-+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
-+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
-+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
-+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
-+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
-+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
-+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
-+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
-+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
-+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
-+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
-+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
-+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
-+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
-+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
-+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-+DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS)
-+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
-+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
-+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
-+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
-+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
-+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
-+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
-+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-+DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
-+DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
-+DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH)
-+DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
-+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
-+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
-+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
-+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
-+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
-+DECLARE_INSN(or, MATCH_OR, MASK_OR)
-+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
-+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
-+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
-+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
-+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
-+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
-+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
-+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
-+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
-+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
-+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
-+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
-+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
-+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
-+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
-+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
-+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
-+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
-+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
-+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
-+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
-+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
-+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
-+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
-+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
-+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
-+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
-+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
-+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
-+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
-+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
-+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
-+DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
-+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
-+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
-+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-+DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
-+DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
-+DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
-+DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
-+DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
-+DECLARE_INSN(vf, MATCH_VF, MASK_VF)
-+DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
-+DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
-+DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
-+DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
-+DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
-+DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
-+DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
-+DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
-+DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
-+DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
-+DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
-+DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
-+DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
-+DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
-+DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
-+DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
-+DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
-+DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
-+DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
-+DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
-+DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
-+DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
-+DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
-+DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
-+DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
-+DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
-+DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
-+DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
-+DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
-+DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
-+DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
-+DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
-+DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
-+DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
-+DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
-+DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
-+DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
-+DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
-+DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
-+DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
-+DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
-+DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
-+DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
-+DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
-+DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
-+DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
-+DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
-+DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
-+DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
-+DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
-+DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
-+DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
-+DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
-+DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
-+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
-+DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
-+DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
-+DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
-+DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
-+DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
-+DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
-+DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
-+DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
-+DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
-+DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
-+DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
-+DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
-+DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
-+DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
-+DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
-+DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
-+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
-+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
-+DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
-+DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
-+DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
-+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
-+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
-+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-+#endif
-+#ifdef DECLARE_CSR
-+DECLARE_CSR(fflags, CSR_FFLAGS)
-+DECLARE_CSR(frm, CSR_FRM)
-+DECLARE_CSR(fcsr, CSR_FCSR)
-+DECLARE_CSR(cycle, CSR_CYCLE)
-+DECLARE_CSR(time, CSR_TIME)
-+DECLARE_CSR(instret, CSR_INSTRET)
-+DECLARE_CSR(stats, CSR_STATS)
-+DECLARE_CSR(uarch0, CSR_UARCH0)
-+DECLARE_CSR(uarch1, CSR_UARCH1)
-+DECLARE_CSR(uarch2, CSR_UARCH2)
-+DECLARE_CSR(uarch3, CSR_UARCH3)
-+DECLARE_CSR(uarch4, CSR_UARCH4)
-+DECLARE_CSR(uarch5, CSR_UARCH5)
-+DECLARE_CSR(uarch6, CSR_UARCH6)
-+DECLARE_CSR(uarch7, CSR_UARCH7)
-+DECLARE_CSR(uarch8, CSR_UARCH8)
-+DECLARE_CSR(uarch9, CSR_UARCH9)
-+DECLARE_CSR(uarch10, CSR_UARCH10)
-+DECLARE_CSR(uarch11, CSR_UARCH11)
-+DECLARE_CSR(uarch12, CSR_UARCH12)
-+DECLARE_CSR(uarch13, CSR_UARCH13)
-+DECLARE_CSR(uarch14, CSR_UARCH14)
-+DECLARE_CSR(uarch15, CSR_UARCH15)
-+DECLARE_CSR(sstatus, CSR_SSTATUS)
-+DECLARE_CSR(stvec, CSR_STVEC)
-+DECLARE_CSR(sie, CSR_SIE)
-+DECLARE_CSR(sscratch, CSR_SSCRATCH)
-+DECLARE_CSR(sepc, CSR_SEPC)
-+DECLARE_CSR(sip, CSR_SIP)
-+DECLARE_CSR(sptbr, CSR_SPTBR)
-+DECLARE_CSR(sasid, CSR_SASID)
-+DECLARE_CSR(cyclew, CSR_CYCLEW)
-+DECLARE_CSR(timew, CSR_TIMEW)
-+DECLARE_CSR(instretw, CSR_INSTRETW)
-+DECLARE_CSR(stime, CSR_STIME)
-+DECLARE_CSR(scause, CSR_SCAUSE)
-+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
-+DECLARE_CSR(stimew, CSR_STIMEW)
-+DECLARE_CSR(mstatus, CSR_MSTATUS)
-+DECLARE_CSR(mtvec, CSR_MTVEC)
-+DECLARE_CSR(mtdeleg, CSR_MTDELEG)
-+DECLARE_CSR(mie, CSR_MIE)
-+DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
-+DECLARE_CSR(mscratch, CSR_MSCRATCH)
-+DECLARE_CSR(mepc, CSR_MEPC)
-+DECLARE_CSR(mcause, CSR_MCAUSE)
-+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
-+DECLARE_CSR(mip, CSR_MIP)
-+DECLARE_CSR(mtime, CSR_MTIME)
-+DECLARE_CSR(mcpuid, CSR_MCPUID)
-+DECLARE_CSR(mimpid, CSR_MIMPID)
-+DECLARE_CSR(mhartid, CSR_MHARTID)
-+DECLARE_CSR(mtohost, CSR_MTOHOST)
-+DECLARE_CSR(mfromhost, CSR_MFROMHOST)
-+DECLARE_CSR(mreset, CSR_MRESET)
-+DECLARE_CSR(send_ipi, CSR_SEND_IPI)
-+DECLARE_CSR(cycleh, CSR_CYCLEH)
-+DECLARE_CSR(timeh, CSR_TIMEH)
-+DECLARE_CSR(instreth, CSR_INSTRETH)
-+DECLARE_CSR(cyclehw, CSR_CYCLEHW)
-+DECLARE_CSR(timehw, CSR_TIMEHW)
-+DECLARE_CSR(instrethw, CSR_INSTRETHW)
-+DECLARE_CSR(stimeh, CSR_STIMEH)
-+DECLARE_CSR(stimehw, CSR_STIMEHW)
-+DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
-+DECLARE_CSR(mtimeh, CSR_MTIMEH)
-+#endif
-+#ifdef DECLARE_CAUSE
-+DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
-+DECLARE_CAUSE("frm", CAUSE_FRM)
-+DECLARE_CAUSE("fcsr", CAUSE_FCSR)
-+DECLARE_CAUSE("cycle", CAUSE_CYCLE)
-+DECLARE_CAUSE("time", CAUSE_TIME)
-+DECLARE_CAUSE("instret", CAUSE_INSTRET)
-+DECLARE_CAUSE("stats", CAUSE_STATS)
-+DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
-+DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
-+DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
-+DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
-+DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
-+DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
-+DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
-+DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
-+DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
-+DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
-+DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
-+DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
-+DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
-+DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
-+DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
-+DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
-+DECLARE_CAUSE("sstatus", CAUSE_SSTATUS)
-+DECLARE_CAUSE("stvec", CAUSE_STVEC)
-+DECLARE_CAUSE("sie", CAUSE_SIE)
-+DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH)
-+DECLARE_CAUSE("sepc", CAUSE_SEPC)
-+DECLARE_CAUSE("sip", CAUSE_SIP)
-+DECLARE_CAUSE("sptbr", CAUSE_SPTBR)
-+DECLARE_CAUSE("sasid", CAUSE_SASID)
-+DECLARE_CAUSE("cyclew", CAUSE_CYCLEW)
-+DECLARE_CAUSE("timew", CAUSE_TIMEW)
-+DECLARE_CAUSE("instretw", CAUSE_INSTRETW)
-+DECLARE_CAUSE("stime", CAUSE_STIME)
-+DECLARE_CAUSE("scause", CAUSE_SCAUSE)
-+DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR)
-+DECLARE_CAUSE("stimew", CAUSE_STIMEW)
-+DECLARE_CAUSE("mstatus", CAUSE_MSTATUS)
-+DECLARE_CAUSE("mtvec", CAUSE_MTVEC)
-+DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG)
-+DECLARE_CAUSE("mie", CAUSE_MIE)
-+DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP)
-+DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH)
-+DECLARE_CAUSE("mepc", CAUSE_MEPC)
-+DECLARE_CAUSE("mcause", CAUSE_MCAUSE)
-+DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR)
-+DECLARE_CAUSE("mip", CAUSE_MIP)
-+DECLARE_CAUSE("mtime", CAUSE_MTIME)
-+DECLARE_CAUSE("mcpuid", CAUSE_MCPUID)
-+DECLARE_CAUSE("mimpid", CAUSE_MIMPID)
-+DECLARE_CAUSE("mhartid", CAUSE_MHARTID)
-+DECLARE_CAUSE("mtohost", CAUSE_MTOHOST)
-+DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST)
-+DECLARE_CAUSE("mreset", CAUSE_MRESET)
-+DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
-+DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
-+DECLARE_CAUSE("timeh", CAUSE_TIMEH)
-+DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
-+DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW)
-+DECLARE_CAUSE("timehw", CAUSE_TIMEHW)
-+DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW)
-+DECLARE_CAUSE("stimeh", CAUSE_STIMEH)
-+DECLARE_CAUSE("stimehw", CAUSE_STIMEHW)
-+DECLARE_CAUSE("mtimecmph", CAUSE_MTIMECMPH)
-+DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH)
-+#endif
-diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
---- binutils-2.25/include/opcode/riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/include/opcode/riscv.h	2015-07-18 00:02:36.222287541 +0200
-@@ -0,0 +1,366 @@
+diff -urN empty/include/opcode/riscv.h binutils-2.26/include/opcode/riscv.h
+--- empty/include/opcode/riscv.h	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/include/opcode/riscv.h	2016-04-03 10:33:12.065459702 +0800
+@@ -0,0 +1,344 @@
 +/* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
 +   Copyright 2011
 +   Free Software Foundation, Inc.
-+   Contributed by Andrew Waterman 
++   Contributed by Andrew Waterman
 +
 +This file is part of GDB, GAS, and the GNU binutils.
 +
@@ -8013,53 +6631,37 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +#include <stdlib.h>
 +#include <stdint.h>
 +
-+/* RVC fields */
-+
-+#define OP_MASK_CRS2 0x1f
-+#define OP_SH_CRS2 2
-+#define OP_MASK_CRS1S 0x7
-+#define OP_SH_CRS1S 7
-+#define OP_MASK_CRS2S 0x7
-+#define OP_SH_CRS2S 2
-+#define OP_MASK_CRDS 0x7
-+#define OP_SH_CRDS 10
-+
-+static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
-+#define rvc_rd_regmap rvc_rs1_regmap
-+#define rvc_rs2b_regmap rvc_rs1_regmap
-+static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
-+
 +typedef uint64_t insn_t;
 +
 +static inline unsigned int riscv_insn_length (insn_t insn)
 +{
-+  if ((insn & 0x3) != 3) /* RVC */
++  if ((insn & 0x3) != 0x3) /* RVC.  */
 +    return 2;
-+  if ((insn & 0x1f) != 0x1f) /* base ISA and extensions in 32-bit space */
++  if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space.  */
 +    return 4;
-+  if ((insn & 0x3f) == 0x1f) /* 48-bit extensions */
++  if ((insn & 0x3f) == 0x1f) /* 48-bit extensions.  */
 +    return 6;
-+  if ((insn & 0x7f) == 0x3f) /* 64-bit extensions */
++  if ((insn & 0x7f) == 0x3f) /* 64-bit extensions.  */
 +    return 8;
-+  /* longer instructions not supported at the moment */
++  /* Longer instructions not supported at the moment.  */
 +  return 2;
 +}
 +
 +static const char * const riscv_rm[8] = {
 +  "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
 +};
-+static const char* const riscv_pred_succ[16] = {
++static const char * const riscv_pred_succ[16] = {
 +  0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
 +  "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw",
 +};
 +
 +#define RVC_JUMP_BITS 11
-+#define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RISCV_JUMP_ALIGN)
++#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
 +
 +#define RVC_BRANCH_BITS 8
-+#define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RISCV_BRANCH_ALIGN)
++#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
 +
-+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
++#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
 +#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
 +
 +#define EXTRACT_ITYPE_IMM(x) \
@@ -8074,12 +6676,14 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +  ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
 +#define EXTRACT_RVC_IMM(x) \
 +  (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
++#define EXTRACT_RVC_LUI_IMM(x) \
++  (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
 +#define EXTRACT_RVC_SIMM3(x) \
 +  (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
 +#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
 +  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
 +#define EXTRACT_RVC_ADDI16SP_IMM(x) \
-+  ((RV_X(x, 6, 1) << 4) | (RV_X(x, 5, 1) << 5) | (RV_X(x, 2, 3) << 6) | (-RV_X(x, 12, 1) << 9))
++  ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
 +#define EXTRACT_RVC_LW_IMM(x) \
 +  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
 +#define EXTRACT_RVC_LD_IMM(x) \
@@ -8093,9 +6697,9 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +#define EXTRACT_RVC_SDSP_IMM(x) \
 +  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
 +#define EXTRACT_RVC_B_IMM(x) \
-+  ((RV_X(x, 3, 4) << 1) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 10, 2) << 6) | (-RV_X(x, 12, 1) << 8))
++  ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
 +#define EXTRACT_RVC_J_IMM(x) \
-+  ((RV_X(x, 3, 4) << 1) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 5) << 6) | (-RV_X(x, 12, 1) << 11))
++  ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
 +
 +#define ENCODE_ITYPE_IMM(x) \
 +  (RV_X(x, 0, 12) << 20)
@@ -8109,12 +6713,14 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +  ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
 +#define ENCODE_RVC_IMM(x) \
 +  ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
++#define ENCODE_RVC_LUI_IMM(x) \
++  ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
 +#define ENCODE_RVC_SIMM3(x) \
 +  (RV_X(x, 0, 3) << 10)
 +#define ENCODE_RVC_ADDI4SPN_IMM(x) \
 +  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
 +#define ENCODE_RVC_ADDI16SP_IMM(x) \
-+  ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 5) | (RV_X(x, 6, 3) << 2) | (RV_X(x, 9, 1) << 12))
++  ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
 +#define ENCODE_RVC_LW_IMM(x) \
 +  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
 +#define ENCODE_RVC_LD_IMM(x) \
@@ -8128,9 +6734,9 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +#define ENCODE_RVC_SDSP_IMM(x) \
 +  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
 +#define ENCODE_RVC_B_IMM(x) \
-+  ((RV_X(x, 1, 4) << 3) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 3) << 10))
++  ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
 +#define ENCODE_RVC_J_IMM(x) \
-+  ((RV_X(x, 1, 4) << 3) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 6) << 7))
++  ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
 +
 +#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 +#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -8138,6 +6744,7 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
 +#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
 +#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
++#define VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
 +#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
 +#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
 +#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
@@ -8172,7 +6779,22 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
 +#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
 +
-+/* RV fields */
++#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
++#define RISCV_JUMP_ALIGN_BITS 1
++#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
++#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
++
++#define RISCV_IMM_BITS 12
++#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
++#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
++#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
++#define RISCV_RVC_IMM_REACH (1LL << 6)
++#define RISCV_BRANCH_BITS RISCV_IMM_BITS
++#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
++#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
++#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
++
++/* RV fields.  */
 +
 +#define OP_MASK_OP		0x7f
 +#define OP_SH_OP		0
@@ -8199,34 +6821,21 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +#define OP_MASK_RL		0x1
 +#define OP_SH_RL		25
 +
-+#define OP_MASK_VRD		0x1f
-+#define OP_SH_VRD		7
-+#define OP_MASK_VRS		0x1f
-+#define OP_SH_VRS		15
-+#define OP_MASK_VRT		0x1f
-+#define OP_SH_VRT		20
-+#define OP_MASK_VRR		0x1f
-+#define OP_SH_VRR		27
-+
-+#define OP_MASK_VFD		0x1f
-+#define OP_SH_VFD		7
-+#define OP_MASK_VFS		0x1f
-+#define OP_SH_VFS		15
-+#define OP_MASK_VFT		0x1f
-+#define OP_SH_VFT		20
-+#define OP_MASK_VFR		0x1f
-+#define OP_SH_VFR		27
-+
-+#define OP_MASK_IMMNGPR         0x3f
-+#define OP_SH_IMMNGPR           20
-+#define OP_MASK_IMMNFPR         0x3f
-+#define OP_SH_IMMNFPR           26
-+#define OP_MASK_IMMSEGNELM      0x7
-+#define OP_SH_IMMSEGNELM        29
-+#define OP_MASK_CUSTOM_IMM      0x7f
-+#define OP_SH_CUSTOM_IMM        25
-+#define OP_MASK_CSR             0xfff
-+#define OP_SH_CSR               20
++#define OP_MASK_CUSTOM_IMM	0x7f
++#define OP_SH_CUSTOM_IMM	25
++#define OP_MASK_CSR		0xfff
++#define OP_SH_CSR		20
++
++/* RVC fields.  */
++
++#define OP_MASK_CRS2 0x1f
++#define OP_SH_CRS2 2
++#define OP_MASK_CRS1S 0x7
++#define OP_SH_CRS1S 7
++#define OP_MASK_CRS2S 0x7
++#define OP_SH_CRS2S 2
++
++/* ABI names for selected x-registers.  */
 +
 +#define X_RA 1
 +#define X_SP 2
@@ -8239,23 +6848,21 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +
 +#define NGPR 32
 +#define NFPR 32
-+#define NVGPR 32
-+#define NVFPR 32
 +
-+#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
-+#define RISCV_JUMP_ALIGN_BITS 1
-+#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
-+#define RISCV_JUMP_REACH ((1ULL<<RISCV_JUMP_BITS)*RISCV_JUMP_ALIGN)
++/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
++   VALUE << SHIFT.  VALUE is evaluated exactly once.  */
++#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
++  (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
++	      | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
 +
-+#define RISCV_IMM_BITS 12
-+#define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS)
-+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
-+#define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS)
-+#define RISCV_RVC_IMM_REACH (1LL<<6)
-+#define RISCV_BRANCH_BITS RISCV_IMM_BITS
-+#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
-+#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
-+#define RISCV_BRANCH_REACH (RISCV_IMM_REACH*RISCV_BRANCH_ALIGN)
++/* Extract bits MASK << SHIFT from STRUCT and shift them right
++   SHIFT places.  */
++#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
++  (((STRUCT) >> (SHIFT)) & (MASK))
++
++/* Extract the operand given by FIELD from integer INSN.  */
++#define EXTRACT_OPERAND(FIELD, INSN) \
++  EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
 +
 +/* This structure holds information for a particular instruction.  */
 +
@@ -8263,7 +6870,7 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +{
 +  /* The name of the instruction.  */
 +  const char *name;
-+  /* The ISA subset name (I, M, A, F, D, Xextension). */
++  /* The ISA subset name (I, M, A, F, D, Xextension).  */
 +  const char *subset;
 +  /* A string describing the arguments for this instruction.  */
 +  const char *args;
@@ -8278,27 +6885,19 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +     INSN_MACRO, then this field is the macro identifier.  */
 +  insn_t mask;
 +  /* A function to determine if a word corresponds to this instruction.
-+     Usually, this computes ((word & mask) == match). */
-+  int (*match_func)(const struct riscv_opcode *op, insn_t word);
++     Usually, this computes ((word & mask) == match).  */
++  int (*match_func) (const struct riscv_opcode *op, insn_t word);
 +  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 +     of bits describing the instruction, notably any relevant hazard
 +     information.  */
 +  unsigned long pinfo;
 +};
 +
-+#define INSN_WRITE_GPR_D            0x00000001
-+#define INSN_WRITE_GPR_RA           0x00000004
-+#define INSN_WRITE_FPR_D            0x00000008
-+#define INSN_READ_GPR_S             0x00000040
-+#define INSN_READ_GPR_T             0x00000080
-+#define INSN_READ_FPR_S             0x00000100
-+#define INSN_READ_FPR_T             0x00000200
-+#define INSN_READ_FPR_R        	    0x00000400
-+/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
-+#define	INSN_ALIAS		    0x00001000
++/* Instruction is a simple alias (e.g. "mv" for "addi").  */
++#define	INSN_ALIAS		0x00000001
 +/* Instruction is actually a macro.  It should be ignored by the
 +   disassembler, and requires special treatment by the assembler.  */
-+#define INSN_MACRO                  0xffffffff
++#define INSN_MACRO		0xffffffff
 +
 +/* This is a list of macro expanded instructions.
 +
@@ -8332,7 +6931,6 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +  M_CALL,
 +  M_J,
 +  M_LI,
-+  M_VF,
 +  M_NUM_MACROS
 +};
 +
@@ -8341,8 +6939,6 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +extern const char * const riscv_gpr_names_abi[NGPR];
 +extern const char * const riscv_fpr_names_numeric[NFPR];
 +extern const char * const riscv_fpr_names_abi[NFPR];
-+extern const char * const riscv_vec_gpr_names[NVGPR];
-+extern const char * const riscv_vec_fpr_names[NVFPR];
 +
 +extern const struct riscv_opcode riscv_builtin_opcodes[];
 +extern const int bfd_riscv_num_builtin_opcodes;
@@ -8351,10 +6947,945 @@ diff -urN empty/include/opcode/riscv.h binutils-2.25/include/opcode/riscv.h
 +#define NUMOPCODES bfd_riscv_num_opcodes
 +
 +#endif /* _RISCV_H_ */
-diff -urN empty/ld/emulparams/elf32lriscv-defs.sh binutils-2.25/ld/emulparams/elf32lriscv-defs.sh
---- binutils-2.25/ld/emulparams/elf32lriscv-defs.sh	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emulparams/elf32lriscv-defs.sh	2015-07-18 00:02:36.222287541 +0200
-@@ -0,0 +1,39 @@
+diff -urN empty/include/opcode/riscv-opc.h binutils-2.26/include/opcode/riscv-opc.h
+--- empty/include/opcode/riscv-opc.h	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/include/opcode/riscv-opc.h	2016-04-03 10:33:12.065459702 +0800
+@@ -0,0 +1,931 @@
++/* Automatically generated by parse-opcodes */
++#ifndef RISCV_ENCODING_H
++#define RISCV_ENCODING_H
++#define MATCH_SLLI_RV32 0x1013
++#define MASK_SLLI_RV32  0xfe00707f
++#define MATCH_SRLI_RV32 0x5013
++#define MASK_SRLI_RV32  0xfe00707f
++#define MATCH_SRAI_RV32 0x40005013
++#define MASK_SRAI_RV32  0xfe00707f
++#define MATCH_FRFLAGS 0x102073
++#define MASK_FRFLAGS  0xfffff07f
++#define MATCH_FSFLAGS 0x101073
++#define MASK_FSFLAGS  0xfff0707f
++#define MATCH_FSFLAGSI 0x105073
++#define MASK_FSFLAGSI  0xfff0707f
++#define MATCH_FRRM 0x202073
++#define MASK_FRRM  0xfffff07f
++#define MATCH_FSRM 0x201073
++#define MASK_FSRM  0xfff0707f
++#define MATCH_FSRMI 0x205073
++#define MASK_FSRMI  0xfff0707f
++#define MATCH_FSCSR 0x301073
++#define MASK_FSCSR  0xfff0707f
++#define MATCH_FRCSR 0x302073
++#define MASK_FRCSR  0xfffff07f
++#define MATCH_RDCYCLE 0xc0002073
++#define MASK_RDCYCLE  0xfffff07f
++#define MATCH_RDTIME 0xc0102073
++#define MASK_RDTIME  0xfffff07f
++#define MATCH_RDINSTRET 0xc0202073
++#define MASK_RDINSTRET  0xfffff07f
++#define MATCH_RDCYCLEH 0xc8002073
++#define MASK_RDCYCLEH  0xfffff07f
++#define MATCH_RDTIMEH 0xc8102073
++#define MASK_RDTIMEH  0xfffff07f
++#define MATCH_RDINSTRETH 0xc8202073
++#define MASK_RDINSTRETH  0xfffff07f
++#define MATCH_ECALL 0x73
++#define MASK_ECALL  0xffffffff
++#define MATCH_EBREAK 0x100073
++#define MASK_EBREAK  0xffffffff
++#define MATCH_ERET 0x10000073
++#define MASK_ERET  0xffffffff
++#define MATCH_BEQ 0x63
++#define MASK_BEQ  0x707f
++#define MATCH_BNE 0x1063
++#define MASK_BNE  0x707f
++#define MATCH_BLT 0x4063
++#define MASK_BLT  0x707f
++#define MATCH_BGE 0x5063
++#define MASK_BGE  0x707f
++#define MATCH_BLTU 0x6063
++#define MASK_BLTU  0x707f
++#define MATCH_BGEU 0x7063
++#define MASK_BGEU  0x707f
++#define MATCH_JALR 0x67
++#define MASK_JALR  0x707f
++#define MATCH_JAL 0x6f
++#define MASK_JAL  0x7f
++#define MATCH_LUI 0x37
++#define MASK_LUI  0x7f
++#define MATCH_AUIPC 0x17
++#define MASK_AUIPC  0x7f
++#define MATCH_ADDI 0x13
++#define MASK_ADDI  0x707f
++#define MATCH_SLLI 0x1013
++#define MASK_SLLI  0xfc00707f
++#define MATCH_SLTI 0x2013
++#define MASK_SLTI  0x707f
++#define MATCH_SLTIU 0x3013
++#define MASK_SLTIU  0x707f
++#define MATCH_XORI 0x4013
++#define MASK_XORI  0x707f
++#define MATCH_SRLI 0x5013
++#define MASK_SRLI  0xfc00707f
++#define MATCH_SRAI 0x40005013
++#define MASK_SRAI  0xfc00707f
++#define MATCH_ORI 0x6013
++#define MASK_ORI  0x707f
++#define MATCH_ANDI 0x7013
++#define MASK_ANDI  0x707f
++#define MATCH_ADD 0x33
++#define MASK_ADD  0xfe00707f
++#define MATCH_SUB 0x40000033
++#define MASK_SUB  0xfe00707f
++#define MATCH_SLL 0x1033
++#define MASK_SLL  0xfe00707f
++#define MATCH_SLT 0x2033
++#define MASK_SLT  0xfe00707f
++#define MATCH_SLTU 0x3033
++#define MASK_SLTU  0xfe00707f
++#define MATCH_XOR 0x4033
++#define MASK_XOR  0xfe00707f
++#define MATCH_SRL 0x5033
++#define MASK_SRL  0xfe00707f
++#define MATCH_SRA 0x40005033
++#define MASK_SRA  0xfe00707f
++#define MATCH_OR 0x6033
++#define MASK_OR  0xfe00707f
++#define MATCH_AND 0x7033
++#define MASK_AND  0xfe00707f
++#define MATCH_ADDIW 0x1b
++#define MASK_ADDIW  0x707f
++#define MATCH_SLLIW 0x101b
++#define MASK_SLLIW  0xfe00707f
++#define MATCH_SRLIW 0x501b
++#define MASK_SRLIW  0xfe00707f
++#define MATCH_SRAIW 0x4000501b
++#define MASK_SRAIW  0xfe00707f
++#define MATCH_ADDW 0x3b
++#define MASK_ADDW  0xfe00707f
++#define MATCH_SUBW 0x4000003b
++#define MASK_SUBW  0xfe00707f
++#define MATCH_SLLW 0x103b
++#define MASK_SLLW  0xfe00707f
++#define MATCH_SRLW 0x503b
++#define MASK_SRLW  0xfe00707f
++#define MATCH_SRAW 0x4000503b
++#define MASK_SRAW  0xfe00707f
++#define MATCH_LB 0x3
++#define MASK_LB  0x707f
++#define MATCH_LH 0x1003
++#define MASK_LH  0x707f
++#define MATCH_LW 0x2003
++#define MASK_LW  0x707f
++#define MATCH_LD 0x3003
++#define MASK_LD  0x707f
++#define MATCH_LBU 0x4003
++#define MASK_LBU  0x707f
++#define MATCH_LHU 0x5003
++#define MASK_LHU  0x707f
++#define MATCH_LWU 0x6003
++#define MASK_LWU  0x707f
++#define MATCH_SB 0x23
++#define MASK_SB  0x707f
++#define MATCH_SH 0x1023
++#define MASK_SH  0x707f
++#define MATCH_SW 0x2023
++#define MASK_SW  0x707f
++#define MATCH_SD 0x3023
++#define MASK_SD  0x707f
++#define MATCH_FENCE 0xf
++#define MASK_FENCE  0x707f
++#define MATCH_FENCE_I 0x100f
++#define MASK_FENCE_I  0x707f
++#define MATCH_MUL 0x2000033
++#define MASK_MUL  0xfe00707f
++#define MATCH_MULH 0x2001033
++#define MASK_MULH  0xfe00707f
++#define MATCH_MULHSU 0x2002033
++#define MASK_MULHSU  0xfe00707f
++#define MATCH_MULHU 0x2003033
++#define MASK_MULHU  0xfe00707f
++#define MATCH_DIV 0x2004033
++#define MASK_DIV  0xfe00707f
++#define MATCH_DIVU 0x2005033
++#define MASK_DIVU  0xfe00707f
++#define MATCH_REM 0x2006033
++#define MASK_REM  0xfe00707f
++#define MATCH_REMU 0x2007033
++#define MASK_REMU  0xfe00707f
++#define MATCH_MULW 0x200003b
++#define MASK_MULW  0xfe00707f
++#define MATCH_DIVW 0x200403b
++#define MASK_DIVW  0xfe00707f
++#define MATCH_DIVUW 0x200503b
++#define MASK_DIVUW  0xfe00707f
++#define MATCH_REMW 0x200603b
++#define MASK_REMW  0xfe00707f
++#define MATCH_REMUW 0x200703b
++#define MASK_REMUW  0xfe00707f
++#define MATCH_AMOADD_W 0x202f
++#define MASK_AMOADD_W  0xf800707f
++#define MATCH_AMOXOR_W 0x2000202f
++#define MASK_AMOXOR_W  0xf800707f
++#define MATCH_AMOOR_W 0x4000202f
++#define MASK_AMOOR_W  0xf800707f
++#define MATCH_AMOAND_W 0x6000202f
++#define MASK_AMOAND_W  0xf800707f
++#define MATCH_AMOMIN_W 0x8000202f
++#define MASK_AMOMIN_W  0xf800707f
++#define MATCH_AMOMAX_W 0xa000202f
++#define MASK_AMOMAX_W  0xf800707f
++#define MATCH_AMOMINU_W 0xc000202f
++#define MASK_AMOMINU_W  0xf800707f
++#define MATCH_AMOMAXU_W 0xe000202f
++#define MASK_AMOMAXU_W  0xf800707f
++#define MATCH_AMOSWAP_W 0x800202f
++#define MASK_AMOSWAP_W  0xf800707f
++#define MATCH_LR_W 0x1000202f
++#define MASK_LR_W  0xf9f0707f
++#define MATCH_SC_W 0x1800202f
++#define MASK_SC_W  0xf800707f
++#define MATCH_AMOADD_D 0x302f
++#define MASK_AMOADD_D  0xf800707f
++#define MATCH_AMOXOR_D 0x2000302f
++#define MASK_AMOXOR_D  0xf800707f
++#define MATCH_AMOOR_D 0x4000302f
++#define MASK_AMOOR_D  0xf800707f
++#define MATCH_AMOAND_D 0x6000302f
++#define MASK_AMOAND_D  0xf800707f
++#define MATCH_AMOMIN_D 0x8000302f
++#define MASK_AMOMIN_D  0xf800707f
++#define MATCH_AMOMAX_D 0xa000302f
++#define MASK_AMOMAX_D  0xf800707f
++#define MATCH_AMOMINU_D 0xc000302f
++#define MASK_AMOMINU_D  0xf800707f
++#define MATCH_AMOMAXU_D 0xe000302f
++#define MASK_AMOMAXU_D  0xf800707f
++#define MATCH_AMOSWAP_D 0x800302f
++#define MASK_AMOSWAP_D  0xf800707f
++#define MATCH_LR_D 0x1000302f
++#define MASK_LR_D  0xf9f0707f
++#define MATCH_SC_D 0x1800302f
++#define MASK_SC_D  0xf800707f
++#define MATCH_SCALL 0x73
++#define MASK_SCALL  0xffffffff
++#define MATCH_SBREAK 0x100073
++#define MASK_SBREAK  0xffffffff
++#define MATCH_SRET 0x10200073
++#define MASK_SRET  0xffffffff
++#define MATCH_SFENCE_VM 0x10400073
++#define MASK_SFENCE_VM  0xfff07fff
++#define MATCH_WFI 0x10500073
++#define MASK_WFI  0xffffffff
++#define MATCH_CSRRW 0x1073
++#define MASK_CSRRW  0x707f
++#define MATCH_CSRRS 0x2073
++#define MASK_CSRRS  0x707f
++#define MATCH_CSRRC 0x3073
++#define MASK_CSRRC  0x707f
++#define MATCH_CSRRWI 0x5073
++#define MASK_CSRRWI  0x707f
++#define MATCH_CSRRSI 0x6073
++#define MASK_CSRRSI  0x707f
++#define MATCH_CSRRCI 0x7073
++#define MASK_CSRRCI  0x707f
++#define MATCH_FADD_S 0x53
++#define MASK_FADD_S  0xfe00007f
++#define MATCH_FSUB_S 0x8000053
++#define MASK_FSUB_S  0xfe00007f
++#define MATCH_FMUL_S 0x10000053
++#define MASK_FMUL_S  0xfe00007f
++#define MATCH_FDIV_S 0x18000053
++#define MASK_FDIV_S  0xfe00007f
++#define MATCH_FSGNJ_S 0x20000053
++#define MASK_FSGNJ_S  0xfe00707f
++#define MATCH_FSGNJN_S 0x20001053
++#define MASK_FSGNJN_S  0xfe00707f
++#define MATCH_FSGNJX_S 0x20002053
++#define MASK_FSGNJX_S  0xfe00707f
++#define MATCH_FMIN_S 0x28000053
++#define MASK_FMIN_S  0xfe00707f
++#define MATCH_FMAX_S 0x28001053
++#define MASK_FMAX_S  0xfe00707f
++#define MATCH_FSQRT_S 0x58000053
++#define MASK_FSQRT_S  0xfff0007f
++#define MATCH_FADD_D 0x2000053
++#define MASK_FADD_D  0xfe00007f
++#define MATCH_FSUB_D 0xa000053
++#define MASK_FSUB_D  0xfe00007f
++#define MATCH_FMUL_D 0x12000053
++#define MASK_FMUL_D  0xfe00007f
++#define MATCH_FDIV_D 0x1a000053
++#define MASK_FDIV_D  0xfe00007f
++#define MATCH_FSGNJ_D 0x22000053
++#define MASK_FSGNJ_D  0xfe00707f
++#define MATCH_FSGNJN_D 0x22001053
++#define MASK_FSGNJN_D  0xfe00707f
++#define MATCH_FSGNJX_D 0x22002053
++#define MASK_FSGNJX_D  0xfe00707f
++#define MATCH_FMIN_D 0x2a000053
++#define MASK_FMIN_D  0xfe00707f
++#define MATCH_FMAX_D 0x2a001053
++#define MASK_FMAX_D  0xfe00707f
++#define MATCH_FCVT_S_D 0x40100053
++#define MASK_FCVT_S_D  0xfff0007f
++#define MATCH_FCVT_D_S 0x42000053
++#define MASK_FCVT_D_S  0xfff0007f
++#define MATCH_FSQRT_D 0x5a000053
++#define MASK_FSQRT_D  0xfff0007f
++#define MATCH_FLE_S 0xa0000053
++#define MASK_FLE_S  0xfe00707f
++#define MATCH_FLT_S 0xa0001053
++#define MASK_FLT_S  0xfe00707f
++#define MATCH_FEQ_S 0xa0002053
++#define MASK_FEQ_S  0xfe00707f
++#define MATCH_FLE_D 0xa2000053
++#define MASK_FLE_D  0xfe00707f
++#define MATCH_FLT_D 0xa2001053
++#define MASK_FLT_D  0xfe00707f
++#define MATCH_FEQ_D 0xa2002053
++#define MASK_FEQ_D  0xfe00707f
++#define MATCH_FCVT_W_S 0xc0000053
++#define MASK_FCVT_W_S  0xfff0007f
++#define MATCH_FCVT_WU_S 0xc0100053
++#define MASK_FCVT_WU_S  0xfff0007f
++#define MATCH_FCVT_L_S 0xc0200053
++#define MASK_FCVT_L_S  0xfff0007f
++#define MATCH_FCVT_LU_S 0xc0300053
++#define MASK_FCVT_LU_S  0xfff0007f
++#define MATCH_FMV_X_S 0xe0000053
++#define MASK_FMV_X_S  0xfff0707f
++#define MATCH_FCLASS_S 0xe0001053
++#define MASK_FCLASS_S  0xfff0707f
++#define MATCH_FCVT_W_D 0xc2000053
++#define MASK_FCVT_W_D  0xfff0007f
++#define MATCH_FCVT_WU_D 0xc2100053
++#define MASK_FCVT_WU_D  0xfff0007f
++#define MATCH_FCVT_L_D 0xc2200053
++#define MASK_FCVT_L_D  0xfff0007f
++#define MATCH_FCVT_LU_D 0xc2300053
++#define MASK_FCVT_LU_D  0xfff0007f
++#define MATCH_FMV_X_D 0xe2000053
++#define MASK_FMV_X_D  0xfff0707f
++#define MATCH_FCLASS_D 0xe2001053
++#define MASK_FCLASS_D  0xfff0707f
++#define MATCH_FCVT_S_W 0xd0000053
++#define MASK_FCVT_S_W  0xfff0007f
++#define MATCH_FCVT_S_WU 0xd0100053
++#define MASK_FCVT_S_WU  0xfff0007f
++#define MATCH_FCVT_S_L 0xd0200053
++#define MASK_FCVT_S_L  0xfff0007f
++#define MATCH_FCVT_S_LU 0xd0300053
++#define MASK_FCVT_S_LU  0xfff0007f
++#define MATCH_FMV_S_X 0xf0000053
++#define MASK_FMV_S_X  0xfff0707f
++#define MATCH_FCVT_D_W 0xd2000053
++#define MASK_FCVT_D_W  0xfff0007f
++#define MATCH_FCVT_D_WU 0xd2100053
++#define MASK_FCVT_D_WU  0xfff0007f
++#define MATCH_FCVT_D_L 0xd2200053
++#define MASK_FCVT_D_L  0xfff0007f
++#define MATCH_FCVT_D_LU 0xd2300053
++#define MASK_FCVT_D_LU  0xfff0007f
++#define MATCH_FMV_D_X 0xf2000053
++#define MASK_FMV_D_X  0xfff0707f
++#define MATCH_FLW 0x2007
++#define MASK_FLW  0x707f
++#define MATCH_FLD 0x3007
++#define MASK_FLD  0x707f
++#define MATCH_FSW 0x2027
++#define MASK_FSW  0x707f
++#define MATCH_FSD 0x3027
++#define MASK_FSD  0x707f
++#define MATCH_FMADD_S 0x43
++#define MASK_FMADD_S  0x600007f
++#define MATCH_FMSUB_S 0x47
++#define MASK_FMSUB_S  0x600007f
++#define MATCH_FNMSUB_S 0x4b
++#define MASK_FNMSUB_S  0x600007f
++#define MATCH_FNMADD_S 0x4f
++#define MASK_FNMADD_S  0x600007f
++#define MATCH_FMADD_D 0x2000043
++#define MASK_FMADD_D  0x600007f
++#define MATCH_FMSUB_D 0x2000047
++#define MASK_FMSUB_D  0x600007f
++#define MATCH_FNMSUB_D 0x200004b
++#define MASK_FNMSUB_D  0x600007f
++#define MATCH_FNMADD_D 0x200004f
++#define MASK_FNMADD_D  0x600007f
++#define MATCH_C_ADDI4SPN 0x0
++#define MASK_C_ADDI4SPN  0xe003
++#define MATCH_C_FLD 0x2000
++#define MASK_C_FLD  0xe003
++#define MATCH_C_LW 0x4000
++#define MASK_C_LW  0xe003
++#define MATCH_C_FLW 0x6000
++#define MASK_C_FLW  0xe003
++#define MATCH_C_FSD 0xa000
++#define MASK_C_FSD  0xe003
++#define MATCH_C_SW 0xc000
++#define MASK_C_SW  0xe003
++#define MATCH_C_FSW 0xe000
++#define MASK_C_FSW  0xe003
++#define MATCH_C_ADDI 0x1
++#define MASK_C_ADDI  0xe003
++#define MATCH_C_JAL 0x2001
++#define MASK_C_JAL  0xe003
++#define MATCH_C_LI 0x4001
++#define MASK_C_LI  0xe003
++#define MATCH_C_LUI 0x6001
++#define MASK_C_LUI  0xe003
++#define MATCH_C_SRLI 0x8001
++#define MASK_C_SRLI  0xec03
++#define MATCH_C_SRAI 0x8401
++#define MASK_C_SRAI  0xec03
++#define MATCH_C_ANDI 0x8801
++#define MASK_C_ANDI  0xec03
++#define MATCH_C_SUB 0x8c01
++#define MASK_C_SUB  0xfc63
++#define MATCH_C_XOR 0x8c21
++#define MASK_C_XOR  0xfc63
++#define MATCH_C_OR 0x8c41
++#define MASK_C_OR  0xfc63
++#define MATCH_C_AND 0x8c61
++#define MASK_C_AND  0xfc63
++#define MATCH_C_SUBW 0x9c01
++#define MASK_C_SUBW  0xfc63
++#define MATCH_C_ADDW 0x9c21
++#define MASK_C_ADDW  0xfc63
++#define MATCH_C_J 0xa001
++#define MASK_C_J  0xe003
++#define MATCH_C_BEQZ 0xc001
++#define MASK_C_BEQZ  0xe003
++#define MATCH_C_BNEZ 0xe001
++#define MASK_C_BNEZ  0xe003
++#define MATCH_C_SLLI 0x2
++#define MASK_C_SLLI  0xe003
++#define MATCH_C_FLDSP 0x2002
++#define MASK_C_FLDSP  0xe003
++#define MATCH_C_LWSP 0x4002
++#define MASK_C_LWSP  0xe003
++#define MATCH_C_FLWSP 0x6002
++#define MASK_C_FLWSP  0xe003
++#define MATCH_C_MV 0x8002
++#define MASK_C_MV  0xf003
++#define MATCH_C_ADD 0x9002
++#define MASK_C_ADD  0xf003
++#define MATCH_C_FSDSP 0xa002
++#define MASK_C_FSDSP  0xe003
++#define MATCH_C_SWSP 0xc002
++#define MASK_C_SWSP  0xe003
++#define MATCH_C_FSWSP 0xe002
++#define MASK_C_FSWSP  0xe003
++#define MATCH_C_NOP 0x1
++#define MASK_C_NOP  0xffff
++#define MATCH_C_ADDI16SP 0x6101
++#define MASK_C_ADDI16SP  0xef83
++#define MATCH_C_JR 0x8002
++#define MASK_C_JR  0xf07f
++#define MATCH_C_JALR 0x9002
++#define MASK_C_JALR  0xf07f
++#define MATCH_C_EBREAK 0x9002
++#define MASK_C_EBREAK  0xffff
++#define MATCH_C_LD 0x6000
++#define MASK_C_LD  0xe003
++#define MATCH_C_SD 0xe000
++#define MASK_C_SD  0xe003
++#define MATCH_C_ADDIW 0x2001
++#define MASK_C_ADDIW  0xe003
++#define MATCH_C_LDSP 0x6002
++#define MASK_C_LDSP  0xe003
++#define MATCH_C_SDSP 0xe002
++#define MASK_C_SDSP  0xe003
++#define MATCH_CUSTOM0 0xb
++#define MASK_CUSTOM0  0x707f
++#define MATCH_CUSTOM0_RS1 0x200b
++#define MASK_CUSTOM0_RS1  0x707f
++#define MATCH_CUSTOM0_RS1_RS2 0x300b
++#define MASK_CUSTOM0_RS1_RS2  0x707f
++#define MATCH_CUSTOM0_RD 0x400b
++#define MASK_CUSTOM0_RD  0x707f
++#define MATCH_CUSTOM0_RD_RS1 0x600b
++#define MASK_CUSTOM0_RD_RS1  0x707f
++#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
++#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM1 0x2b
++#define MASK_CUSTOM1  0x707f
++#define MATCH_CUSTOM1_RS1 0x202b
++#define MASK_CUSTOM1_RS1  0x707f
++#define MATCH_CUSTOM1_RS1_RS2 0x302b
++#define MASK_CUSTOM1_RS1_RS2  0x707f
++#define MATCH_CUSTOM1_RD 0x402b
++#define MASK_CUSTOM1_RD  0x707f
++#define MATCH_CUSTOM1_RD_RS1 0x602b
++#define MASK_CUSTOM1_RD_RS1  0x707f
++#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
++#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM2 0x5b
++#define MASK_CUSTOM2  0x707f
++#define MATCH_CUSTOM2_RS1 0x205b
++#define MASK_CUSTOM2_RS1  0x707f
++#define MATCH_CUSTOM2_RS1_RS2 0x305b
++#define MASK_CUSTOM2_RS1_RS2  0x707f
++#define MATCH_CUSTOM2_RD 0x405b
++#define MASK_CUSTOM2_RD  0x707f
++#define MATCH_CUSTOM2_RD_RS1 0x605b
++#define MASK_CUSTOM2_RD_RS1  0x707f
++#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
++#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM3 0x7b
++#define MASK_CUSTOM3  0x707f
++#define MATCH_CUSTOM3_RS1 0x207b
++#define MASK_CUSTOM3_RS1  0x707f
++#define MATCH_CUSTOM3_RS1_RS2 0x307b
++#define MASK_CUSTOM3_RS1_RS2  0x707f
++#define MATCH_CUSTOM3_RD 0x407b
++#define MASK_CUSTOM3_RD  0x707f
++#define MATCH_CUSTOM3_RD_RS1 0x607b
++#define MASK_CUSTOM3_RD_RS1  0x707f
++#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
++#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
++#define CSR_FFLAGS 0x1
++#define CSR_FRM 0x2
++#define CSR_FCSR 0x3
++#define CSR_CYCLE 0xc00
++#define CSR_TIME 0xc01
++#define CSR_INSTRET 0xc02
++#define CSR_STATS 0xc0
++#define CSR_UARCH0 0xcc0
++#define CSR_UARCH1 0xcc1
++#define CSR_UARCH2 0xcc2
++#define CSR_UARCH3 0xcc3
++#define CSR_UARCH4 0xcc4
++#define CSR_UARCH5 0xcc5
++#define CSR_UARCH6 0xcc6
++#define CSR_UARCH7 0xcc7
++#define CSR_UARCH8 0xcc8
++#define CSR_UARCH9 0xcc9
++#define CSR_UARCH10 0xcca
++#define CSR_UARCH11 0xccb
++#define CSR_UARCH12 0xccc
++#define CSR_UARCH13 0xccd
++#define CSR_UARCH14 0xcce
++#define CSR_UARCH15 0xccf
++#define CSR_SSTATUS 0x100
++#define CSR_SIE 0x104
++#define CSR_STVEC 0x105
++#define CSR_SSCRATCH 0x140
++#define CSR_SEPC 0x141
++#define CSR_SCAUSE 0x142
++#define CSR_SBADADDR 0x143
++#define CSR_SIP 0x144
++#define CSR_SPTBR 0x180
++#define CSR_SASID 0x181
++#define CSR_SCYCLE 0xd00
++#define CSR_STIME 0xd01
++#define CSR_SINSTRET 0xd02
++#define CSR_MSTATUS 0x300
++#define CSR_MEDELEG 0x302
++#define CSR_MIDELEG 0x303
++#define CSR_MIE 0x304
++#define CSR_MTVEC 0x305
++#define CSR_MTIMECMP 0x321
++#define CSR_MSCRATCH 0x340
++#define CSR_MEPC 0x341
++#define CSR_MCAUSE 0x342
++#define CSR_MBADADDR 0x343
++#define CSR_MIP 0x344
++#define CSR_MIPI 0x345
++#define CSR_MUCOUNTEREN 0x310
++#define CSR_MSCOUNTEREN 0x311
++#define CSR_MUCYCLE_DELTA 0x700
++#define CSR_MUTIME_DELTA 0x701
++#define CSR_MUINSTRET_DELTA 0x702
++#define CSR_MSCYCLE_DELTA 0x704
++#define CSR_MSTIME_DELTA 0x705
++#define CSR_MSINSTRET_DELTA 0x706
++#define CSR_MCYCLE 0xf00
++#define CSR_MTIME 0xf01
++#define CSR_MINSTRET 0xf02
++#define CSR_MISA 0xf10
++#define CSR_MVENDORID 0xf11
++#define CSR_MARCHID 0xf12
++#define CSR_MIMPID 0xf13
++#define CSR_MCFGADDR 0xf14
++#define CSR_MHARTID 0xf15
++#define CSR_MTOHOST 0x7c0
++#define CSR_MFROMHOST 0x7c1
++#define CSR_MRESET 0x7c2
++#define CSR_CYCLEH 0xc80
++#define CSR_TIMEH 0xc81
++#define CSR_INSTRETH 0xc82
++#define CSR_MTIMECMPH 0x361
++#define CSR_MUCYCLE_DELTAH 0x780
++#define CSR_MUTIME_DELTAH 0x781
++#define CSR_MUINSTRET_DELTAH 0x782
++#define CSR_MSCYCLE_DELTAH 0x784
++#define CSR_MSTIME_DELTAH 0x785
++#define CSR_MSINSTRET_DELTAH 0x786
++#define CSR_MCYCLEH 0xf80
++#define CSR_MTIMEH 0xf81
++#define CSR_MINSTRETH 0xf82
++#define CAUSE_MISALIGNED_FETCH 0x0
++#define CAUSE_FAULT_FETCH 0x1
++#define CAUSE_ILLEGAL_INSTRUCTION 0x2
++#define CAUSE_BREAKPOINT 0x3
++#define CAUSE_MISALIGNED_LOAD 0x4
++#define CAUSE_FAULT_LOAD 0x5
++#define CAUSE_MISALIGNED_STORE 0x6
++#define CAUSE_FAULT_STORE 0x7
++#define CAUSE_USER_ECALL 0x8
++#define CAUSE_SUPERVISOR_ECALL 0x9
++#define CAUSE_HYPERVISOR_ECALL 0xa
++#define CAUSE_MACHINE_ECALL 0xb
++#endif
++#ifdef DECLARE_INSN
++DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
++DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
++DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
++DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
++DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
++DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
++DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
++DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
++DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
++DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
++DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
++DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
++DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
++DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
++DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
++DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
++DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
++DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
++DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
++DECLARE_INSN(eret, MATCH_ERET, MASK_ERET)
++DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
++DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
++DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
++DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
++DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
++DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
++DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
++DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
++DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
++DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
++DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
++DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
++DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
++DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
++DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
++DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
++DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
++DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
++DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
++DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
++DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
++DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
++DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
++DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
++DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
++DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
++DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
++DECLARE_INSN(or, MATCH_OR, MASK_OR)
++DECLARE_INSN(and, MATCH_AND, MASK_AND)
++DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
++DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
++DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
++DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
++DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
++DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
++DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
++DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
++DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
++DECLARE_INSN(lb, MATCH_LB, MASK_LB)
++DECLARE_INSN(lh, MATCH_LH, MASK_LH)
++DECLARE_INSN(lw, MATCH_LW, MASK_LW)
++DECLARE_INSN(ld, MATCH_LD, MASK_LD)
++DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
++DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
++DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
++DECLARE_INSN(sb, MATCH_SB, MASK_SB)
++DECLARE_INSN(sh, MATCH_SH, MASK_SH)
++DECLARE_INSN(sw, MATCH_SW, MASK_SW)
++DECLARE_INSN(sd, MATCH_SD, MASK_SD)
++DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
++DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
++DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
++DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
++DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
++DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
++DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
++DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
++DECLARE_INSN(rem, MATCH_REM, MASK_REM)
++DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
++DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
++DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
++DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
++DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
++DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
++DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
++DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
++DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
++DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
++DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
++DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
++DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
++DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
++DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
++DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
++DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
++DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
++DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
++DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
++DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
++DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
++DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
++DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
++DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
++DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
++DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
++DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
++DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
++DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
++DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
++DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
++DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
++DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
++DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
++DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
++DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
++DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
++DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
++DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
++DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
++DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
++DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
++DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
++DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
++DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
++DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
++DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
++DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
++DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
++DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
++DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
++DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
++DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
++DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
++DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
++DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
++DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
++DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
++DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
++DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
++DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
++DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
++DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
++DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
++DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
++DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
++DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
++DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
++DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
++DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
++DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
++DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
++DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
++DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
++DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
++DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
++DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
++DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
++DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
++DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
++DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
++DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
++DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
++DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
++DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
++DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
++DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
++DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
++DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
++DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
++DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
++DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
++DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
++DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
++DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
++DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
++DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
++DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
++DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
++DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
++DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
++DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
++DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
++DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
++DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
++DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
++DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
++DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
++DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
++DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
++DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
++DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
++DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
++DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
++DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
++DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
++DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
++DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
++DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
++DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
++DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
++DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
++DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
++DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
++DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
++DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
++DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
++DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
++DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
++DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
++DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
++DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
++DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
++DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
++DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
++DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
++DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
++DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
++DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
++DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
++DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
++DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
++DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
++DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
++DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
++DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
++DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
++DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
++DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
++DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
++DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
++DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
++DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
++DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
++DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
++DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
++DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
++DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
++DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
++DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
++DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
++DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
++DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
++DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
++DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
++DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
++#endif
++#ifdef DECLARE_CSR
++DECLARE_CSR(fflags, CSR_FFLAGS)
++DECLARE_CSR(frm, CSR_FRM)
++DECLARE_CSR(fcsr, CSR_FCSR)
++DECLARE_CSR(cycle, CSR_CYCLE)
++DECLARE_CSR(time, CSR_TIME)
++DECLARE_CSR(instret, CSR_INSTRET)
++DECLARE_CSR(stats, CSR_STATS)
++DECLARE_CSR(uarch0, CSR_UARCH0)
++DECLARE_CSR(uarch1, CSR_UARCH1)
++DECLARE_CSR(uarch2, CSR_UARCH2)
++DECLARE_CSR(uarch3, CSR_UARCH3)
++DECLARE_CSR(uarch4, CSR_UARCH4)
++DECLARE_CSR(uarch5, CSR_UARCH5)
++DECLARE_CSR(uarch6, CSR_UARCH6)
++DECLARE_CSR(uarch7, CSR_UARCH7)
++DECLARE_CSR(uarch8, CSR_UARCH8)
++DECLARE_CSR(uarch9, CSR_UARCH9)
++DECLARE_CSR(uarch10, CSR_UARCH10)
++DECLARE_CSR(uarch11, CSR_UARCH11)
++DECLARE_CSR(uarch12, CSR_UARCH12)
++DECLARE_CSR(uarch13, CSR_UARCH13)
++DECLARE_CSR(uarch14, CSR_UARCH14)
++DECLARE_CSR(uarch15, CSR_UARCH15)
++DECLARE_CSR(sstatus, CSR_SSTATUS)
++DECLARE_CSR(sie, CSR_SIE)
++DECLARE_CSR(stvec, CSR_STVEC)
++DECLARE_CSR(sscratch, CSR_SSCRATCH)
++DECLARE_CSR(sepc, CSR_SEPC)
++DECLARE_CSR(scause, CSR_SCAUSE)
++DECLARE_CSR(sbadaddr, CSR_SBADADDR)
++DECLARE_CSR(sip, CSR_SIP)
++DECLARE_CSR(sptbr, CSR_SPTBR)
++DECLARE_CSR(sasid, CSR_SASID)
++DECLARE_CSR(scycle, CSR_SCYCLE)
++DECLARE_CSR(stime, CSR_STIME)
++DECLARE_CSR(sinstret, CSR_SINSTRET)
++DECLARE_CSR(mstatus, CSR_MSTATUS)
++DECLARE_CSR(medeleg, CSR_MEDELEG)
++DECLARE_CSR(mideleg, CSR_MIDELEG)
++DECLARE_CSR(mie, CSR_MIE)
++DECLARE_CSR(mtvec, CSR_MTVEC)
++DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
++DECLARE_CSR(mscratch, CSR_MSCRATCH)
++DECLARE_CSR(mepc, CSR_MEPC)
++DECLARE_CSR(mcause, CSR_MCAUSE)
++DECLARE_CSR(mbadaddr, CSR_MBADADDR)
++DECLARE_CSR(mip, CSR_MIP)
++DECLARE_CSR(mipi, CSR_MIPI)
++DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
++DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
++DECLARE_CSR(mucycle_delta, CSR_MUCYCLE_DELTA)
++DECLARE_CSR(mutime_delta, CSR_MUTIME_DELTA)
++DECLARE_CSR(muinstret_delta, CSR_MUINSTRET_DELTA)
++DECLARE_CSR(mscycle_delta, CSR_MSCYCLE_DELTA)
++DECLARE_CSR(mstime_delta, CSR_MSTIME_DELTA)
++DECLARE_CSR(msinstret_delta, CSR_MSINSTRET_DELTA)
++DECLARE_CSR(mcycle, CSR_MCYCLE)
++DECLARE_CSR(mtime, CSR_MTIME)
++DECLARE_CSR(minstret, CSR_MINSTRET)
++DECLARE_CSR(misa, CSR_MISA)
++DECLARE_CSR(mvendorid, CSR_MVENDORID)
++DECLARE_CSR(marchid, CSR_MARCHID)
++DECLARE_CSR(mimpid, CSR_MIMPID)
++DECLARE_CSR(mcfgaddr, CSR_MCFGADDR)
++DECLARE_CSR(mhartid, CSR_MHARTID)
++DECLARE_CSR(mtohost, CSR_MTOHOST)
++DECLARE_CSR(mfromhost, CSR_MFROMHOST)
++DECLARE_CSR(mreset, CSR_MRESET)
++DECLARE_CSR(cycleh, CSR_CYCLEH)
++DECLARE_CSR(timeh, CSR_TIMEH)
++DECLARE_CSR(instreth, CSR_INSTRETH)
++DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
++DECLARE_CSR(mucycle_deltah, CSR_MUCYCLE_DELTAH)
++DECLARE_CSR(mutime_deltah, CSR_MUTIME_DELTAH)
++DECLARE_CSR(muinstret_deltah, CSR_MUINSTRET_DELTAH)
++DECLARE_CSR(mscycle_deltah, CSR_MSCYCLE_DELTAH)
++DECLARE_CSR(mstime_deltah, CSR_MSTIME_DELTAH)
++DECLARE_CSR(msinstret_deltah, CSR_MSINSTRET_DELTAH)
++DECLARE_CSR(mcycleh, CSR_MCYCLEH)
++DECLARE_CSR(mtimeh, CSR_MTIMEH)
++DECLARE_CSR(minstreth, CSR_MINSTRETH)
++#endif
++#ifdef DECLARE_CAUSE
++DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
++DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
++DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
++DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
++DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
++DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
++DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
++DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
++DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
++DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
++DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
++DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
++#endif
+diff -urN empty/ld/emulparams/elf32lriscv-defs.sh binutils-2.26/ld/emulparams/elf32lriscv-defs.sh
+--- empty/ld/emulparams/elf32lriscv-defs.sh	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/ld/emulparams/elf32lriscv-defs.sh	2016-04-03 10:33:12.065459702 +0800
+@@ -0,0 +1,48 @@
 +# This is an ELF platform.
 +SCRIPT_NAME=elf
 +ARCH=riscv
@@ -8364,9 +7895,10 @@ diff -urN empty/ld/emulparams/elf32lriscv-defs.sh binutils-2.25/ld/emulparams/el
 +TEMPLATE_NAME=elf32
 +EXTRA_EM_FILE=riscvelf
 +
-+case "$EMULATION_NAME" in
-+elf32*) ELFSIZE=32; LIBPATH_SUFFIX=32 ;;
-+elf64*) ELFSIZE=64; LIBPATH_SUFFIX=   ;;
++case x"$EMULATION_NAME" in
++xelf32*) ELFSIZE=32; LIBPATH_SUFFIX=32 ;;
++xelf64*) ELFSIZE=64; LIBPATH_SUFFIX=   ;;
++x) ;;
 +*) echo $0: unhandled emulation $EMULATION_NAME >&2; exit 1 ;;
 +esac
 +
@@ -8381,39 +7913,47 @@ diff -urN empty/ld/emulparams/elf32lriscv-defs.sh binutils-2.25/ld/emulparams/el
 +GENERATE_SHLIB_SCRIPT=yes
 +GENERATE_PIE_SCRIPT=yes
 +
-+TEXT_START_ADDR=0x800000
++TEXT_START_ADDR=0x10000
 +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
 +COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
 +
-+INITIAL_READONLY_SECTIONS=".interp       ${RELOCATING-0} : { *(.interp) }"
 +SDATA_START_SYMBOLS="_gp = . + 0x800;
-+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)"
-+if test -n "${CREATE_SHLIB}"; then
-+  INITIAL_READONLY_SECTIONS=
-+  SDATA_START_SYMBOLS=
-+  OTHER_READONLY_SECTIONS=".srodata      ${RELOCATING-0} : { *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) }"
-+  unset GOT
-+fi
-diff -urN empty/ld/emulparams/elf32lriscv.sh binutils-2.25/ld/emulparams/elf32lriscv.sh
---- binutils-2.25/ld/emulparams/elf32lriscv.sh	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emulparams/elf32lriscv.sh	2015-07-18 00:02:36.222287541 +0200
++    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)"
++
++# Place the data section before text section.  This enables more compact
++# global variable access for RVC code via linker relaxation.
++INITIAL_READONLY_SECTIONS="
++  .data           : { *(.data) *(.data.*) *(.gnu.linkonce.d.*) }
++  .rodata         : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) }
++  .srodata        : { ${SDATA_START_SYMBOLS} }
++  .sdata          : { *(.sdata .sdata.* .gnu.linkonce.s.*) }
++  .sbss           : { *(.dynsbss) *(.sbss .sbss.* .gnu.linkonce.sb.*) }
++  .bss            : { *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) }
++  . = ALIGN(${SEGMENT_SIZE}) + (. & (${MAXPAGESIZE} - 1));"
++INITIAL_READONLY_SECTIONS=".interp         : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}"
++INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}"
++
++SDATA_START_SYMBOLS="${CREATE_PIE+${SDATA_START_SYMBOLS}}"
+diff -urN empty/ld/emulparams/elf32lriscv.sh binutils-2.26/ld/emulparams/elf32lriscv.sh
+--- empty/ld/emulparams/elf32lriscv.sh	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/ld/emulparams/elf32lriscv.sh	2016-04-02 14:07:12.469104719 +0800
 @@ -0,0 +1,2 @@
 +. ${srcdir}/emulparams/elf32lriscv-defs.sh
 +OUTPUT_FORMAT="elf32-littleriscv"
-diff -urN empty/ld/emulparams/elf64lriscv-defs.sh binutils-2.25/ld/emulparams/elf64lriscv-defs.sh
---- binutils-2.25/ld/emulparams/elf64lriscv-defs.sh	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emulparams/elf64lriscv-defs.sh	2015-07-18 00:02:36.222287541 +0200
+diff -urN empty/ld/emulparams/elf64lriscv-defs.sh binutils-2.26/ld/emulparams/elf64lriscv-defs.sh
+--- empty/ld/emulparams/elf64lriscv-defs.sh	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/ld/emulparams/elf64lriscv-defs.sh	2016-04-02 14:07:12.469104719 +0800
 @@ -0,0 +1 @@
 +. ${srcdir}/emulparams/elf32lriscv-defs.sh
-diff -urN empty/ld/emulparams/elf64lriscv.sh binutils-2.25/ld/emulparams/elf64lriscv.sh
---- binutils-2.25/ld/emulparams/elf64lriscv.sh	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emulparams/elf64lriscv.sh	2015-07-18 00:02:36.222287541 +0200
+diff -urN empty/ld/emulparams/elf64lriscv.sh binutils-2.26/ld/emulparams/elf64lriscv.sh
+--- empty/ld/emulparams/elf64lriscv.sh	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/ld/emulparams/elf64lriscv.sh	2016-04-02 14:07:12.469104719 +0800
 @@ -0,0 +1,2 @@
 +. ${srcdir}/emulparams/elf64lriscv-defs.sh
 +OUTPUT_FORMAT="elf64-littleriscv"
-diff -urN empty/ld/emultempl/riscvelf.em binutils-2.25/ld/emultempl/riscvelf.em
---- binutils-2.25/ld/emultempl/riscvelf.em	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/ld/emultempl/riscvelf.em	2015-07-18 00:02:36.222287541 +0200
+diff -urN empty/ld/emultempl/riscvelf.em binutils-2.26/ld/emultempl/riscvelf.em
+--- empty/ld/emultempl/riscvelf.em	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/ld/emultempl/riscvelf.em	2016-04-03 10:33:12.065459702 +0800
 @@ -0,0 +1,68 @@
 +# This shell script emits a C file. -*- C -*-
 +#   Copyright 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
@@ -8466,7 +8006,7 @@ diff -urN empty/ld/emultempl/riscvelf.em binutils-2.25/ld/emultempl/riscvelf.em
 +
 +  /* Don't attempt to discard unused .eh_frame sections until the final link,
 +     as we can't reliably tell if they're used until after relaxation.  */
-+  if (!link_info.relocatable)
++  if (!bfd_link_relocatable (&link_info))
 +    {
 +      need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
 +      if (need_layout < 0)
@@ -8483,12 +8023,12 @@ diff -urN empty/ld/emultempl/riscvelf.em binutils-2.25/ld/emultempl/riscvelf.em
 +
 +LDEMUL_BEFORE_ALLOCATION=riscv_elf_before_allocation
 +LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
-diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
---- binutils-2.25/opcodes/riscv-dis.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/opcodes/riscv-dis.c	2015-07-18 00:02:36.222287541 +0200
-@@ -0,0 +1,590 @@
+diff -urN empty/opcodes/riscv-dis.c binutils-2.26/opcodes/riscv-dis.c
+--- empty/opcodes/riscv-dis.c	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/opcodes/riscv-dis.c	2016-04-03 10:33:12.065459702 +0800
+@@ -0,0 +1,521 @@
 +/* RISC-V disassembler
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
 +   Based on MIPS target.
@@ -8506,9 +8046,8 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +   License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the Free Software
-+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-+   MA 02110-1301, USA.  */
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +#include "sysdep.h"
 +#include "dis-asm.h"
@@ -8576,7 +8115,7 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +  free (opts);
 +}
 +
-+/* Print one argument from an array. */
++/* Print one argument from an array.  */
 +
 +static void
 +arg_print (struct disassemble_info *info, unsigned long val,
@@ -8596,7 +8135,7 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +    }
 +  else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
 +    pd->print_addr = pd->gp + offset;
-+  else if (base_reg == X_TP)
++  else if (base_reg == X_TP || base_reg == 0)
 +    pd->print_addr = offset;
 +}
 +
@@ -8617,122 +8156,48 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +    {
 +      switch (*d)
 +	{
-+        /* Xcustom */
-+        case '^':
-+          switch (*++d)
-+            {
-+            case 'd':
-+              (*info->fprintf_func) (info->stream, "%d", rd);
-+              break;
-+            case 's':
-+              (*info->fprintf_func) (info->stream, "%d", rs1);
-+              break;
-+            case 't':
-+              (*info->fprintf_func)
-+                ( info->stream, "%d", (int)((l >> OP_SH_RS2) & OP_MASK_RS2));
-+              break;
-+            case 'j':
-+              (*info->fprintf_func)
-+                ( info->stream, "%d", (int)((l >> OP_SH_CUSTOM_IMM) & OP_MASK_CUSTOM_IMM));
-+              break;
-+            }
-+          break;
-+
-+        /* Xhwacha */
-+        case '#':
-+          switch ( *++d ) {
-+            case 'g':
-+              (*info->fprintf_func)
-+                ( info->stream, "%d",
-+                  (int)((l >> OP_SH_IMMNGPR) & OP_MASK_IMMNGPR));
-+              break;
-+            case 'f':
-+              (*info->fprintf_func)
-+                ( info->stream, "%d",
-+                  (int)((l >> OP_SH_IMMNFPR) & OP_MASK_IMMNFPR));
-+              break;
-+            case 'p':
-+              (*info->fprintf_func)
-+                ( info->stream, "%d",
-+                 (int)((l >> OP_SH_CUSTOM_IMM) & OP_MASK_CUSTOM_IMM));
-+              break;
-+            case 'n':
-+              (*info->fprintf_func)
-+                ( info->stream, "%d",
-+                  (int)(((l >> OP_SH_IMMSEGNELM) & OP_MASK_IMMSEGNELM) + 1));
-+              break;
-+            case 'd':
-+              (*info->fprintf_func)
-+                ( info->stream, "%s",
-+                  riscv_vec_gpr_names[(l >> OP_SH_VRD) & OP_MASK_VRD]);
-+              break;
-+            case 's':
-+              (*info->fprintf_func)
-+                ( info->stream, "%s",
-+                  riscv_vec_gpr_names[(l >> OP_SH_VRS) & OP_MASK_VRS]);
-+              break;
-+            case 't':
-+              (*info->fprintf_func)
-+                ( info->stream, "%s",
-+                  riscv_vec_gpr_names[(l >> OP_SH_VRT) & OP_MASK_VRT]);
-+              break;
-+            case 'r':
-+              (*info->fprintf_func)
-+                ( info->stream, "%s",
-+                  riscv_vec_gpr_names[(l >> OP_SH_VRR) & OP_MASK_VRR]);
-+              break;
-+            case 'D':
-+              (*info->fprintf_func)
-+                ( info->stream, "%s",
-+                  riscv_vec_fpr_names[(l >> OP_SH_VFD) & OP_MASK_VFD]);
-+              break;
-+            case 'S':
-+              (*info->fprintf_func)
-+                ( info->stream, "%s",
-+                  riscv_vec_fpr_names[(l >> OP_SH_VFS) & OP_MASK_VFS]);
-+              break;
-+            case 'T':
-+              (*info->fprintf_func)
-+                ( info->stream, "%s",
-+                  riscv_vec_fpr_names[(l >> OP_SH_VFT) & OP_MASK_VFT]);
-+              break;
-+            case 'R':
-+              (*info->fprintf_func)
-+                ( info->stream, "%s",
-+                  riscv_vec_fpr_names[(l >> OP_SH_VFR) & OP_MASK_VFR]);
-+              break;
-+          }
-+          break;
++	/* Xcustom */
++	case '^':
++	  switch (*++d)
++	    {
++	    case 'd':
++	      print (info->stream, "%d", rd);
++	      break;
++	    case 's':
++	      print (info->stream, "%d", rs1);
++	      break;
++	    case 't':
++	      print (info->stream, "%d", (int) EXTRACT_OPERAND (RS2, l));
++	      break;
++	    case 'j':
++	      print (info->stream, "%d", (int) EXTRACT_OPERAND (CUSTOM_IMM, l));
++	      break;
++	    }
++	  break;
 +
 +	case 'C': /* RVC */
 +	  switch (*++d)
 +	    {
-+	    case 'd': /* RD x8-x15 */
-+	      print (info->stream, "%s",
-+		     riscv_gpr_names[((l >> OP_SH_CRDS) & OP_MASK_CRDS) + 8]);
-+	      break;
 +	    case 's': /* RS1 x8-x15 */
 +	    case 'w': /* RS1 x8-x15 */
 +	      print (info->stream, "%s",
-+		     riscv_gpr_names[((l >> OP_SH_CRS1S) & OP_MASK_CRS1S) + 8]);
++		     riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
 +	      break;
 +	    case 't': /* RS2 x8-x15 */
 +	    case 'x': /* RS2 x8-x15 */
 +	      print (info->stream, "%s",
-+		     riscv_gpr_names[((l >> OP_SH_CRS2S) & OP_MASK_CRS2S) + 8]);
++		     riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
 +	      break;
 +	    case 'U': /* RS1, constrained to equal RD */
-+	    case 'D': /* RS1 or RD, nonzero */
 +	      print (info->stream, "%s", riscv_gpr_names[rd]);
 +	      break;
 +	    case 'c': /* RS1, constrained to equal sp */
 +	      print (info->stream, "%s", riscv_gpr_names[X_SP]);
-+	      continue;
-+	    case 'T': /* RS2, nonzero */
++	      break;
 +	    case 'V': /* RS2 */
 +	      print (info->stream, "%s",
-+		     riscv_gpr_names[(l >> OP_SH_CRS2) & OP_MASK_CRS2]);
-+	      continue;
++		     riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
++	      break;
 +	    case 'i':
 +	      print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
 +	      break;
@@ -8773,13 +8238,21 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +	      break;
 +	    case 'u':
 +	      print (info->stream, "0x%x",
-+		     (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
++		     (int) (EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
 +	      break;
 +	    case '>':
-+	      print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
++	      print (info->stream, "0x%x", (int) EXTRACT_RVC_IMM (l) & 0x3f);
 +	      break;
 +	    case '<':
-+	      print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
++	      print (info->stream, "0x%x", (int) EXTRACT_RVC_IMM (l) & 0x1f);
++	      break;
++	    case 'T': /* floating-point RS2 */
++	      print (info->stream, "%s",
++		     riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
++	      break;
++	    case 'D': /* floating-point RS2 x8-x15 */
++	      print (info->stream, "%s",
++		     riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
 +	      break;
 +	    }
 +	  break;
@@ -8789,7 +8262,7 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +	case ')':
 +	case '[':
 +	case ']':
-+	  (*info->fprintf_func) (info->stream, "%c", *d);
++	  print (info->stream, "%c", *d);
 +	  break;
 +
 +	case '0':
@@ -8800,44 +8273,46 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +
 +	case 'b':
 +	case 's':
-+	  (*info->fprintf_func) (info->stream, "%s", riscv_gpr_names[rs1]);
++	  print (info->stream, "%s", riscv_gpr_names[rs1]);
 +	  break;
 +
 +	case 't':
-+	  (*info->fprintf_func) (info->stream, "%s",
-+				 riscv_gpr_names[(l >> OP_SH_RS2) & OP_MASK_RS2]);
++	  print (info->stream, "%s",
++		 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
 +	  break;
 +
 +	case 'u':
-+	  (*info->fprintf_func) (info->stream, "0x%x", (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
++	  print (info->stream, "0x%x",
++		 (unsigned) EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
 +	  break;
 +
 +	case 'm':
-+	  arg_print(info, (l >> OP_SH_RM) & OP_MASK_RM,
-+		    riscv_rm, ARRAY_SIZE(riscv_rm));
++	  arg_print (info, EXTRACT_OPERAND (RM, l),
++		     riscv_rm, ARRAY_SIZE (riscv_rm));
 +	  break;
 +
 +	case 'P':
-+	  arg_print(info, (l >> OP_SH_PRED) & OP_MASK_PRED,
-+	            riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ));
++	  arg_print (info, EXTRACT_OPERAND (PRED, l),
++		     riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
 +	  break;
 +
 +	case 'Q':
-+	  arg_print(info, (l >> OP_SH_SUCC) & OP_MASK_SUCC,
-+	            riscv_pred_succ, ARRAY_SIZE(riscv_pred_succ));
++	  arg_print (info, EXTRACT_OPERAND (SUCC, l),
++		     riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
 +	  break;
 +
 +	case 'o':
 +	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
 +	case 'j':
-+	  if ((l & MASK_ADDI) == MATCH_ADDI || (l & MASK_JALR) == MATCH_JALR)
++	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
++	      || (l & MASK_JALR) == MATCH_JALR)
 +	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
-+	  (*info->fprintf_func) (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
++	  print (info->stream, "%d", (int) EXTRACT_ITYPE_IMM (l));
 +	  break;
 +
 +	case 'q':
 +	  maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
-+	  (*info->fprintf_func) (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
++	  print (info->stream, "%d", (int) EXTRACT_STYPE_IMM (l));
 +	  break;
 +
 +	case 'a':
@@ -8855,68 +8330,65 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +	    pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
 +	  else if ((l & MASK_LUI) == MATCH_LUI)
 +	    pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
-+	  (*info->fprintf_func) (info->stream, "%s", riscv_gpr_names[rd]);
++	  else if ((l & MASK_C_LUI) == MATCH_C_LUI)
++	    pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
++	  print (info->stream, "%s", riscv_gpr_names[rd]);
 +	  break;
 +
 +	case 'z':
-+	  (*info->fprintf_func) (info->stream, "%s", riscv_gpr_names[0]);
++	  print (info->stream, "%s", riscv_gpr_names[0]);
 +	  break;
 +
 +	case '>':
-+	  (*info->fprintf_func) (info->stream, "0x%x",
-+				 (unsigned)((l >> OP_SH_SHAMT) & OP_MASK_SHAMT));
++	  print (info->stream, "0x%x", (int) EXTRACT_OPERAND (SHAMT, l));
 +	  break;
 +
 +	case '<':
-+	  (*info->fprintf_func) (info->stream, "0x%x",
-+				 (unsigned)((l >> OP_SH_SHAMTW) & OP_MASK_SHAMTW));
++	  print (info->stream, "0x%x", (int) EXTRACT_OPERAND (SHAMTW, l));
 +	  break;
 +
 +	case 'S':
 +	case 'U':
-+	  (*info->fprintf_func) (info->stream, "%s", riscv_fpr_names[rs1]);
++	  print (info->stream, "%s", riscv_fpr_names[rs1]);
 +	  break;
 +
 +	case 'T':
-+	  (*info->fprintf_func) (info->stream, "%s",
-+				 riscv_fpr_names[(l >> OP_SH_RS2) & OP_MASK_RS2]);
++	  print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
 +	  break;
 +
 +	case 'D':
-+	  (*info->fprintf_func) (info->stream, "%s", riscv_fpr_names[rd]);
++	  print (info->stream, "%s", riscv_fpr_names[rd]);
 +	  break;
 +
 +	case 'R':
-+	  (*info->fprintf_func) (info->stream, "%s",
-+				 riscv_fpr_names[(l >> OP_SH_RS3) & OP_MASK_RS3]);
++	  print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
 +	  break;
 +
 +	case 'E':
 +	  {
 +	    const char* csr_name = NULL;
-+	    unsigned int csr = (l >> OP_SH_CSR) & OP_MASK_CSR;
++	    unsigned int csr = EXTRACT_OPERAND (CSR, l);
 +	    switch (csr)
 +	      {
-+		#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
-+		#include "opcode/riscv-opc.h"
-+		#undef DECLARE_CSR
++	      #define DECLARE_CSR(name, num) case num: csr_name = #name; break;
++	      #include "opcode/riscv-opc.h"
++	      #undef DECLARE_CSR
 +	      }
 +	    if (csr_name)
-+	      (*info->fprintf_func) (info->stream, "%s", csr_name);
++	      print (info->stream, "%s", csr_name);
 +	    else
-+	      (*info->fprintf_func) (info->stream, "0x%x", csr);
++	      print (info->stream, "0x%x", csr);
 +	    break;
 +	  }
 +
 +	case 'Z':
-+	  (*info->fprintf_func) (info->stream, "%d", rs1);
++	  print (info->stream, "%d", rs1);
 +	  break;
 +
 +	default:
 +	  /* xgettext:c-format */
-+	  (*info->fprintf_func) (info->stream,
-+				 _("# internal error, undefined modifier (%c)"),
-+				 *d);
++	  print (info->stream, _("# internal error, undefined modifier (%c)"),
++		 *d);
 +	  return;
 +	}
 +    }
@@ -8936,16 +8408,14 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +  struct riscv_private_data *pd;
 +  int insnlen;
 +
-+#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : 0x7f))
++#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
 +
 +  /* Build a hash table to shorten the search time.  */
 +  if (! init)
 +    {
 +      for (op = riscv_opcodes; op < &riscv_opcodes[NUMOPCODES]; op++)
-+        {
-+	  if (!riscv_hash[OP_HASH_IDX (op->match)])
-+	    riscv_hash[OP_HASH_IDX (op->match)] = op;
-+        }
++	if (!riscv_hash[OP_HASH_IDX (op->match)])
++	  riscv_hash[OP_HASH_IDX (op->match)] = op;
 +
 +      init = 1;
 +    }
@@ -8957,7 +8427,7 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +      pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
 +      pd->gp = -1;
 +      pd->print_addr = -1;
-+      for (i = 0; i < (int) ARRAY_SIZE(pd->hi_addr); i++)
++      for (i = 0; i < (int) ARRAY_SIZE (pd->hi_addr); i++)
 +	pd->hi_addr[i] = -1;
 +
 +      for (i = 0; i < info->symtab_size; i++)
@@ -8982,44 +8452,45 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +  op = riscv_hash[OP_HASH_IDX (word)];
 +  if (op != NULL)
 +    {
-+      const char *extension = NULL;
 +      int xlen = 0;
 +
 +      /* The incoming section might not always be complete.  */
 +      if (info->section != NULL)
 +	{
 +	  Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
-+	  unsigned int e_flags = ehdr->e_flags;
-+	  extension = riscv_elf_flag_to_name (EF_GET_RISCV_EXT (e_flags));
-+
-+	  xlen = 32;
-+	  if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
-+	    xlen = 64;
++	  xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
 +	}
 +
 +      for (; op < &riscv_opcodes[NUMOPCODES]; op++)
 +	{
-+	  if ((op->match_func) (op, word)
-+	      && !(no_aliases && (op->pinfo & INSN_ALIAS))
-+	      && !(op->subset[0] == 'X' && extension != NULL
-+		   && strcmp (op->subset, extension))
-+	      && !(isdigit(op->subset[0]) && atoi(op->subset) != xlen))
++	  /* Does the opcode match?  */
++	  if (! (op->match_func) (op, word))
++	    continue;
++	  /* Is this a pseudo-instruction and may we print it as such?  */
++	  if (no_aliases && (op->pinfo & INSN_ALIAS))
++	    continue;
++	  /* Is this instruction restricted to a certain value of XLEN?  */
++	  if (isdigit (op->subset[0]) && atoi (op->subset) != xlen)
++	    continue;
++
++	  /* It's a match.  */
++	  (*info->fprintf_func) (info->stream, "%s", op->name);
++	  print_insn_args (op->args, word, memaddr, info);
++
++	  /* Try to disassemble multi-instruction addressing sequences.  */
++	  if (pd->print_addr != (bfd_vma)-1)
 +	    {
-+	      (*info->fprintf_func) (info->stream, "%s", op->name);
-+	      print_insn_args (op->args, word, memaddr, info);
-+	      if (pd->print_addr != (bfd_vma)-1)
-+		{
-+		  info->target = pd->print_addr;
-+		  (*info->fprintf_func) (info->stream, " # ");
-+		  (*info->print_address_func) (info->target, info);
-+		  pd->print_addr = -1;
-+		}
-+	      return insnlen;
++	      info->target = pd->print_addr;
++	      (*info->fprintf_func) (info->stream, " # ");
++	      (*info->print_address_func) (info->target, info);
++	      pd->print_addr = -1;
 +	    }
++
++	  return insnlen;
 +	}
 +    }
 +
-+  /* Handle undefined instructions.  */
++  /* We did not find a match, so just print the instruction bits.  */
 +  info->insn_type = dis_noninsn;
 +  (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
 +  return insnlen;
@@ -9028,7 +8499,7 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +int
 +print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
 +{
-+  uint16_t i2;
++  bfd_byte packet[2];
 +  insn_t insn = 0;
 +  bfd_vma n;
 +  int status;
@@ -9043,19 +8514,19 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +    set_default_riscv_dis_options ();
 +
 +  /* Instructions are a sequence of 2-byte packets in little-endian order.  */
-+  for (n = 0; n < sizeof(insn) && n < riscv_insn_length (insn); n += 2)
++  for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
 +    {
-+      status = (*info->read_memory_func) (memaddr + n, (bfd_byte*)&i2, 2, info);
++      status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
 +      if (status != 0)
 +	{
-+	  if (n > 0) /* Don't fail just because we fell off the end. */
++	  /* Don't fail just because we fell off the end.  */
++	  if (n > 0)
 +	    break;
 +	  (*info->memory_error_func) (status, memaddr, info);
 +	  return status;
 +	}
 +
-+      i2 = bfd_getl16 (&i2);
-+      insn |= (insn_t)i2 << (8*n);
++      insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n);
 +    }
 +
 +  return riscv_disassemble_insn (memaddr, insn, info);
@@ -9077,12 +8548,12 @@ diff -urN empty/opcodes/riscv-dis.c binutils-2.25/opcodes/riscv-dis.c
 +
 +  fprintf (stream, _("\n"));
 +}
-diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
---- binutils-2.25/opcodes/riscv-opc.c	1970-01-01 01:00:00.000000000 +0100
-+++ binutils-2.25/opcodes/riscv-opc.c	2015-07-18 00:02:36.222287541 +0200
-@@ -0,0 +1,867 @@
+diff -urN empty/opcodes/riscv-opc.c binutils-2.26/opcodes/riscv-opc.c
+--- empty/opcodes/riscv-opc.c	1970-01-01 08:00:00.000000000 +0800
++++ binutils-2.26/opcodes/riscv-opc.c	2016-04-16 11:38:25.314563423 +0800
+@@ -0,0 +1,647 @@
 +/* RISC-V opcode list
-+   Copyright 2011-2014 Free Software Foundation, Inc.
++   Copyright 2011-2015 Free Software Foundation, Inc.
 +
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
 +   Based on MIPS target.
@@ -9100,9 +8571,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +   License for more details.
 +
 +   You should have received a copy of the GNU General Public License
-+   along with this file; see the file COPYING.  If not, write to the
-+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
-+   MA 02110-1301, USA.  */
++   along with this program; see the file COPYING3. If not,
++   see <http://www.gnu.org/licenses/>.  */
 +
 +#include "sysdep.h"
 +#include "opcode/riscv.h"
@@ -9140,22 +8610,6 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
 +};
 +
-+const char * const riscv_vec_gpr_names[32] =
-+{
-+  "vx0",  "vx1",  "vx2",  "vx3",  "vx4",  "vx5",  "vx6",  "vx7",
-+  "vx8",  "vx9",  "vx10", "vx11", "vx12", "vx13", "vx14", "vx15",
-+  "vx16", "vx17", "vx18", "vx19", "vx20", "vx21", "vx22", "vx23",
-+  "vx24", "vx25", "vx26", "vx27", "vx28", "vx29", "vx30", "vx31"
-+};
-+
-+const char * const riscv_vec_fpr_names[32] =
-+{
-+  "vf0",  "vf1",  "vf2",  "vf3",  "vf4",  "vf5",  "vf6",  "vf7",
-+  "vf8",  "vf9",  "vf10", "vf11", "vf12", "vf13", "vf14", "vf15",
-+  "vf16", "vf17", "vf18", "vf19", "vf20", "vf21", "vf22", "vf23",
-+  "vf24", "vf25", "vf26", "vf27", "vf28", "vf29", "vf30", "vf31"
-+};
-+
 +/* The order of overloaded instructions matters.  Label arguments and
 +   register arguments look the same. Instructions that can have either
 +   for arguments must apear in the correct order in this table for the
@@ -9164,19 +8618,12 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +   registers.
 +
 +   Because of the lookup algorithm used, entries with the same opcode
-+   name must be contiguous. */
-+
-+#define WR_xd INSN_WRITE_GPR_D
-+#define WR_fd INSN_WRITE_FPR_D
-+#define RD_xs1 INSN_READ_GPR_S
-+#define RD_xs2 INSN_READ_GPR_T
-+#define RD_fs1 INSN_READ_FPR_S
-+#define RD_fs2 INSN_READ_FPR_T
-+#define RD_fs3 INSN_READ_FPR_R
++   name must be contiguous.  */
 +
 +#define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1)
 +#define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2)
 +#define MASK_RD (OP_MASK_RD << OP_SH_RD)
++#define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2)
 +#define MASK_IMM ENCODE_ITYPE_IMM(-1U)
 +#define MASK_RVC_IMM ENCODE_RVC_IMM(-1U)
 +#define MASK_UIMM ENCODE_UTYPE_IMM(-1U)
@@ -9200,13 +8647,24 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +
 +static int match_rs1_eq_rs2(const struct riscv_opcode *op, insn_t insn)
 +{
-+  return match_opcode(op, insn) &&
-+    ((insn & MASK_RS1) >> OP_SH_RS1) == ((insn & MASK_RS2) >> OP_SH_RS2);
++  int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
++  int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
++  return match_opcode (op, insn) && rs1 == rs2;
 +}
 +
 +static int match_rd_nonzero(const struct riscv_opcode *op, insn_t insn)
 +{
-+  return match_opcode(op, insn) && ((insn & MASK_RD) != 0);
++  return match_opcode (op, insn) && ((insn & MASK_RD) != 0);
++}
++
++static int match_c_add(const struct riscv_opcode *op, insn_t insn)
++{
++  return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0);
++}
++
++static int match_c_lui(const struct riscv_opcode *op, insn_t insn)
++{
++  return match_rd_nonzero (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2);
 +}
 +
 +const struct riscv_opcode riscv_builtin_opcodes[] =
@@ -9215,570 +8673,494 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +{"unimp",     "C",   "",  0, 0xffffU,  match_opcode, 0 },
 +{"unimp",     "I",   "",  MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU,  match_opcode, 0 }, /* csrw cycle, x0 */
 +{"ebreak",    "C",   "",  MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
-+{"ebreak",    "I",   "",    MATCH_EBREAK, MASK_EBREAK, match_opcode,   0 },
++{"ebreak",    "I",   "",    MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 },
 +{"sbreak",    "C",   "",  MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
-+{"sbreak",    "I",   "",    MATCH_EBREAK, MASK_EBREAK, match_opcode,   INSN_ALIAS },
++{"sbreak",    "I",   "",    MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS },
 +{"ret",       "C",   "",  MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS },
-+{"ret",       "I",   "",  MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jr",        "C",   "CD",  MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS },
-+{"jr",        "I",   "s",  MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jr",        "I",   "s,j",  MATCH_JALR, MASK_JALR | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr",      "C",   "CD",  MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS },
-+{"jalr",      "I",   "s",  MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr",      "I",   "s,j",  MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr",      "I",   "d,s",  MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"jalr",      "I",   "d,s,j",  MATCH_JALR, MASK_JALR, match_opcode,   WR_xd|RD_xs1 },
++{"ret",       "I",   "",  MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
++{"jr",        "C",   "d",  MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS },
++{"jr",        "I",   "s",  MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS },
++{"jr",        "I",   "s,j",  MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS },
++{"jalr",      "C",   "d",  MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS },
++{"jalr",      "I",   "s",  MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS },
++{"jalr",      "I",   "s,j",  MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS },
++{"jalr",      "I",   "d,s",  MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS },
++{"jalr",      "I",   "d,s,j",  MATCH_JALR, MASK_JALR, match_opcode, 0 },
 +{"j",         "C",   "Ca",  MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS },
-+{"j",         "I",   "a",  MATCH_JAL, MASK_JAL | MASK_RD, match_opcode,   INSN_ALIAS },
-+{"jal",       "C",   "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
-+{"jal",       "I",   "a",  MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode,   INSN_ALIAS|WR_xd },
-+{"jal",       "I",   "d,a",  MATCH_JAL, MASK_JAL, match_opcode,   WR_xd },
-+{"call",      "I",   "c", (X_T0 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
-+{"call",      "I",   "d,c", (X_T0 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
-+{"tail",      "I",   "c", (X_T0 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
++{"j",         "I",   "a",  MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
++{"jal",       "32C", "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
++{"jal",       "I",   "a",  MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
++{"jal",       "I",   "d,a",  MATCH_JAL, MASK_JAL, match_opcode, 0 },
++{"call",      "I",   "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL,  match_never, INSN_MACRO },
++{"call",      "I",   "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
++{"tail",      "I",   "c", (X_T1 << OP_SH_RS1), (int) M_CALL,  match_never, INSN_MACRO },
 +{"jump",      "I",   "c,s", 0, (int) M_CALL,  match_never, INSN_MACRO },
-+{"nop",       "C",   "",  MATCH_C_ADDI16SP, 0xffff, match_opcode, INSN_ALIAS },
-+{"nop",       "I",   "",         MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode,  INSN_ALIAS },
-+{"lui",       "C",   "CD,Cu",  MATCH_C_LUI, MASK_C_LUI, match_rd_nonzero, INSN_ALIAS },
-+{"lui",       "I",   "d,u",  MATCH_LUI, MASK_LUI, match_opcode,   WR_xd },
-+{"li",        "C",   "CD,Cv",  MATCH_C_LUI, MASK_C_LUI, match_rd_nonzero, INSN_ALIAS },
-+{"li",        "C",   "CD,Cj",  MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
-+{"li",        "C",   "CD,0",  MATCH_C_MV, MASK_C_MV | (OP_MASK_CRS2 << OP_SH_CRS2), match_rd_nonzero, INSN_ALIAS },
-+{"li",        "I",   "d,j",      MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode,  INSN_ALIAS|WR_xd }, /* addi */
++{"nop",       "C",   "",  MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },
++{"nop",       "I",   "",         MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
++{"lui",       "C",   "d,Cu",  MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS },
++{"lui",       "I",   "d,u",  MATCH_LUI, MASK_LUI, match_opcode, 0 },
++{"li",        "C",   "d,Cv",  MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS },
++{"li",        "C",   "d,Cj",  MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS },
++{"li",        "C",   "d,0",  MATCH_C_LI, MASK_C_LI | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
++{"li",        "I",   "d,j",      MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */
 +{"li",        "I",   "d,I",  0,    (int) M_LI,  match_never, INSN_MACRO },
-+{"mv",        "C",   "CD,CV",  MATCH_C_MV, MASK_C_MV, match_rd_nonzero, INSN_ALIAS },
-+{"mv",        "I",   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"move",      "C",   "CD,CV",  MATCH_C_MV, MASK_C_MV, match_rd_nonzero, INSN_ALIAS },
-+{"move",      "I",   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"andi",      "32C", "CD,CU,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_rd_nonzero, INSN_ALIAS },
-+{"andi",      "32C", "Ct,Cs,Ci",  MATCH_C_ANDIN, MASK_C_ANDIN, match_opcode, INSN_ALIAS },
-+{"andi",      "I",   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode,   WR_xd|RD_xs1 },
-+{"and",       "C",   "Cd,Cs,Ct",  MATCH_C_AND3, MASK_C_AND3, match_opcode, INSN_ALIAS },
-+{"and",       "32C", "CD,CU,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_rd_nonzero, INSN_ALIAS },
-+{"and",       "32C", "Ct,Cs,Ci",  MATCH_C_ANDIN, MASK_C_ANDIN, match_opcode, INSN_ALIAS },
-+{"and",       "I",   "d,s,t",  MATCH_AND, MASK_AND, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"and",       "I",   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
++{"mv",        "C",   "d,CV",  MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
++{"mv",        "I",   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
++{"move",      "C",   "d,CV",  MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
++{"move",      "I",   "d,s",  MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
++{"andi",      "C",   "Cs,Cw,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
++{"andi",      "I",   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
++{"and",       "C",   "Cs,Cw,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
++{"and",       "C",   "Cs,Ct,Cw",  MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
++{"and",       "C",   "Cs,Cw,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
++{"and",       "I",   "d,s,t",  MATCH_AND, MASK_AND, match_opcode, 0 },
++{"and",       "I",   "d,s,j",  MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS },
 +{"beqz",      "C",   "Cs,Cp",  MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS },
-+{"beqz",      "I",   "s,p",  MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode,   INSN_ALIAS|RD_xs1 },
-+{"beq",       "I",   "s,t,p",  MATCH_BEQ, MASK_BEQ, match_opcode,   RD_xs1|RD_xs2 },
-+{"blez",      "I",   "t,p",  MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode,   INSN_ALIAS|RD_xs2 },
-+{"bgez",      "32C", "Cs,Cp",  MATCH_C_BGEZ, MASK_C_BGEZ, match_opcode, INSN_ALIAS },
-+{"bgez",      "I",   "s,p",  MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode,   INSN_ALIAS|RD_xs1 },
-+{"ble",       "I",   "t,s,p",  MATCH_BGE, MASK_BGE, match_opcode,   INSN_ALIAS|RD_xs1|RD_xs2 },
-+{"bleu",      "I",   "t,s,p",  MATCH_BGEU, MASK_BGEU, match_opcode,   INSN_ALIAS|RD_xs1|RD_xs2 },
-+{"bge",       "I",   "s,t,p",  MATCH_BGE, MASK_BGE, match_opcode,   RD_xs1|RD_xs2 },
-+{"bgeu",      "I",   "s,t,p",  MATCH_BGEU, MASK_BGEU, match_opcode,   RD_xs1|RD_xs2 },
-+{"bltz",      "32C", "Cs,Cp",  MATCH_C_BLTZ, MASK_C_BLTZ, match_opcode, INSN_ALIAS },
-+{"bltz",      "I",   "s,p",  MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode,   INSN_ALIAS|RD_xs1 },
-+{"bgtz",      "I",   "t,p",  MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode,   INSN_ALIAS|RD_xs2 },
-+{"blt",       "I",   "s,t,p",  MATCH_BLT, MASK_BLT, match_opcode,   RD_xs1|RD_xs2 },
-+{"bltu",      "I",   "s,t,p",  MATCH_BLTU, MASK_BLTU, match_opcode,   RD_xs1|RD_xs2 },
-+{"bgt",       "I",   "t,s,p",  MATCH_BLT, MASK_BLT, match_opcode,   INSN_ALIAS|RD_xs1|RD_xs2 },
-+{"bgtu",      "I",   "t,s,p",  MATCH_BLTU, MASK_BLTU, match_opcode,   INSN_ALIAS|RD_xs1|RD_xs2 },
++{"beqz",      "I",   "s,p",  MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS },
++{"beq",       "I",   "s,t,p",  MATCH_BEQ, MASK_BEQ, match_opcode, 0 },
++{"blez",      "I",   "t,p",  MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS },
++{"bgez",      "I",   "s,p",  MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS },
++{"ble",       "I",   "t,s,p",  MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS },
++{"bleu",      "I",   "t,s,p",  MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS },
++{"bge",       "I",   "s,t,p",  MATCH_BGE, MASK_BGE, match_opcode, 0 },
++{"bgeu",      "I",   "s,t,p",  MATCH_BGEU, MASK_BGEU, match_opcode, 0 },
++{"bltz",      "I",   "s,p",  MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS },
++{"bgtz",      "I",   "t,p",  MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS },
++{"blt",       "I",   "s,t,p",  MATCH_BLT, MASK_BLT, match_opcode, 0 },
++{"bltu",      "I",   "s,t,p",  MATCH_BLTU, MASK_BLTU, match_opcode, 0 },
++{"bgt",       "I",   "t,s,p",  MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS },
++{"bgtu",      "I",   "t,s,p",  MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS },
 +{"bnez",      "C",   "Cs,Cp",  MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS },
-+{"bnez",      "I",   "s,p",  MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode,   INSN_ALIAS|RD_xs1 },
-+{"bne",       "I",   "s,t,p",  MATCH_BNE, MASK_BNE, match_opcode,   RD_xs1|RD_xs2 },
++{"bnez",      "I",   "s,p",  MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS },
++{"bne",       "I",   "s,t,p",  MATCH_BNE, MASK_BNE, match_opcode, 0 },
 +{"addi",      "C",   "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS },
-+{"addi",      "C",   "CD,CU,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
++{"addi",      "C",   "d,CU,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
 +{"addi",      "C",   "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS },
-+{"addi",      "32C", "Ct,Cs,Ci",  MATCH_C_ADDIN, MASK_C_ADDIN, match_opcode, INSN_ALIAS },
-+{"addi",      "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode,  WR_xd|RD_xs1 },
-+{"add",       "C",   "CD,CU,CT",  MATCH_C_ADD, MASK_C_ADD, match_rd_nonzero, INSN_ALIAS },
-+{"add",       "C",   "CD,CT,CU",  MATCH_C_ADD, MASK_C_ADD, match_rd_nonzero, INSN_ALIAS },
-+{"add",       "C",   "CD,CU,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
++{"addi",      "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
++{"add",       "C",   "d,CU,CV",  MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
++{"add",       "C",   "d,CV,CU",  MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
++{"add",       "C",   "d,CU,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
 +{"add",       "C",   "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS },
-+{"add",       "C",   "Cd,Cs,Ct",  MATCH_C_ADD3, MASK_C_ADD3, match_opcode, INSN_ALIAS },
 +{"add",       "C",   "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS },
-+{"add",       "32C", "Ct,Cs,Ci",  MATCH_C_ADDIN, MASK_C_ADDIN, match_opcode, INSN_ALIAS },
-+{"add",       "I",   "d,s,t",  MATCH_ADD, MASK_ADD, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"add",       "I",   "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"add",       "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode,  INSN_ALIAS|WR_xd|RD_xs1 },
++{"add",       "I",   "d,s,t",  MATCH_ADD, MASK_ADD, match_opcode, 0 },
++{"add",       "I",   "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },
++{"add",       "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
 +{"la",        "I",   "d,A",  0,    (int) M_LA,  match_never, INSN_MACRO },
 +{"lla",       "I",   "d,A",  0,    (int) M_LLA,  match_never, INSN_MACRO },
 +{"la.tls.gd", "I",   "d,A",  0,    (int) M_LA_TLS_GD,  match_never, INSN_MACRO },
 +{"la.tls.ie", "I",   "d,A",  0,    (int) M_LA_TLS_IE,  match_never, INSN_MACRO },
-+{"neg",       "I",   "d,t",  MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode,   INSN_ALIAS|WR_xd|RD_xs2 }, /* sub 0 */
-+{"slli",      "C",   "CD,CU,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
-+{"slli",      "I",   "d,s,>",   MATCH_SLLI, MASK_SLLI, match_opcode,   WR_xd|RD_xs1 },
-+{"sll",       "C",   "CD,CU,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
-+{"sll",       "32C", "Cs,Cw,Ct",  MATCH_C_SLL, MASK_C_SLL, match_opcode, INSN_ALIAS },
-+{"sll",       "32C", "Ct,Cs,Cx",  MATCH_C_SLLR, MASK_C_SLLR, match_opcode, INSN_ALIAS },
-+{"sll",       "I",   "d,s,t",   MATCH_SLL, MASK_SLL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"sll",       "I",   "d,s,>",   MATCH_SLLI, MASK_SLLI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"srli",      "C",   "CD,CU,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
-+{"srli",      "I",   "d,s,>",   MATCH_SRLI, MASK_SRLI, match_opcode,   WR_xd|RD_xs1 },
-+{"srl",       "C",   "CD,CU,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
-+{"srl",       "32C", "Cs,Cw,Ct",  MATCH_C_SRL, MASK_C_SRL, match_opcode, INSN_ALIAS },
-+{"srl",       "32C", "Ct,Cs,Cx",  MATCH_C_SRLR, MASK_C_SRLR, match_opcode, INSN_ALIAS },
-+{"srl",       "I",   "d,s,t",   MATCH_SRL, MASK_SRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"srl",       "I",   "d,s,>",   MATCH_SRLI, MASK_SRLI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"srai",      "C",   "CD,CU,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
-+{"srai",      "I",   "d,s,>",   MATCH_SRAI, MASK_SRAI, match_opcode,   WR_xd|RD_xs1 },
-+{"sra",       "C",   "CD,CU,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
-+{"sra",       "32C", "Cs,Cw,Ct",  MATCH_C_SRA, MASK_C_SRA, match_opcode, INSN_ALIAS },
-+{"sra",       "I",   "d,s,t",   MATCH_SRA, MASK_SRA, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"sra",       "I",   "d,s,>",   MATCH_SRAI, MASK_SRAI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"sub",       "C",   "CD,CU,CT",  MATCH_C_SUB, MASK_C_SUB, match_rd_nonzero, INSN_ALIAS },
-+{"sub",       "C",   "Cd,Cs,Ct",  MATCH_C_SUB3, MASK_C_SUB3, match_opcode, INSN_ALIAS },
-+{"sub",       "I",   "d,s,t",  MATCH_SUB, MASK_SUB, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"lb",        "I",   "d,o(s)",  MATCH_LB, MASK_LB, match_opcode,   WR_xd|RD_xs1 },
++{"neg",       "I",   "d,t",  MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */
++{"slli",      "C",   "d,CU,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
++{"slli",      "I",   "d,s,>",   MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
++{"sll",       "C",   "d,CU,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
++{"sll",       "I",   "d,s,t",   MATCH_SLL, MASK_SLL, match_opcode, 0 },
++{"sll",       "I",   "d,s,>",   MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
++{"srli",      "C",   "Cs,Cw,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
++{"srli",      "I",   "d,s,>",   MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
++{"srl",       "C",   "Cs,Cw,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
++{"srl",       "I",   "d,s,t",   MATCH_SRL, MASK_SRL, match_opcode, 0 },
++{"srl",       "I",   "d,s,>",   MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
++{"srai",      "C",   "Cs,Cw,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
++{"srai",      "I",   "d,s,>",   MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
++{"sra",       "C",   "Cs,Cw,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
++{"sra",       "I",   "d,s,t",   MATCH_SRA, MASK_SRA, match_opcode, 0 },
++{"sra",       "I",   "d,s,>",   MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
++{"sub",       "C",   "Cs,Cw,Ct",  MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
++{"sub",       "I",   "d,s,t",  MATCH_SUB, MASK_SUB, match_opcode, 0 },
++{"lb",        "I",   "d,o(s)",  MATCH_LB, MASK_LB, match_opcode, 0 },
 +{"lb",        "I",   "d,A",  0, (int) M_LB, match_never, INSN_MACRO },
-+{"lbu",       "I",   "d,o(s)",  MATCH_LBU, MASK_LBU, match_opcode,   WR_xd|RD_xs1 },
++{"lbu",       "I",   "d,o(s)",  MATCH_LBU, MASK_LBU, match_opcode, 0 },
 +{"lbu",       "I",   "d,A",  0, (int) M_LBU, match_never, INSN_MACRO },
-+{"lh",        "I",   "d,o(s)",  MATCH_LH, MASK_LH, match_opcode,   WR_xd|RD_xs1 },
++{"lh",        "I",   "d,o(s)",  MATCH_LH, MASK_LH, match_opcode, 0 },
 +{"lh",        "I",   "d,A",  0, (int) M_LH, match_never, INSN_MACRO },
-+{"lhu",       "I",   "d,o(s)",  MATCH_LHU, MASK_LHU, match_opcode,   WR_xd|RD_xs1 },
++{"lhu",       "I",   "d,o(s)",  MATCH_LHU, MASK_LHU, match_opcode, 0 },
 +{"lhu",       "I",   "d,A",  0, (int) M_LHU, match_never, INSN_MACRO },
-+{"lw",        "C",   "CD,Cm(Cc)",  MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS },
++{"lw",        "C",   "d,Cm(Cc)",  MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS },
 +{"lw",        "C",   "Ct,Ck(Cs)",  MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS },
-+{"lw",        "I",   "d,o(s)",  MATCH_LW, MASK_LW, match_opcode,   WR_xd|RD_xs1 },
++{"lw",        "I",   "d,o(s)",  MATCH_LW, MASK_LW, match_opcode, 0 },
 +{"lw",        "I",   "d,A",  0, (int) M_LW, match_never, INSN_MACRO },
-+{"not",       "I",   "d,s",  MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"ori",       "32C", "Ct,Cs,Ci",  MATCH_C_ORIN, MASK_C_ORIN, match_opcode, INSN_ALIAS },
-+{"ori",       "I",   "d,s,j",  MATCH_ORI, MASK_ORI, match_opcode,   WR_xd|RD_xs1 },
-+{"or",        "C",   "Cd,Cs,Ct",  MATCH_C_OR3, MASK_C_OR3, match_opcode, INSN_ALIAS },
-+{"or",        "32C", "Ct,Cs,Ci",  MATCH_C_ORIN, MASK_C_ORIN, match_opcode, INSN_ALIAS },
-+{"or",        "I",   "d,s,t",  MATCH_OR, MASK_OR, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"or",        "I",   "d,s,j",  MATCH_ORI, MASK_ORI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"auipc",     "I",   "d,u",  MATCH_AUIPC, MASK_AUIPC, match_opcode,  WR_xd },
-+{"seqz",      "I",   "d,s",  MATCH_SLTIU | ENCODE_ITYPE_IMM(1), MASK_SLTIU | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"snez",      "I",   "d,t",  MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode,   INSN_ALIAS|WR_xd|RD_xs2 },
-+{"sltz",      "I",   "d,s",  MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"sgtz",      "I",   "d,t",  MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode,   INSN_ALIAS|WR_xd|RD_xs2 },
-+{"slti",      "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"slt",       "32C", "Cs,Cw,Ct",  MATCH_C_SLT, MASK_C_SLT, match_opcode, INSN_ALIAS },
-+{"slt",       "32C", "Ct,Cs,Cx",  MATCH_C_SLTR, MASK_C_SLTR, match_opcode, INSN_ALIAS },
-+{"slt",       "I",   "d,s,t",  MATCH_SLT, MASK_SLT, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"slt",       "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode,   WR_xd|RD_xs1 },
-+{"sltiu",     "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode,   WR_xd|RD_xs1 },
-+{"sltu",      "32C", "Cs,Cw,Ct",  MATCH_C_SLTU, MASK_C_SLTU, match_opcode, INSN_ALIAS },
-+{"sltu",      "32C", "Ct,Cs,Cx",  MATCH_C_SLTUR, MASK_C_SLTUR, match_opcode, INSN_ALIAS },
-+{"sltu",      "I",   "d,s,t",  MATCH_SLTU, MASK_SLTU, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"sltu",      "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"sgt",       "I",   "d,t,s",  MATCH_SLT, MASK_SLT, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1|RD_xs2 },
-+{"sgtu",      "I",   "d,t,s",  MATCH_SLTU, MASK_SLTU, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1|RD_xs2 },
-+{"sb",        "I",   "t,q(s)",  MATCH_SB, MASK_SB, match_opcode,   RD_xs1|RD_xs2 },
-+{"sb",        "I",   "t,A,s",  0, (int) M_SB, match_never,  INSN_MACRO },
-+{"sh",        "I",   "t,q(s)",  MATCH_SH, MASK_SH, match_opcode,   RD_xs1|RD_xs2 },
-+{"sh",        "I",   "t,A,s",  0, (int) M_SH, match_never,  INSN_MACRO },
++{"not",       "I",   "d,s",  MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS },
++{"ori",       "I",   "d,s,j",  MATCH_ORI, MASK_ORI, match_opcode, 0 },
++{"or",       "C",   "Cs,Cw,Ct",  MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
++{"or",       "C",   "Cs,Ct,Cw",  MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
++{"or",        "I",   "d,s,t",  MATCH_OR, MASK_OR, match_opcode, 0 },
++{"or",        "I",   "d,s,j",  MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
++{"auipc",     "I",   "d,u",  MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
++{"seqz",      "I",   "d,s",  MATCH_SLTIU | ENCODE_ITYPE_IMM(1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
++{"snez",      "I",   "d,t",  MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
++{"sltz",      "I",   "d,s",  MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
++{"sgtz",      "I",   "d,t",  MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },
++{"slti",      "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
++{"slt",       "I",   "d,s,t",  MATCH_SLT, MASK_SLT, match_opcode, 0 },
++{"slt",       "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
++{"sltiu",     "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 },
++{"sltu",      "I",   "d,s,t",  MATCH_SLTU, MASK_SLTU, match_opcode, 0 },
++{"sltu",      "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS },
++{"sgt",       "I",   "d,t,s",  MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS },
++{"sgtu",      "I",   "d,t,s",  MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS },
++{"sb",        "I",   "t,q(s)",  MATCH_SB, MASK_SB, match_opcode, 0 },
++{"sb",        "I",   "t,A,s",  0, (int) M_SB, match_never, INSN_MACRO },
++{"sh",        "I",   "t,q(s)",  MATCH_SH, MASK_SH, match_opcode, 0 },
++{"sh",        "I",   "t,A,s",  0, (int) M_SH, match_never, INSN_MACRO },
 +{"sw",        "C",   "CV,CM(Cc)",  MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS },
 +{"sw",        "C",   "Ct,Ck(Cs)",  MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS },
-+{"sw",        "I",   "t,q(s)",  MATCH_SW, MASK_SW, match_opcode,   RD_xs1|RD_xs2 },
-+{"sw",        "I",   "t,A,s",  0, (int) M_SW, match_never,  INSN_MACRO },
-+{"fence",     "I",   "",  MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode,   INSN_ALIAS },
-+{"fence",     "I",   "P,Q",  MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode,   0 },
-+{"fence.i",   "I",   "",  MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode,   0 },
-+{"rdcycle",   "I",   "d",  MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode,  WR_xd },
-+{"rdinstret", "I",   "d",  MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode,  WR_xd },
-+{"rdtime",    "I",   "d",  MATCH_RDTIME, MASK_RDTIME, match_opcode,  WR_xd },
-+{"rdcycleh",  "32I", "d",  MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode,  WR_xd },
-+{"rdinstreth","32I", "d",  MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode,  WR_xd },
-+{"rdtimeh",   "32I", "d",  MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode,  WR_xd },
-+{"ecall",     "I",   "",    MATCH_SCALL, MASK_SCALL, match_opcode,   0 },
-+{"scall",     "I",   "",    MATCH_SCALL, MASK_SCALL, match_opcode,   0 },
-+{"xori",      "32C", "Ct,Cs,Ci",  MATCH_C_XORIN, MASK_C_XORIN, match_opcode, INSN_ALIAS },
-+{"xori",      "I",   "d,s,j",  MATCH_XORI, MASK_XORI, match_opcode,   WR_xd|RD_xs1 },
-+{"xor",       "32C", "Cs,Cw,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
-+{"xor",       "32C", "Cs,Ct,Cw",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
-+{"xor",       "32C", "Ct,Cs,Ci",  MATCH_C_XORIN, MASK_C_XORIN, match_opcode, INSN_ALIAS },
-+{"xor",       "I",   "d,s,t",  MATCH_XOR, MASK_XOR, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"xor",       "I",   "d,s,j",  MATCH_XORI, MASK_XORI, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"lwu",       "64I", "d,o(s)",  MATCH_LWU, MASK_LWU, match_opcode,   WR_xd|RD_xs1 },
++{"sw",        "I",   "t,q(s)",  MATCH_SW, MASK_SW, match_opcode, 0 },
++{"sw",        "I",   "t,A,s",  0, (int) M_SW, match_never, INSN_MACRO },
++{"fence",     "I",   "",  MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
++{"fence",     "I",   "P,Q",  MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
++{"fence.i",   "I",   "",  MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
++{"rdcycle",   "I",   "d",  MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, 0 },
++{"rdinstret", "I",   "d",  MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, 0 },
++{"rdtime",    "I",   "d",  MATCH_RDTIME, MASK_RDTIME, match_opcode, 0 },
++{"rdcycleh",  "32I", "d",  MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, 0 },
++{"rdinstreth","32I", "d",  MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, 0 },
++{"rdtimeh",   "32I", "d",  MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, 0 },
++{"ecall",     "I",   "",    MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
++{"scall",     "I",   "",    MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
++{"xori",      "I",   "d,s,j",  MATCH_XORI, MASK_XORI, match_opcode, 0 },
++{"xor",       "C",   "Cs,Cw,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
++{"xor",       "C",   "Cs,Ct,Cw",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
++{"xor",       "I",   "d,s,t",  MATCH_XOR, MASK_XOR, match_opcode, 0 },
++{"xor",       "I",   "d,s,j",  MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
++{"lwu",       "64I", "d,o(s)",  MATCH_LWU, MASK_LWU, match_opcode, 0 },
 +{"lwu",       "64I", "d,A",  0, (int) M_LWU, match_never, INSN_MACRO },
-+{"ld",        "64C", "CD,Cn(Cc)",  MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS },
++{"ld",        "64C", "d,Cn(Cc)",  MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS },
 +{"ld",        "64C", "Ct,Cl(Cs)",  MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS },
-+{"ld",        "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode,  WR_xd|RD_xs1 },
++{"ld",        "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, 0 },
 +{"ld",        "64I", "d,A",  0, (int) M_LD, match_never, INSN_MACRO },
 +{"sd",        "64C", "CV,CN(Cc)",  MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS },
 +{"sd",        "64C", "Ct,Cl(Cs)",  MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS },
-+{"sd",        "64I", "t,q(s)",  MATCH_SD, MASK_SD, match_opcode,   RD_xs1|RD_xs2 },
-+{"sd",        "64I", "t,A,s",  0, (int) M_SD, match_never,  INSN_MACRO },
-+{"sext.w",    "64C", "CD,CU",  MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
-+{"sext.w",    "64I", "d,s",  MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"addiw",     "64C", "CD,CU,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
-+{"addiw",     "64I", "d,s,j",  MATCH_ADDIW, MASK_ADDIW, match_opcode,   WR_xd|RD_xs1 },
-+{"addw",      "64C", "CD,CU,CT",  MATCH_C_ADDW, MASK_C_ADDW, match_rd_nonzero, INSN_ALIAS },
-+{"addw",      "64C", "CD,CT,CU",  MATCH_C_ADDW, MASK_C_ADDW, match_rd_nonzero, INSN_ALIAS },
-+{"addw",      "64C", "CD,CU,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
-+{"addw",      "64I", "d,s,t",  MATCH_ADDW, MASK_ADDW, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"addw",      "64I", "d,s,j",  MATCH_ADDIW, MASK_ADDIW, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"negw",      "64I", "d,t",  MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode,   INSN_ALIAS|WR_xd|RD_xs2 }, /* sub 0 */
-+{"slliw",     "64C",   "CD,CU,C<",  MATCH_C_SLLIW, MASK_C_SLLIW, match_rd_nonzero, INSN_ALIAS },
-+{"slliw",     "64I", "d,s,<",   MATCH_SLLIW, MASK_SLLIW, match_opcode,   WR_xd|RD_xs1 },
-+{"sllw",      "64C",   "CD,CU,C<",  MATCH_C_SLLIW, MASK_C_SLLIW, match_rd_nonzero, INSN_ALIAS },
-+{"sllw",      "64I", "d,s,t",   MATCH_SLLW, MASK_SLLW, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"sllw",      "64I", "d,s,<",   MATCH_SLLIW, MASK_SLLIW, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"srliw",     "64I", "d,s,<",   MATCH_SRLIW, MASK_SRLIW, match_opcode,   WR_xd|RD_xs1 },
-+{"srlw",      "64I", "d,s,t",   MATCH_SRLW, MASK_SRLW, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"srlw",      "64I", "d,s,<",   MATCH_SRLIW, MASK_SRLIW, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"sraiw",     "64I", "d,s,<",   MATCH_SRAIW, MASK_SRAIW, match_opcode,   WR_xd|RD_xs1 },
-+{"sraw",      "64I", "d,s,t",   MATCH_SRAW, MASK_SRAW, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"sraw",      "64I", "d,s,<",   MATCH_SRAIW, MASK_SRAIW, match_opcode,   INSN_ALIAS|WR_xd|RD_xs1 },
-+{"subw",      "64I", "d,s,t",  MATCH_SUBW, MASK_SUBW, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
++{"sd",        "64I", "t,q(s)",  MATCH_SD, MASK_SD, match_opcode, 0 },
++{"sd",        "64I", "t,A,s",  0, (int) M_SD, match_never, INSN_MACRO },
++{"sext.w",    "64C", "d,CU",  MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
++{"sext.w",    "64I", "d,s",  MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS },
++{"addiw",     "64C", "d,CU,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
++{"addiw",     "64I", "d,s,j",  MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 },
++{"addw",      "64C", "Cs,Cw,Ct",  MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
++{"addw",      "64C", "Cs,Ct,Cw",  MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS },
++{"addw",      "64C", "d,CU,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
++{"addw",      "64I", "d,s,t",  MATCH_ADDW, MASK_ADDW, match_opcode, 0 },
++{"addw",      "64I", "d,s,j",  MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS },
++{"negw",      "64I", "d,t",  MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */
++{"slliw",     "64I", "d,s,<",   MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 },
++{"sllw",      "64I", "d,s,t",   MATCH_SLLW, MASK_SLLW, match_opcode, 0 },
++{"sllw",      "64I", "d,s,<",   MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS },
++{"srliw",     "64I", "d,s,<",   MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 },
++{"srlw",      "64I", "d,s,t",   MATCH_SRLW, MASK_SRLW, match_opcode, 0 },
++{"srlw",      "64I", "d,s,<",   MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS },
++{"sraiw",     "64I", "d,s,<",   MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 },
++{"sraw",      "64I", "d,s,t",   MATCH_SRAW, MASK_SRAW, match_opcode, 0 },
++{"sraw",      "64I", "d,s,<",   MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS },
++{"subw",      "64C", "Cs,Cw,Ct",  MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS },
++{"subw",      "64I", "d,s,t",  MATCH_SUBW, MASK_SUBW, match_opcode, 0 },
++
++/* Atomic memory operation instruction subset */
++{"lr.w",         "A",   "d,0(s)",    MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, 0 },
++{"sc.w",         "A",   "d,t,0(s)",  MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, 0 },
++{"amoadd.w",     "A",   "d,t,0(s)",  MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 },
++{"amoswap.w",    "A",   "d,t,0(s)",  MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 },
++{"amoand.w",     "A",   "d,t,0(s)",  MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 },
++{"amoor.w",      "A",   "d,t,0(s)",  MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 },
++{"amoxor.w",     "A",   "d,t,0(s)",  MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 },
++{"amomax.w",     "A",   "d,t,0(s)",  MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 },
++{"amomaxu.w",    "A",   "d,t,0(s)",  MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 },
++{"amomin.w",     "A",   "d,t,0(s)",  MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 },
++{"amominu.w",    "A",   "d,t,0(s)",  MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 },
++{"lr.w.aq",      "A",   "d,0(s)",    MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, 0 },
++{"sc.w.aq",      "A",   "d,t,0(s)",  MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, 0 },
++{"amoadd.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 },
++{"amoswap.w.aq", "A",   "d,t,0(s)",  MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 },
++{"amoand.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 },
++{"amoor.w.aq",   "A",   "d,t,0(s)",  MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 },
++{"amoxor.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 },
++{"amomax.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 },
++{"amomaxu.w.aq", "A",   "d,t,0(s)",  MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 },
++{"amomin.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 },
++{"amominu.w.aq", "A",   "d,t,0(s)",  MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 },
++{"lr.w.rl",      "A",   "d,0(s)",    MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, 0 },
++{"sc.w.rl",      "A",   "d,t,0(s)",  MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, 0 },
++{"amoadd.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 },
++{"amoswap.w.rl", "A",   "d,t,0(s)",  MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 },
++{"amoand.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 },
++{"amoor.w.rl",   "A",   "d,t,0(s)",  MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 },
++{"amoxor.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 },
++{"amomax.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 },
++{"amomaxu.w.rl", "A",   "d,t,0(s)",  MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 },
++{"amomin.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 },
++{"amominu.w.rl", "A",   "d,t,0(s)",  MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 },
++{"lr.w.sc",      "A",   "d,0(s)",    MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, 0 },
++{"sc.w.sc",      "A",   "d,t,0(s)",  MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, 0 },
++{"amoadd.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 },
++{"amoswap.w.sc", "A",   "d,t,0(s)",  MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 },
++{"amoand.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 },
++{"amoor.w.sc",   "A",   "d,t,0(s)",  MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 },
++{"amoxor.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 },
++{"amomax.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 },
++{"amomaxu.w.sc", "A",   "d,t,0(s)",  MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 },
++{"amomin.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 },
++{"amominu.w.sc", "A",   "d,t,0(s)",  MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 },
++{"lr.d",         "64A", "d,0(s)",    MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, 0 },
++{"sc.d",         "64A", "d,t,0(s)",  MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, 0 },
++{"amoadd.d",     "64A", "d,t,0(s)",  MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 },
++{"amoswap.d",    "64A", "d,t,0(s)",  MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 },
++{"amoand.d",     "64A", "d,t,0(s)",  MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 },
++{"amoor.d",      "64A", "d,t,0(s)",  MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 },
++{"amoxor.d",     "64A", "d,t,0(s)",  MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 },
++{"amomax.d",     "64A", "d,t,0(s)",  MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 },
++{"amomaxu.d",    "64A", "d,t,0(s)",  MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 },
++{"amomin.d",     "64A", "d,t,0(s)",  MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 },
++{"amominu.d",    "64A", "d,t,0(s)",  MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 },
++{"lr.d.aq",      "64A", "d,0(s)",    MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, 0 },
++{"sc.d.aq",      "64A", "d,t,0(s)",  MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, 0 },
++{"amoadd.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 },
++{"amoswap.d.aq", "64A", "d,t,0(s)",  MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 },
++{"amoand.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 },
++{"amoor.d.aq",   "64A", "d,t,0(s)",  MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 },
++{"amoxor.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 },
++{"amomax.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 },
++{"amomaxu.d.aq", "64A", "d,t,0(s)",  MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 },
++{"amomin.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 },
++{"amominu.d.aq", "64A", "d,t,0(s)",  MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 },
++{"lr.d.rl",      "64A", "d,0(s)",    MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, 0 },
++{"sc.d.rl",      "64A", "d,t,0(s)",  MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, 0 },
++{"amoadd.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 },
++{"amoswap.d.rl", "64A", "d,t,0(s)",  MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 },
++{"amoand.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 },
++{"amoor.d.rl",   "64A", "d,t,0(s)",  MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 },
++{"amoxor.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 },
++{"amomax.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 },
++{"amomaxu.d.rl", "64A", "d,t,0(s)",  MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 },
++{"amomin.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 },
++{"amominu.d.rl", "64A", "d,t,0(s)",  MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 },
++{"lr.d.sc",      "64A", "d,0(s)",    MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, 0 },
++{"sc.d.sc",      "64A", "d,t,0(s)",  MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, 0 },
++{"amoadd.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 },
++{"amoswap.d.sc", "64A", "d,t,0(s)",  MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 },
++{"amoand.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 },
++{"amoor.d.sc",   "64A", "d,t,0(s)",  MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 },
++{"amoxor.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 },
++{"amomax.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 },
++{"amomaxu.d.sc", "64A", "d,t,0(s)",  MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 },
++{"amomin.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 },
++{"amominu.d.sc", "64A", "d,t,0(s)",  MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 },
++
++/* Multiply/Divide instruction subset */
++{"mul",       "M",   "d,s,t",  MATCH_MUL, MASK_MUL, match_opcode, 0 },
++{"mulh",      "M",   "d,s,t",  MATCH_MULH, MASK_MULH, match_opcode, 0 },
++{"mulhu",     "M",   "d,s,t",  MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
++{"mulhsu",    "M",   "d,s,t",  MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
++{"div",       "M",   "d,s,t",  MATCH_DIV, MASK_DIV, match_opcode, 0 },
++{"divu",      "M",   "d,s,t",  MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
++{"rem",       "M",   "d,s,t",  MATCH_REM, MASK_REM, match_opcode, 0 },
++{"remu",      "M",   "d,s,t",  MATCH_REMU, MASK_REMU, match_opcode, 0 },
++{"mulw",      "64M", "d,s,t",  MATCH_MULW, MASK_MULW, match_opcode, 0 },
++{"divw",      "64M", "d,s,t",  MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
++{"divuw",     "64M", "d,s,t",  MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
++{"remw",      "64M", "d,s,t",  MATCH_REMW, MASK_REMW, match_opcode, 0 },
++{"remuw",     "64M", "d,s,t",  MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
++
++/* Single-precision floating-point instruction subset */
++{"frsr",      "F",   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
++{"fssr",      "F",   "s",  MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
++{"fssr",      "F",   "d,s",  MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
++{"frcsr",     "F",   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
++{"fscsr",     "F",   "s",  MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
++{"fscsr",     "F",   "d,s",  MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
++{"frrm",      "F",   "d",  MATCH_FRRM, MASK_FRRM, match_opcode, 0 },
++{"fsrm",      "F",   "s",  MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 },
++{"fsrm",      "F",   "d,s",  MATCH_FSRM, MASK_FSRM, match_opcode, 0 },
++{"frflags",   "F",   "d",  MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 },
++{"fsflags",   "F",   "s",  MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 },
++{"fsflags",   "F",   "d,s",  MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 },
++{"flw",       "32C", "D,Cm(Cc)",  MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS },
++{"flw",       "32C", "CD,Ck(Cs)",  MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS },
++{"flw",       "F",   "D,o(s)",  MATCH_FLW, MASK_FLW, match_opcode, 0 },
++{"flw",       "F",   "D,A,s",  0, (int) M_FLW, match_never, INSN_MACRO },
++{"fsw",       "32C", "CT,CM(Cc)",  MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS },
++{"fsw",       "32C", "CD,Ck(Cs)",  MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS },
++{"fsw",       "F",   "T,q(s)",  MATCH_FSW, MASK_FSW, match_opcode, 0 },
++{"fsw",       "F",   "T,A,s",  0, (int) M_FSW, match_never, INSN_MACRO },
++{"fmv.x.s",   "F",   "d,S",  MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
++{"fmv.s.x",   "F",   "D,s",  MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
++{"fmv.s",     "F",   "D,U",  MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
++{"fneg.s",    "F",   "D,U",  MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
++{"fabs.s",    "F",   "D,U",  MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
++{"fsgnj.s",   "F",   "D,S,T",  MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
++{"fsgnjn.s",  "F",   "D,S,T",  MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
++{"fsgnjx.s",  "F",   "D,S,T",  MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
++{"fadd.s",    "F",   "D,S,T",  MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 },
++{"fadd.s",    "F",   "D,S,T,m",  MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
++{"fsub.s",    "F",   "D,S,T",  MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 },
++{"fsub.s",    "F",   "D,S,T,m",  MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
++{"fmul.s",    "F",   "D,S,T",  MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 },
++{"fmul.s",    "F",   "D,S,T,m",  MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
++{"fdiv.s",    "F",   "D,S,T",  MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 },
++{"fdiv.s",    "F",   "D,S,T,m",  MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
++{"fsqrt.s",   "F",   "D,S",  MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 },
++{"fsqrt.s",   "F",   "D,S,m",  MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
++{"fmin.s",    "F",   "D,S,T",  MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
++{"fmax.s",    "F",   "D,S,T",  MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
++{"fmadd.s",   "F",   "D,S,T,R",  MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 },
++{"fmadd.s",   "F",   "D,S,T,R,m",  MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
++{"fnmadd.s",  "F",   "D,S,T,R",  MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 },
++{"fnmadd.s",  "F",   "D,S,T,R,m",  MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
++{"fmsub.s",   "F",   "D,S,T,R",  MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 },
++{"fmsub.s",   "F",   "D,S,T,R,m",  MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
++{"fnmsub.s",  "F",   "D,S,T,R",  MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 },
++{"fnmsub.s",  "F",   "D,S,T,R,m",  MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
++{"fcvt.w.s",  "F",   "d,S",  MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 },
++{"fcvt.w.s",  "F",   "d,S,m",  MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
++{"fcvt.wu.s", "F",   "d,S",  MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 },
++{"fcvt.wu.s", "F",   "d,S,m",  MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
++{"fcvt.s.w",  "F",   "D,s",  MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 },
++{"fcvt.s.w",  "F",   "D,s,m",  MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
++{"fcvt.s.wu", "F",   "D,s",  MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 },
++{"fcvt.s.wu", "F",   "D,s,m",  MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
++{"fclass.s",  "F",   "d,S",  MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
++{"feq.s",     "F",   "d,S,T",    MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
++{"flt.s",     "F",   "d,S,T",    MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
++{"fle.s",     "F",   "d,S,T",    MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
++{"fgt.s",     "F",   "d,T,S",    MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
++{"fge.s",     "F",   "d,T,S",    MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
++{"fcvt.l.s",  "64F", "d,S",  MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 },
++{"fcvt.l.s",  "64F", "d,S,m",  MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
++{"fcvt.lu.s", "64F", "d,S",  MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 },
++{"fcvt.lu.s", "64F", "d,S,m",  MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
++{"fcvt.s.l",  "64F", "D,s",  MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
++{"fcvt.s.l",  "64F", "D,s,m",  MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
++{"fcvt.s.lu", "64F", "D,s",  MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
++{"fcvt.s.lu", "64F", "D,s,m",  MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
++
++/* Double-precision floating-point instruction subset */
++{"fld",       "C",   "D,Cn(Cc)",  MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS },
++{"fld",       "C",   "CD,Cl(Cs)",  MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS },
++{"fld",       "D",   "D,o(s)",  MATCH_FLD, MASK_FLD, match_opcode, 0 },
++{"fld",       "D",   "D,A,s",  0, (int) M_FLD, match_never, INSN_MACRO },
++{"fsd",       "C",   "CT,CN(Cc)",  MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS },
++{"fsd",       "C",   "CD,Cl(Cs)",  MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS },
++{"fsd",       "D",   "T,q(s)",  MATCH_FSD, MASK_FSD, match_opcode, 0 },
++{"fsd",       "D",   "T,A,s",  0, (int) M_FSD, match_never, INSN_MACRO },
++{"fmv.d",     "D",   "D,U",  MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
++{"fneg.d",    "D",   "D,U",  MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
++{"fabs.d",    "D",   "D,U",  MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
++{"fsgnj.d",   "D",   "D,S,T",  MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
++{"fsgnjn.d",  "D",   "D,S,T",  MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
++{"fsgnjx.d",  "D",   "D,S,T",  MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
++{"fadd.d",    "D",   "D,S,T",  MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 },
++{"fadd.d",    "D",   "D,S,T,m",  MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
++{"fsub.d",    "D",   "D,S,T",  MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 },
++{"fsub.d",    "D",   "D,S,T,m",  MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
++{"fmul.d",    "D",   "D,S,T",  MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 },
++{"fmul.d",    "D",   "D,S,T,m",  MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
++{"fdiv.d",    "D",   "D,S,T",  MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 },
++{"fdiv.d",    "D",   "D,S,T,m",  MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
++{"fsqrt.d",   "D",   "D,S",  MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 },
++{"fsqrt.d",   "D",   "D,S,m",  MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
++{"fmin.d",    "D",   "D,S,T",  MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
++{"fmax.d",    "D",   "D,S,T",  MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
++{"fmadd.d",   "D",   "D,S,T,R",  MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 },
++{"fmadd.d",   "D",   "D,S,T,R,m",  MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
++{"fnmadd.d",  "D",   "D,S,T,R",  MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 },
++{"fnmadd.d",  "D",   "D,S,T,R,m",  MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
++{"fmsub.d",   "D",   "D,S,T,R",  MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 },
++{"fmsub.d",   "D",   "D,S,T,R,m",  MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
++{"fnmsub.d",  "D",   "D,S,T,R",  MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 },
++{"fnmsub.d",  "D",   "D,S,T,R,m",  MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
++{"fcvt.w.d",  "D",   "d,S",  MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 },
++{"fcvt.w.d",  "D",   "d,S,m",  MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
++{"fcvt.wu.d", "D",   "d,S",  MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 },
++{"fcvt.wu.d", "D",   "d,S,m",  MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
++{"fcvt.d.w",  "D",   "D,s",  MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 },
++{"fcvt.d.wu", "D",   "D,s",  MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 },
++{"fcvt.d.s",  "D",   "D,S",  MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 },
++{"fcvt.s.d",  "D",   "D,S",  MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 },
++{"fcvt.s.d",  "D",   "D,S,m",  MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
++{"fclass.d",  "D",   "d,S",  MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
++{"feq.d",     "D",   "d,S,T",    MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
++{"flt.d",     "D",   "d,S,T",    MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
++{"fle.d",     "D",   "d,S,T",    MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
++{"fgt.d",     "D",   "d,T,S",    MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
++{"fge.d",     "D",   "d,T,S",    MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
++{"fmv.x.d",   "64D", "d,S",  MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
++{"fmv.d.x",   "64D", "D,s",  MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
++{"fcvt.l.d",  "64D", "d,S",  MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 },
++{"fcvt.l.d",  "64D", "d,S,m",  MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
++{"fcvt.lu.d", "64D", "d,S",  MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 },
++{"fcvt.lu.d", "64D", "d,S,m",  MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
++{"fcvt.d.l",  "64D", "D,s",  MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
++{"fcvt.d.l",  "64D", "D,s,m",  MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
++{"fcvt.d.lu", "64D", "D,s",  MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
++{"fcvt.d.lu", "64D", "D,s,m",  MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
 +
 +/* Compressed instructions */
 +{"c.ebreak",  "C",   "",  MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
-+{"c.jr",      "C",   "CD",  MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 },
-+{"c.jalr",    "C",   "CD",  MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 },
++{"c.jr",      "C",   "d",  MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 },
++{"c.jalr",    "C",   "d",  MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 },
 +{"c.j",       "C",   "Ca",  MATCH_C_J, MASK_C_J, match_opcode, 0 },
-+{"c.jal",     "C",   "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 },
++{"c.jal",     "32C", "Ca",  MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 },
 +{"c.beqz",    "C",   "Cs,Cp",  MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, 0 },
 +{"c.bnez",    "C",   "Cs,Cp",  MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, 0 },
-+{"c.lwsp",    "C",   "CD,Cm(Cc)",  MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 },
++{"c.lwsp",    "C",   "d,Cm(Cc)",  MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 },
 +{"c.lw",      "C",   "Ct,Ck(Cs)",  MATCH_C_LW, MASK_C_LW, match_opcode, 0 },
 +{"c.swsp",    "C",   "CV,CM(Cc)",  MATCH_C_SWSP, MASK_C_SWSP, match_opcode, 0 },
 +{"c.sw",      "C",   "Ct,Ck(Cs)",  MATCH_C_SW, MASK_C_SW, match_opcode, 0 },
-+{"c.nop",     "C",   "",  MATCH_C_ADDI16SP, 0xffff, match_opcode, 0 },
-+{"c.mv",      "C",   "CD,CV",  MATCH_C_MV, MASK_C_MV, match_rd_nonzero, 0 },
-+{"c.lui",     "C",   "CD,Cu",  MATCH_C_LUI, MASK_C_LUI, match_rd_nonzero, 0 },
-+{"c.li",      "C",   "CD,Cj",  MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
++{"c.nop",     "C",   "",  MATCH_C_ADDI, 0xffff, match_opcode, 0 },
++{"c.mv",      "C",   "d,CV",  MATCH_C_MV, MASK_C_MV, match_c_add, 0 },
++{"c.lui",     "C",   "d,Cu",  MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 },
++{"c.li",      "C",   "d,Cj",  MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
 +{"c.addi4spn","C",   "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
 +{"c.addi16sp","C",   "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
-+{"c.addi",    "C",   "CD,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 },
-+{"c.add",     "C",   "CD,CT",  MATCH_C_ADD, MASK_C_ADD, match_rd_nonzero, 0 },
-+{"c.sub",     "C",   "CD,CT",  MATCH_C_SUB, MASK_C_SUB, match_rd_nonzero, 0 },
-+{"c.add3",    "C",   "Cd,Cs,Ct",  MATCH_C_ADD3, MASK_C_ADD3, match_opcode, 0 },
-+{"c.sub3",    "C",   "Cd,Cs,Ct",  MATCH_C_SUB3, MASK_C_SUB3, match_opcode, 0 },
-+{"c.and3",    "C",   "Cd,Cs,Ct",  MATCH_C_AND3, MASK_C_AND3, match_opcode, 0 },
-+{"c.or3",     "C",   "Cd,Cs,Ct",  MATCH_C_OR3, MASK_C_OR3, match_opcode, 0 },
-+{"c.slli",    "C",   "CD,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 },
-+{"c.srli",    "C",   "CD,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, 0 },
-+{"c.srai",    "C",   "CD,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, 0 },
-+{"c.slliw",   "64C", "CD,CU,C<",  MATCH_C_SLLIW, MASK_C_SLLIW, match_rd_nonzero, 0 },
-+{"c.addiw",   "64C", "CD,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
-+{"c.addw",    "64C", "CD,CT",  MATCH_C_ADDW, MASK_C_ADDW, match_rd_nonzero, 0 },
-+{"c.ldsp",    "64C", "CD,Cn(Cc)",  MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 },
++{"c.addi",    "C",   "d,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 },
++{"c.add",     "C",   "d,CV",  MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 },
++{"c.sub",     "C",   "Cs,Ct",  MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 },
++{"c.and",     "C",   "Cs,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, 0 },
++{"c.or",      "C",   "Cs,Ct",  MATCH_C_OR, MASK_C_OR, match_opcode, 0 },
++{"c.xor",     "C",   "Cs,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 },
++{"c.slli",    "C",   "d,C>",  MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 },
++{"c.srli",    "C",   "Cs,C>",  MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 },
++{"c.srai",    "C",   "Cs,C>",  MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 },
++{"c.andi",    "C",   "Cs,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
++{"c.addiw",   "64C", "d,Cj",  MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
++{"c.addw",    "64C", "Cs,Ct",  MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 },
++{"c.subw",    "64C", "Cs,Ct",  MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 },
++{"c.ldsp",    "64C", "d,Cn(Cc)",  MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 },
 +{"c.ld",      "64C", "Ct,Cl(Cs)",  MATCH_C_LD, MASK_C_LD, match_opcode, 0 },
 +{"c.sdsp",    "64C", "CV,CN(Cc)",  MATCH_C_SDSP, MASK_C_SDSP, match_opcode, 0 },
 +{"c.sd",      "64C", "Ct,Cl(Cs)",  MATCH_C_SD, MASK_C_SD, match_opcode, 0 },
-+{"c.xor",     "32C", "Cs,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 },
-+{"c.sra",     "32C", "Cs,Ct",  MATCH_C_SRA, MASK_C_SRA, match_opcode, 0 },
-+{"c.sll",     "32C", "Cs,Ct",  MATCH_C_SLL, MASK_C_SLL, match_opcode, 0 },
-+{"c.srl",     "32C", "Cs,Ct",  MATCH_C_SRL, MASK_C_SRL, match_opcode, 0 },
-+{"c.slt",     "32C", "Cs,Ct",  MATCH_C_SLT, MASK_C_SLT, match_opcode, 0 },
-+{"c.sltu",    "32C", "Cs,Ct",  MATCH_C_SLTU, MASK_C_SLTU, match_opcode, 0 },
-+{"c.sllr",    "32C", "Ct,Cs",  MATCH_C_SLLR, MASK_C_SLLR, match_opcode, 0 },
-+{"c.srlr",    "32C", "Ct,Cs",  MATCH_C_SRLR, MASK_C_SRLR, match_opcode, 0 },
-+{"c.sltr",    "32C", "Ct,Cs",  MATCH_C_SLTR, MASK_C_SLTR, match_opcode, 0 },
-+{"c.sltur",   "32C", "Ct,Cs",  MATCH_C_SLTUR, MASK_C_SLTUR, match_opcode, 0 },
-+{"c.addin",   "32C", "Ct,Cs,Ci",  MATCH_C_ADDIN, MASK_C_ADDIN, match_opcode, 0 },
-+{"c.xorin",   "32C", "Ct,Cs,Ci",  MATCH_C_XORIN, MASK_C_XORIN, match_opcode, 0 },
-+{"c.orin",    "32C", "Ct,Cs,Ci",  MATCH_C_ORIN, MASK_C_ORIN, match_opcode, 0 },
-+{"c.andin",   "32C", "Ct,Cs,Ci",  MATCH_C_ANDIN, MASK_C_ANDIN, match_opcode, 0 },
-+{"c.andi",    "32C", "CD,Cj",  MATCH_C_ANDI, MASK_C_ANDI, match_rd_nonzero, 0 },
-+{"c.bltz",    "32C", "Cs,Cp",  MATCH_C_BLTZ, MASK_C_BLTZ, match_opcode, 0 },
-+{"c.bgez",    "32C", "Cs,Cp",  MATCH_C_BGEZ, MASK_C_BGEZ, match_opcode, 0 },
-+
-+/* Atomic memory operation instruction subset */
-+{"lr.w",         "A",   "d,0(s)",    MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
-+{"sc.w",         "A",   "d,t,0(s)",  MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoadd.w",     "A",   "d,t,0(s)",  MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoswap.w",    "A",   "d,t,0(s)",  MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoand.w",     "A",   "d,t,0(s)",  MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoor.w",      "A",   "d,t,0(s)",  MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoxor.w",     "A",   "d,t,0(s)",  MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomax.w",     "A",   "d,t,0(s)",  MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomaxu.w",    "A",   "d,t,0(s)",  MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomin.w",     "A",   "d,t,0(s)",  MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amominu.w",    "A",   "d,t,0(s)",  MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"lr.w.aq",      "A",   "d,0(s)",    MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
-+{"sc.w.aq",      "A",   "d,t,0(s)",  MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoadd.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoswap.w.aq", "A",   "d,t,0(s)",  MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoand.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoor.w.aq",   "A",   "d,t,0(s)",  MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoxor.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomax.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomaxu.w.aq", "A",   "d,t,0(s)",  MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomin.w.aq",  "A",   "d,t,0(s)",  MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amominu.w.aq", "A",   "d,t,0(s)",  MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"lr.w.rl",      "A",   "d,0(s)",    MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
-+{"sc.w.rl",      "A",   "d,t,0(s)",  MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoadd.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoswap.w.rl", "A",   "d,t,0(s)",  MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoand.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoor.w.rl",   "A",   "d,t,0(s)",  MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoxor.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomax.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomaxu.w.rl", "A",   "d,t,0(s)",  MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomin.w.rl",  "A",   "d,t,0(s)",  MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amominu.w.rl", "A",   "d,t,0(s)",  MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"lr.w.sc",      "A",   "d,0(s)",    MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
-+{"sc.w.sc",      "A",   "d,t,0(s)",  MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoadd.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoswap.w.sc", "A",   "d,t,0(s)",  MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoand.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoor.w.sc",   "A",   "d,t,0(s)",  MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoxor.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomax.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomaxu.w.sc", "A",   "d,t,0(s)",  MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomin.w.sc",  "A",   "d,t,0(s)",  MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amominu.w.sc", "A",   "d,t,0(s)",  MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"lr.d",         "64A", "d,0(s)",    MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
-+{"sc.d",         "64A", "d,t,0(s)",  MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoadd.d",     "64A", "d,t,0(s)",  MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoswap.d",    "64A", "d,t,0(s)",  MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoand.d",     "64A", "d,t,0(s)",  MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoor.d",      "64A", "d,t,0(s)",  MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoxor.d",     "64A", "d,t,0(s)",  MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomax.d",     "64A", "d,t,0(s)",  MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomaxu.d",    "64A", "d,t,0(s)",  MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomin.d",     "64A", "d,t,0(s)",  MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amominu.d",    "64A", "d,t,0(s)",  MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"lr.d.aq",      "64A", "d,0(s)",    MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
-+{"sc.d.aq",      "64A", "d,t,0(s)",  MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoadd.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoswap.d.aq", "64A", "d,t,0(s)",  MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoand.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoor.d.aq",   "64A", "d,t,0(s)",  MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoxor.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomax.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomaxu.d.aq", "64A", "d,t,0(s)",  MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomin.d.aq",  "64A", "d,t,0(s)",  MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amominu.d.aq", "64A", "d,t,0(s)",  MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"lr.d.rl",      "64A", "d,0(s)",    MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
-+{"sc.d.rl",      "64A", "d,t,0(s)",  MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoadd.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoswap.d.rl", "64A", "d,t,0(s)",  MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoand.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoor.d.rl",   "64A", "d,t,0(s)",  MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoxor.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomax.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomaxu.d.rl", "64A", "d,t,0(s)",  MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomin.d.rl",  "64A", "d,t,0(s)",  MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amominu.d.rl", "64A", "d,t,0(s)",  MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"lr.d.sc",      "64A", "d,0(s)",    MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1 },
-+{"sc.d.sc",      "64A", "d,t,0(s)",  MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoadd.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoswap.d.sc", "64A", "d,t,0(s)",  MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoand.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoor.d.sc",   "64A", "d,t,0(s)",  MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amoxor.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomax.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomaxu.d.sc", "64A", "d,t,0(s)",  MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amomin.d.sc",  "64A", "d,t,0(s)",  MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+{"amominu.d.sc", "64A", "d,t,0(s)",  MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode,   WR_xd|RD_xs1|RD_xs2 },
-+
-+/* Multiply/Divide instruction subset */
-+{"mul",       "M",   "d,s,t",  MATCH_MUL, MASK_MUL, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"mulh",      "M",   "d,s,t",  MATCH_MULH, MASK_MULH, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"mulhu",     "M",   "d,s,t",  MATCH_MULHU, MASK_MULHU, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"mulhsu",    "M",   "d,s,t",  MATCH_MULHSU, MASK_MULHSU, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"div",       "M",   "d,s,t",  MATCH_DIV, MASK_DIV, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"divu",      "M",   "d,s,t",  MATCH_DIVU, MASK_DIVU, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"rem",       "M",   "d,s,t",  MATCH_REM, MASK_REM, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"remu",      "M",   "d,s,t",  MATCH_REMU, MASK_REMU, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"mulw",      "64M", "d,s,t",  MATCH_MULW, MASK_MULW, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"divw",      "64M", "d,s,t",  MATCH_DIVW, MASK_DIVW, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"divuw",     "64M", "d,s,t",  MATCH_DIVUW, MASK_DIVUW, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"remw",      "64M", "d,s,t",  MATCH_REMW, MASK_REMW, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+{"remuw",     "64M", "d,s,t",  MATCH_REMUW, MASK_REMUW, match_opcode,  WR_xd|RD_xs1|RD_xs2 },
-+
-+/* Single-precision floating-point instruction subset */
-+{"frsr",      "F",   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode,  WR_xd },
-+{"fssr",      "F",   "s",  MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode,  RD_xs1 },
-+{"fssr",      "F",   "d,s",  MATCH_FSCSR, MASK_FSCSR, match_opcode,  WR_xd|RD_xs1 },
-+{"frcsr",     "F",   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode,  WR_xd },
-+{"fscsr",     "F",   "s",  MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode,  RD_xs1 },
-+{"fscsr",     "F",   "d,s",  MATCH_FSCSR, MASK_FSCSR, match_opcode,  WR_xd|RD_xs1 },
-+{"frrm",      "F",   "d",  MATCH_FRRM, MASK_FRRM, match_opcode,  WR_xd },
-+{"fsrm",      "F",   "s",  MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode,  RD_xs1 },
-+{"fsrm",      "F",   "d,s",  MATCH_FSRM, MASK_FSRM, match_opcode,  WR_xd|RD_xs1 },
-+{"frflags",   "F",   "d",  MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode,  WR_xd },
-+{"fsflags",   "F",   "s",  MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode,  RD_xs1 },
-+{"fsflags",   "F",   "d,s",  MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode,  WR_xd|RD_xs1 },
-+{"flw",       "F",   "D,o(s)",  MATCH_FLW, MASK_FLW, match_opcode,   WR_fd|RD_xs1 },
-+{"flw",       "F",   "D,A,s",  0, (int) M_FLW, match_never,  INSN_MACRO },
-+{"fsw",       "F",   "T,q(s)",  MATCH_FSW, MASK_FSW, match_opcode,   RD_xs1|RD_fs2 },
-+{"fsw",       "F",   "T,A,s",  0, (int) M_FSW, match_never,  INSN_MACRO },
-+{"fmv.x.s",   "F",   "d,S",  MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode,  WR_xd|RD_fs1 },
-+{"fmv.s.x",   "F",   "D,s",  MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode,  WR_fd|RD_xs1 },
-+{"fmv.s",     "F",   "D,U",  MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2,   INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 },
-+{"fneg.s",    "F",   "D,U",  MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2,   INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 },
-+{"fabs.s",    "F",   "D,U",  MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2,   INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 },
-+{"fsgnj.s",   "F",   "D,S,T",  MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsgnjn.s",  "F",   "D,S,T",  MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsgnjx.s",  "F",   "D,S,T",  MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fadd.s",    "F",   "D,S,T",  MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fadd.s",    "F",   "D,S,T,m",  MATCH_FADD_S, MASK_FADD_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsub.s",    "F",   "D,S,T",  MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsub.s",    "F",   "D,S,T,m",  MATCH_FSUB_S, MASK_FSUB_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fmul.s",    "F",   "D,S,T",  MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fmul.s",    "F",   "D,S,T,m",  MATCH_FMUL_S, MASK_FMUL_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fdiv.s",    "F",   "D,S,T",  MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fdiv.s",    "F",   "D,S,T,m",  MATCH_FDIV_S, MASK_FDIV_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsqrt.s",   "F",   "D,S",  MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode,  WR_fd|RD_fs1 },
-+{"fsqrt.s",   "F",   "D,S,m",  MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode,  WR_fd|RD_fs1 },
-+{"fmin.s",    "F",   "D,S,T",  MATCH_FMIN_S, MASK_FMIN_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fmax.s",    "F",   "D,S,T",  MATCH_FMAX_S, MASK_FMAX_S, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fmadd.s",   "F",   "D,S,T,R",  MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmadd.s",   "F",   "D,S,T,R,m",  MATCH_FMADD_S, MASK_FMADD_S, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmadd.s",  "F",   "D,S,T,R",  MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmadd.s",  "F",   "D,S,T,R,m",  MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmsub.s",   "F",   "D,S,T,R",  MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmsub.s",   "F",   "D,S,T,R,m",  MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmsub.s",  "F",   "D,S,T,R",  MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmsub.s",  "F",   "D,S,T,R,m",  MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fcvt.w.s",  "F",   "d,S",  MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.w.s",  "F",   "d,S,m",  MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.wu.s", "F",   "d,S",  MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.wu.s", "F",   "d,S,m",  MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.s.w",  "F",   "D,s",  MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.s.w",  "F",   "D,s,m",  MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.s.wu", "F",   "D,s",  MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.s.wu", "F",   "D,s,m",  MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode,   WR_fd|RD_xs1 },
-+{"fclass.s",  "F",   "d,S",  MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode,   WR_xd|RD_fs1 },
-+{"feq.s",     "F",   "d,S,T",    MATCH_FEQ_S, MASK_FEQ_S, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"flt.s",     "F",   "d,S,T",    MATCH_FLT_S, MASK_FLT_S, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"fle.s",     "F",   "d,S,T",    MATCH_FLE_S, MASK_FLE_S, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"fgt.s",     "F",   "d,T,S",    MATCH_FLT_S, MASK_FLT_S, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"fge.s",     "F",   "d,T,S",    MATCH_FLE_S, MASK_FLE_S, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"fcvt.l.s",  "64F", "d,S",  MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.l.s",  "64F", "d,S,m",  MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.lu.s", "64F", "d,S",  MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.lu.s", "64F", "d,S,m",  MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.s.l",  "64F", "D,s",  MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.s.l",  "64F", "D,s,m",  MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.s.lu", "64F", "D,s",  MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.s.lu", "64F", "D,s,m",  MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode,   WR_fd|RD_xs1 },
-+
-+/* Double-precision floating-point instruction subset */
-+{"fld",       "D",   "D,o(s)",  MATCH_FLD, MASK_FLD, match_opcode,  WR_fd|RD_xs1 },
-+{"fld",       "D",   "D,A,s",  0, (int) M_FLD, match_never,  INSN_MACRO },
-+{"fsd",       "D",   "T,q(s)",  MATCH_FSD, MASK_FSD, match_opcode,  RD_xs1|RD_fs2 },
-+{"fsd",       "D",   "T,A,s",  0, (int) M_FSD, match_never,  INSN_MACRO },
-+{"fmv.d",     "D",   "D,U",  MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2,   INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 },
-+{"fneg.d",    "D",   "D,U",  MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2,   INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 },
-+{"fabs.d",    "D",   "D,U",  MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2,   INSN_ALIAS|WR_fd|RD_fs1|RD_fs2 },
-+{"fsgnj.d",   "D",   "D,S,T",  MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsgnjn.d",  "D",   "D,S,T",  MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsgnjx.d",  "D",   "D,S,T",  MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fadd.d",    "D",   "D,S,T",  MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fadd.d",    "D",   "D,S,T,m",  MATCH_FADD_D, MASK_FADD_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsub.d",    "D",   "D,S,T",  MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsub.d",    "D",   "D,S,T,m",  MATCH_FSUB_D, MASK_FSUB_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fmul.d",    "D",   "D,S,T",  MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fmul.d",    "D",   "D,S,T,m",  MATCH_FMUL_D, MASK_FMUL_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fdiv.d",    "D",   "D,S,T",  MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fdiv.d",    "D",   "D,S,T,m",  MATCH_FDIV_D, MASK_FDIV_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fsqrt.d",   "D",   "D,S",  MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode,  WR_fd|RD_fs1 },
-+{"fsqrt.d",   "D",   "D,S,m",  MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode,  WR_fd|RD_fs1 },
-+{"fmin.d",    "D",   "D,S,T",  MATCH_FMIN_D, MASK_FMIN_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fmax.d",    "D",   "D,S,T",  MATCH_FMAX_D, MASK_FMAX_D, match_opcode,   WR_fd|RD_fs1|RD_fs2 },
-+{"fmadd.d",   "D",   "D,S,T,R",  MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmadd.d",   "D",   "D,S,T,R,m",  MATCH_FMADD_D, MASK_FMADD_D, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmadd.d",  "D",   "D,S,T,R",  MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmadd.d",  "D",   "D,S,T,R,m",  MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmsub.d",   "D",   "D,S,T,R",  MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmsub.d",   "D",   "D,S,T,R,m",  MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmsub.d",  "D",   "D,S,T,R",  MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmsub.d",  "D",   "D,S,T,R,m",  MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode,   WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fcvt.w.d",  "D",   "d,S",  MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.w.d",  "D",   "d,S,m",  MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.wu.d", "D",   "d,S",  MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.wu.d", "D",   "d,S,m",  MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.d.w",  "D",   "D,s",  MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.d.wu", "D",   "D,s",  MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.d.s",  "D",   "D,S",  MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode,   WR_fd|RD_fs1 },
-+{"fcvt.s.d",  "D",   "D,S",  MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode,   WR_fd|RD_fs1 },
-+{"fcvt.s.d",  "D",   "D,S,m",  MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode,   WR_fd|RD_fs1 },
-+{"fclass.d",  "D",   "d,S",  MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode,   WR_xd|RD_fs1 },
-+{"feq.d",     "D",   "d,S,T",    MATCH_FEQ_D, MASK_FEQ_D, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"flt.d",     "D",   "d,S,T",    MATCH_FLT_D, MASK_FLT_D, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"fle.d",     "D",   "d,S,T",    MATCH_FLE_D, MASK_FLE_D, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"fgt.d",     "D",   "d,T,S",    MATCH_FLT_D, MASK_FLT_D, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"fge.d",     "D",   "d,T,S",    MATCH_FLE_D, MASK_FLE_D, match_opcode,  WR_xd|RD_fs1|RD_fs2 },
-+{"fmv.x.d",   "64D", "d,S",  MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode,  WR_xd|RD_fs1 },
-+{"fmv.d.x",   "64D", "D,s",  MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode,  WR_fd|RD_xs1 },
-+{"fcvt.l.d",  "64D", "d,S",  MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.l.d",  "64D", "d,S,m",  MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.lu.d", "64D", "d,S",  MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.lu.d", "64D", "d,S,m",  MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode,  WR_xd|RD_fs1 },
-+{"fcvt.d.l",  "64D", "D,s",  MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.d.l",  "64D", "D,s,m",  MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.d.lu", "64D", "D,s",  MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode,   WR_fd|RD_xs1 },
-+{"fcvt.d.lu", "64D", "D,s,m",  MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode,   WR_fd|RD_xs1 },
++{"c.fldsp",   "C",   "D,Cn(Cc)",  MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, 0 },
++{"c.fld",     "C",   "CD,Cl(Cs)",  MATCH_C_FLD, MASK_C_FLD, match_opcode, 0 },
++{"c.fsdsp",   "C",   "CT,CN(Cc)",  MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, 0 },
++{"c.fsd",     "C",   "CD,Cl(Cs)",  MATCH_C_FSD, MASK_C_FSD, match_opcode, 0 },
++{"c.flwsp",   "32C", "D,Cm(Cc)",  MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, 0 },
++{"c.flw",     "32C", "CD,Ck(Cs)",  MATCH_C_FLW, MASK_C_FLW, match_opcode, 0 },
++{"c.fswsp",   "32C", "CT,CM(Cc)",  MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, 0 },
++{"c.fsw",     "32C", "CD,Ck(Cs)",  MATCH_C_FSW, MASK_C_FSW, match_opcode, 0 },
 +
 +/* Supervisor instructions */
-+{"csrr",      "I",   "d,E",  MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode,  WR_xd },
-+{"csrwi",     "I",   "E,Z",  MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode,  WR_xd|RD_xs1 },
-+{"csrw",      "I",   "E,s",  MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode,  RD_xs1 },
-+{"csrw",      "I",   "E,Z",  MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode,  WR_xd|RD_xs1 },
-+{"csrsi",     "I",   "E,Z",  MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode,  WR_xd|RD_xs1 },
-+{"csrs",      "I",   "E,s",  MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode,  WR_xd|RD_xs1 },
-+{"csrs",      "I",   "E,Z",  MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode,  WR_xd|RD_xs1 },
-+{"csrci",     "I",   "E,Z",  MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode,  WR_xd|RD_xs1 },
-+{"csrc",      "I",   "E,s",  MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode,  WR_xd|RD_xs1 },
-+{"csrc",      "I",   "E,Z",  MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrw",     "I",   "d,E,s",  MATCH_CSRRW, MASK_CSRRW, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrw",     "I",   "d,E,Z",  MATCH_CSRRWI, MASK_CSRRWI, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrs",     "I",   "d,E,s",  MATCH_CSRRS, MASK_CSRRS, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrs",     "I",   "d,E,Z",  MATCH_CSRRSI, MASK_CSRRSI, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrc",     "I",   "d,E,s",  MATCH_CSRRC, MASK_CSRRC, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrc",     "I",   "d,E,Z",  MATCH_CSRRCI, MASK_CSRRCI, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrwi",    "I",   "d,E,Z",  MATCH_CSRRWI, MASK_CSRRWI, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrsi",    "I",   "d,E,Z",  MATCH_CSRRSI, MASK_CSRRSI, match_opcode,  WR_xd|RD_xs1 },
-+{"csrrci",    "I",   "d,E,Z",  MATCH_CSRRCI, MASK_CSRRCI, match_opcode,  WR_xd|RD_xs1 },
-+{"eret",      "I",   "",     MATCH_SRET, MASK_SRET, match_opcode,  0 },
-+{"sret",      "I",   "",     MATCH_SRET, MASK_SRET, match_opcode,  0 },
-+{"mrts",      "I",   "",     MATCH_MRTS, MASK_MRTS, match_opcode,  0 },
-+{"sfence.vm", "I",   "",     MATCH_SFENCE_VM | MASK_RS1, MASK_SFENCE_VM | MASK_RS1, match_opcode,  0 },
-+{"sfence.vm", "I",   "s",    MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode,  RD_xs1 },
-+{"wfi",       "I",   "",     MATCH_WFI, MASK_WFI, match_opcode,  0 },
-+
-+/* Half-precision floating-point instruction subset */
-+{"flh",       "Xhwacha",   "D,o(s)",  MATCH_FLH, MASK_FLH, match_opcode, WR_fd|RD_xs1 },
-+{"fsh",       "Xhwacha",   "T,q(s)",  MATCH_FSH, MASK_FSH, match_opcode, RD_xs1|RD_fs2 },
-+{"fsgnj.h",   "Xhwacha",   "D,S,T",  MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fsgnjn.h",  "Xhwacha",   "D,S,T",  MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fsgnjx.h",  "Xhwacha",   "D,S,T",  MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fadd.h",    "Xhwacha",   "D,S,T",  MATCH_FADD_H | MASK_RM, MASK_FADD_H | MASK_RM, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fadd.h",    "Xhwacha",   "D,S,T,m",  MATCH_FADD_H, MASK_FADD_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fsub.h",    "Xhwacha",   "D,S,T",  MATCH_FSUB_H | MASK_RM, MASK_FSUB_H | MASK_RM, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fsub.h",    "Xhwacha",   "D,S,T,m",  MATCH_FSUB_H, MASK_FSUB_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fmul.h",    "Xhwacha",   "D,S,T",  MATCH_FMUL_H | MASK_RM, MASK_FMUL_H | MASK_RM, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fmul.h",    "Xhwacha",   "D,S,T,m",  MATCH_FMUL_H, MASK_FMUL_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fdiv.h",    "Xhwacha",   "D,S,T",  MATCH_FDIV_H | MASK_RM, MASK_FDIV_H | MASK_RM, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fdiv.h",    "Xhwacha",   "D,S,T,m",  MATCH_FDIV_H, MASK_FDIV_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fsqrt.h",   "Xhwacha",   "D,S",  MATCH_FSQRT_H | MASK_RM, MASK_FSQRT_H | MASK_RM, match_opcode, WR_fd|RD_fs1 },
-+{"fsqrt.h",   "Xhwacha",   "D,S,m",  MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, WR_fd|RD_fs1 },
-+{"fmin.h",    "Xhwacha",   "D,S,T",  MATCH_FMIN_H, MASK_FMIN_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fmax.h",    "Xhwacha",   "D,S,T",  MATCH_FMAX_H, MASK_FMAX_H, match_opcode,  WR_fd|RD_fs1|RD_fs2 },
-+{"fmadd.h",   "Xhwacha",   "D,S,T,R",  MATCH_FMADD_H | MASK_RM, MASK_FMADD_H | MASK_RM, match_opcode,  WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmadd.h",   "Xhwacha",   "D,S,T,R,m",  MATCH_FMADD_H, MASK_FMADD_H, match_opcode,  WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmadd.h",  "Xhwacha",   "D,S,T,R",  MATCH_FNMADD_H | MASK_RM, MASK_FNMADD_H | MASK_RM, match_opcode,  WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmadd.h",  "Xhwacha",   "D,S,T,R,m",  MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode,  WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmsub.h",   "Xhwacha",   "D,S,T,R",  MATCH_FMSUB_H | MASK_RM, MASK_FMSUB_H | MASK_RM, match_opcode,  WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fmsub.h",   "Xhwacha",   "D,S,T,R,m",  MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode,  WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmsub.h",  "Xhwacha",   "D,S,T,R",  MATCH_FNMSUB_H | MASK_RM, MASK_FNMSUB_H | MASK_RM, match_opcode,  WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fnmsub.h",  "Xhwacha",   "D,S,T,R,m",  MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode,  WR_fd|RD_fs1|RD_fs2|RD_fs3 },
-+{"fcvt.s.h",  "Xhwacha",   "D,S",  MATCH_FCVT_S_H, MASK_FCVT_S_H | MASK_RM, match_opcode,  WR_fd|RD_fs1 },
-+{"fcvt.h.s",  "Xhwacha",   "D,S",  MATCH_FCVT_H_S | MASK_RM, MASK_FCVT_H_S | MASK_RM, match_opcode,  WR_fd|RD_fs1 },
-+{"fcvt.h.s",  "Xhwacha",   "D,S,m",  MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode,  WR_fd|RD_fs1 },
-+{"fcvt.d.h",  "Xhwacha",   "D,S",  MATCH_FCVT_D_H, MASK_FCVT_D_H | MASK_RM, match_opcode,  WR_fd|RD_fs1 },
-+{"fcvt.h.d",  "Xhwacha",   "D,S",  MATCH_FCVT_H_D | MASK_RM, MASK_FCVT_H_D | MASK_RM, match_opcode,  WR_fd|RD_fs1 },
-+{"fcvt.h.d",  "Xhwacha",   "D,S,m",  MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode,  WR_fd|RD_fs1 },
-+{"feq.h",     "Xhwacha",   "d,S,T",    MATCH_FEQ_H, MASK_FEQ_H, match_opcode, WR_xd|RD_fs1|RD_fs2 },
-+{"flt.h",     "Xhwacha",   "d,S,T",    MATCH_FLT_H, MASK_FLT_H, match_opcode, WR_xd|RD_fs1|RD_fs2 },
-+{"fle.h",     "Xhwacha",   "d,S,T",    MATCH_FLE_H, MASK_FLE_H, match_opcode, WR_xd|RD_fs1|RD_fs2 },
-+{"fgt.h",     "Xhwacha",   "d,T,S",    MATCH_FLT_H, MASK_FLT_H, match_opcode, WR_xd|RD_fs1|RD_fs2 },
-+{"fge.h",     "Xhwacha",   "d,T,S",    MATCH_FLE_H, MASK_FLE_H, match_opcode, WR_xd|RD_fs1|RD_fs2 },
-+{"fmv.x.h",   "Xhwacha",   "d,S",  MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, WR_xd|RD_fs1 },
-+{"fmv.h.x",   "Xhwacha",   "D,s",  MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, WR_fd|RD_xs1 },
-+{"fcvt.w.h",  "Xhwacha",   "d,S",  MATCH_FCVT_W_H | MASK_RM, MASK_FCVT_W_H | MASK_RM, match_opcode, WR_xd|RD_fs1 },
-+{"fcvt.w.h",  "Xhwacha",   "d,S,m",  MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, WR_xd|RD_fs1 },
-+{"fcvt.wu.h", "Xhwacha",   "d,S",  MATCH_FCVT_WU_H | MASK_RM, MASK_FCVT_WU_H | MASK_RM, match_opcode, WR_xd|RD_fs1 },
-+{"fcvt.wu.h", "Xhwacha",   "d,S,m",  MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, WR_xd|RD_fs1 },
-+{"fcvt.h.w",  "Xhwacha",   "D,s",  MATCH_FCVT_H_W, MASK_FCVT_H_W | MASK_RM, match_opcode,  WR_fd|RD_xs1 },
-+{"fcvt.h.wu", "Xhwacha",   "D,s",  MATCH_FCVT_H_WU, MASK_FCVT_H_WU | MASK_RM, match_opcode,  WR_fd|RD_xs1 },
-+{"fcvt.l.h",  "Xhwacha", "d,S",  MATCH_FCVT_L_H | MASK_RM, MASK_FCVT_L_H | MASK_RM, match_opcode, WR_xd|RD_fs1 },
-+{"fcvt.l.h",  "Xhwacha", "d,S,m",  MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, WR_xd|RD_fs1 },
-+{"fcvt.lu.h", "Xhwacha", "d,S",  MATCH_FCVT_LU_H | MASK_RM, MASK_FCVT_LU_H | MASK_RM, match_opcode, WR_xd|RD_fs1 },
-+{"fcvt.lu.h", "Xhwacha", "d,S,m",  MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, WR_xd|RD_fs1 },
-+{"fcvt.h.l",  "Xhwacha", "D,s",  MATCH_FCVT_H_L | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode,  WR_fd|RD_xs1 },
-+{"fcvt.h.l",  "Xhwacha", "D,s,m",  MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode,  WR_fd|RD_xs1 },
-+{"fcvt.h.lu", "Xhwacha", "D,s",  MATCH_FCVT_H_LU | MASK_RM, MASK_FCVT_H_L | MASK_RM, match_opcode,  WR_fd|RD_xs1 },
-+{"fcvt.h.lu", "Xhwacha", "D,s,m",  MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode,  WR_fd|RD_xs1 },
++{"csrr",      "I",   "d,E",  MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, 0 },
++{"csrwi",     "I",   "E,Z",  MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, 0 },
++{"csrw",      "I",   "E,s",  MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, 0 },
++{"csrw",      "I",   "E,Z",  MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, 0 },
++{"csrsi",     "I",   "E,Z",  MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, 0 },
++{"csrs",      "I",   "E,s",  MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, 0 },
++{"csrs",      "I",   "E,Z",  MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, 0 },
++{"csrci",     "I",   "E,Z",  MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, 0 },
++{"csrc",      "I",   "E,s",  MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, 0 },
++{"csrc",      "I",   "E,Z",  MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, 0 },
++{"csrrw",     "I",   "d,E,s",  MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 },
++{"csrrw",     "I",   "d,E,Z",  MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
++{"csrrs",     "I",   "d,E,s",  MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 },
++{"csrrs",     "I",   "d,E,Z",  MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
++{"csrrc",     "I",   "d,E,s",  MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 },
++{"csrrc",     "I",   "d,E,Z",  MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
++{"csrrwi",    "I",   "d,E,Z",  MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 },
++{"csrrsi",    "I",   "d,E,Z",  MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 },
++{"csrrci",    "I",   "d,E,Z",  MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 },
++{"eret",      "I",   "",     MATCH_SRET, MASK_SRET, match_opcode, 0 },
++{"sret",      "I",   "",     MATCH_SRET, MASK_SRET, match_opcode, 0 },
++{"sfence.vm", "I",   "",     MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 },
++{"sfence.vm", "I",   "s",    MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 },
++{"wfi",       "I",   "",     MATCH_WFI, MASK_WFI, match_opcode, 0 },
 +
 +/* Rocket Custom Coprocessor extension */
 +{"custom0",   "Xcustom", "d,s,t,^j", MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2, match_opcode, 0},
@@ -9805,152 +9187,21 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +{"custom3",   "Xcustom", "^d,s,t,^j", MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2, match_opcode, 0},
 +{"custom3",   "Xcustom", "^d,s,^t,^j", MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1, match_opcode, 0},
 +{"custom3",   "Xcustom", "^d,^s,^t,^j", MATCH_CUSTOM3, MASK_CUSTOM3, match_opcode, 0},
-+
-+/* Xhwacha extension */
-+{"stop",      "Xhwacha", "", MATCH_STOP, MASK_STOP, match_opcode, 0},
-+{"utidx",     "Xhwacha", "d", MATCH_UTIDX, MASK_UTIDX, match_opcode, WR_xd},
-+{"movz",      "Xhwacha", "d,s,t", MATCH_MOVZ, MASK_MOVZ, match_opcode, WR_xd|RD_xs1|RD_xs2},
-+{"movn",      "Xhwacha", "d,s,t", MATCH_MOVN, MASK_MOVN, match_opcode, WR_xd|RD_xs1|RD_xs2},
-+{"fmovz",     "Xhwacha", "D,s,T", MATCH_FMOVZ, MASK_FMOVZ, match_opcode, WR_fd|RD_xs1|RD_fs2},
-+{"fmovn",     "Xhwacha", "D,s,T", MATCH_FMOVN, MASK_FMOVN, match_opcode, WR_fd|RD_xs1|RD_fs2},
-+
-+/* unit stride */
-+/* xloads */
-+{"vld",       "Xhwacha", "#d,s", MATCH_VLD, MASK_VLD, match_opcode, 0},
-+{"vlw",       "Xhwacha", "#d,s", MATCH_VLW, MASK_VLW, match_opcode, 0},
-+{"vlwu",      "Xhwacha", "#d,s", MATCH_VLWU, MASK_VLWU, match_opcode, 0},
-+{"vlh",       "Xhwacha", "#d,s", MATCH_VLH, MASK_VLH, match_opcode, 0},
-+{"vlhu",      "Xhwacha", "#d,s", MATCH_VLHU, MASK_VLHU, match_opcode, 0},
-+{"vlb",       "Xhwacha", "#d,s", MATCH_VLB, MASK_VLB, match_opcode, 0},
-+{"vlbu",      "Xhwacha", "#d,s", MATCH_VLBU, MASK_VLBU, match_opcode, 0},
-+/* floads */
-+{"vfld",      "Xhwacha", "#D,s", MATCH_VFLD, MASK_VFLD, match_opcode, 0},
-+{"vflw",      "Xhwacha", "#D,s", MATCH_VFLW, MASK_VFLW, match_opcode, 0},
-+
-+/* stride */
-+/* xloads */
-+{"vlstd",     "Xhwacha", "#d,s,t", MATCH_VLSTD, MASK_VLSTD, match_opcode, 0},
-+{"vlstw",     "Xhwacha", "#d,s,t", MATCH_VLSTW, MASK_VLSTW, match_opcode, 0},
-+{"vlstwu",    "Xhwacha", "#d,s,t", MATCH_VLSTWU, MASK_VLSTWU, match_opcode, 0},
-+{"vlsth",     "Xhwacha", "#d,s,t", MATCH_VLSTH, MASK_VLSTH, match_opcode, 0},
-+{"vlsthu",    "Xhwacha", "#d,s,t", MATCH_VLSTHU, MASK_VLSTHU, match_opcode, 0},
-+{"vlstb",     "Xhwacha", "#d,s,t", MATCH_VLSTB, MASK_VLSTB, match_opcode, 0},
-+{"vlstbu",    "Xhwacha", "#d,s,t", MATCH_VLSTBU, MASK_VLSTBU, match_opcode, 0},
-+/* floads */
-+{"vflstd",    "Xhwacha", "#D,s,t", MATCH_VFLSTD, MASK_VFLSTD, match_opcode, 0},
-+{"vflstw",    "Xhwacha", "#D,s,t", MATCH_VFLSTW, MASK_VFLSTW, match_opcode, 0},
-+
-+/* segment */
-+/* xloads */
-+{"vlsegd",    "Xhwacha", "#d,s,#n", MATCH_VLSEGD, MASK_VLSEGD, match_opcode, 0},
-+{"vlsegw",    "Xhwacha", "#d,s,#n", MATCH_VLSEGW, MASK_VLSEGW, match_opcode, 0},
-+{"vlsegwu",   "Xhwacha", "#d,s,#n", MATCH_VLSEGWU, MASK_VLSEGWU, match_opcode, 0},
-+{"vlsegh",    "Xhwacha", "#d,s,#n", MATCH_VLSEGH, MASK_VLSEGH, match_opcode, 0},
-+{"vlseghu",   "Xhwacha", "#d,s,#n", MATCH_VLSEGHU, MASK_VLSEGHU, match_opcode, 0},
-+{"vlsegb",    "Xhwacha", "#d,s,#n", MATCH_VLSEGB, MASK_VLSEGB, match_opcode, 0},
-+{"vlsegbu",   "Xhwacha", "#d,s,#n", MATCH_VLSEGBU, MASK_VLSEGBU, match_opcode, 0},
-+/* floads */
-+{"vflsegd",   "Xhwacha", "#D,s,#n", MATCH_VFLSEGD, MASK_VFLSEGD, match_opcode, 0},
-+{"vflsegw",   "Xhwacha", "#D,s,#n", MATCH_VFLSEGW, MASK_VFLSEGW, match_opcode, 0},
-+
-+/* stride segment */
-+/* xloads */
-+{"vlsegstd",  "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTD, MASK_VLSEGSTD, match_opcode, 0},
-+{"vlsegstw",  "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTW, MASK_VLSEGSTW, match_opcode, 0},
-+{"vlsegstwu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTWU, MASK_VLSEGSTWU, match_opcode, 0},
-+{"vlsegsth",  "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTH, MASK_VLSEGSTH, match_opcode, 0},
-+{"vlsegsthu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTHU, MASK_VLSEGSTHU, match_opcode, 0},
-+{"vlsegstb",  "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTB, MASK_VLSEGSTB, match_opcode, 0},
-+{"vlsegstbu", "Xhwacha", "#d,s,t,#n", MATCH_VLSEGSTBU, MASK_VLSEGSTBU, match_opcode, 0},
-+/* floads */
-+{"vflsegstd", "Xhwacha", "#D,s,t,#n", MATCH_VFLSEGSTD, MASK_VFLSEGSTD, match_opcode, 0},
-+{"vflsegstw", "Xhwacha", "#D,s,t,#n", MATCH_VFLSEGSTW, MASK_VFLSEGSTW, match_opcode, 0},
-+
-+/* unit stride */
-+/* xstores */
-+{"vsd",       "Xhwacha", "#d,s", MATCH_VSD, MASK_VSD, match_opcode, 0},
-+{"vsw",       "Xhwacha", "#d,s", MATCH_VSW, MASK_VSW, match_opcode, 0},
-+{"vsh",       "Xhwacha", "#d,s", MATCH_VSH, MASK_VSH, match_opcode, 0},
-+{"vsb",       "Xhwacha", "#d,s", MATCH_VSB, MASK_VSB, match_opcode, 0},
-+/* fstores */
-+{"vfsd",      "Xhwacha", "#D,s", MATCH_VFSD, MASK_VFSD, match_opcode, 0},
-+{"vfsw",      "Xhwacha", "#D,s", MATCH_VFSW, MASK_VFSW, match_opcode, 0},
-+
-+/* stride */
-+/* xstores */
-+{"vsstd",     "Xhwacha", "#d,s,t", MATCH_VSSTD, MASK_VSSTD, match_opcode, 0},
-+{"vsstw",     "Xhwacha", "#d,s,t", MATCH_VSSTW, MASK_VSSTW, match_opcode, 0},
-+{"vssth",     "Xhwacha", "#d,s,t", MATCH_VSSTH, MASK_VSSTH, match_opcode, 0},
-+{"vsstb",     "Xhwacha", "#d,s,t", MATCH_VSSTB, MASK_VSSTB, match_opcode, 0},
-+/* fstores */
-+{"vfsstd",    "Xhwacha", "#D,s,t", MATCH_VFSSTD, MASK_VFSSTD, match_opcode, 0},
-+{"vfsstw",    "Xhwacha", "#D,s,t", MATCH_VFSSTW, MASK_VFSSTW, match_opcode, 0},
-+
-+/* segment */
-+/* xstores */
-+{"vssegd",    "Xhwacha", "#d,s,#n", MATCH_VSSEGD, MASK_VSSEGD, match_opcode, 0},
-+{"vssegw",    "Xhwacha", "#d,s,#n", MATCH_VSSEGW, MASK_VSSEGW, match_opcode, 0},
-+{"vssegh",    "Xhwacha", "#d,s,#n", MATCH_VSSEGH, MASK_VSSEGH, match_opcode, 0},
-+{"vssegb",    "Xhwacha", "#d,s,#n", MATCH_VSSEGB, MASK_VSSEGB, match_opcode, 0},
-+/* fstores */
-+{"vfssegd",   "Xhwacha", "#D,s,#n", MATCH_VFSSEGD, MASK_VFSSEGD, match_opcode, 0},
-+{"vfssegw",   "Xhwacha", "#D,s,#n", MATCH_VFSSEGW, MASK_VFSSEGW, match_opcode, 0},
-+
-+/* stride segment */
-+/* xsegstores */
-+{"vssegstd",  "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTD, MASK_VSSEGSTD, match_opcode, 0},
-+{"vssegstw",  "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTW, MASK_VSSEGSTW, match_opcode, 0},
-+{"vssegsth",  "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTH, MASK_VSSEGSTH, match_opcode, 0},
-+{"vssegstb",  "Xhwacha", "#d,s,t,#n", MATCH_VSSEGSTB, MASK_VSSEGSTB, match_opcode, 0},
-+/* fsegstores */
-+{"vfssegstd", "Xhwacha", "#D,s,t,#n", MATCH_VFSSEGSTD, MASK_VFSSEGSTD, match_opcode, 0},
-+{"vfssegstw", "Xhwacha", "#D,s,t,#n", MATCH_VFSSEGSTW, MASK_VFSSEGSTW, match_opcode, 0},
-+
-+{"vsetcfg",   "Xhwacha", "s", MATCH_VSETCFG, MASK_VSETCFG | MASK_IMM, match_opcode, 0},
-+{"vsetcfg",   "Xhwacha", "#g,#f", MATCH_VSETCFG, MASK_VSETCFG | MASK_RS1, match_opcode, 0},
-+{"vsetcfg",   "Xhwacha", "s,#g,#f", MATCH_VSETCFG, MASK_VSETCFG, match_opcode, 0},
-+{"vsetucfg",  "Xhwacha", "d,u", MATCH_LUI, MASK_LUI, match_opcode, INSN_ALIAS | WR_xd},
-+{"vsetvl",    "Xhwacha", "d,s", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
-+{"vgetcfg",   "Xhwacha", "d", MATCH_VGETCFG, MASK_VGETCFG, match_opcode, 0},
-+{"vgetvl",    "Xhwacha", "d", MATCH_VGETVL, MASK_VGETVL, match_opcode, 0},
-+
-+{"vmvv",      "Xhwacha", "#d,#s", MATCH_VMVV, MASK_VMVV, match_opcode, 0},
-+{"vmsv",      "Xhwacha", "#d,s", MATCH_VMSV, MASK_VMSV, match_opcode, 0},
-+{"vfmvv",     "Xhwacha", "#D,#S", MATCH_VFMVV, MASK_VFMVV, match_opcode, 0},
-+{"vfmsv.d",   "Xhwacha", "#D,s", MATCH_VFMSV_D, MASK_VFMSV_D, match_opcode, 0},
-+{"vfmsv.s",   "Xhwacha", "#D,s", MATCH_VFMSV_S, MASK_VFMSV_S, match_opcode, 0},
-+
-+{"vf",        "Xhwacha", "q(s)", MATCH_VF, MASK_VF, match_opcode, 0},
-+{"vf",        "Xhwacha", "A,s", 0, (int) M_VF, match_never, INSN_MACRO },
-+
-+{"vxcptcause",   "Xhwacha", "d", MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE, match_opcode, 0},
-+{"vxcptaux",     "Xhwacha", "d", MATCH_VXCPTAUX, MASK_VXCPTAUX, match_opcode, 0},
-+
-+{"vxcptsave",    "Xhwacha", "s", MATCH_VXCPTSAVE, MASK_VXCPTSAVE, match_opcode, 0},
-+{"vxcptrestore", "Xhwacha", "s", MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE, match_opcode, 0},
-+{"vxcptkill",    "Xhwacha", "", MATCH_VXCPTKILL, MASK_VXCPTKILL, match_opcode, 0},
-+
-+{"vxcptevac",    "Xhwacha", "s", MATCH_VXCPTEVAC, MASK_VXCPTEVAC, match_opcode, 0},
-+{"vxcpthold",    "Xhwacha", "s", MATCH_VXCPTHOLD, MASK_VXCPTHOLD, match_opcode, 0},
-+{"venqcmd",      "Xhwacha", "s,t", MATCH_VENQCMD, MASK_VENQCMD, match_opcode, 0},
-+{"venqimm1",     "Xhwacha", "s,t", MATCH_VENQIMM1, MASK_VENQIMM1, match_opcode, 0},
-+{"venqimm2",     "Xhwacha", "s,t", MATCH_VENQIMM2, MASK_VENQIMM2, match_opcode, 0},
-+{"venqcnt",      "Xhwacha", "s,t", MATCH_VENQCNT, MASK_VENQCNT, match_opcode, 0},
 +};
 +
 +#define RISCV_NUM_OPCODES \
 +  ((sizeof riscv_builtin_opcodes) / (sizeof (riscv_builtin_opcodes[0])))
 +const int bfd_riscv_num_builtin_opcodes = RISCV_NUM_OPCODES;
 +
-+/* const removed from the following to allow for dynamic extensions to the
-+ * built-in instruction set. */
++/* Removed const from the following to allow for dynamic extensions to the
++   built-in instruction set.  */
 +struct riscv_opcode *riscv_opcodes =
 +  (struct riscv_opcode *) riscv_builtin_opcodes;
 +int bfd_riscv_num_opcodes = RISCV_NUM_OPCODES;
 +#undef RISCV_NUM_OPCODES
 --- original-binutils/bfd/archures.c
-+++ binutils-2.25/bfd/archures.c
-@@ -597,6 +597,7 @@ extern const bfd_arch_info_type bfd_pj_a
++++ binutils-2.26/bfd/archures.c
+@@ -612,6 +612,7 @@ extern const bfd_arch_info_type bfd_pj_a
  extern const bfd_arch_info_type bfd_plugin_arch;
  extern const bfd_arch_info_type bfd_powerpc_archs[];
  #define bfd_powerpc_arch bfd_powerpc_archs[0]
@@ -9958,7 +9209,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  extern const bfd_arch_info_type bfd_rs6000_arch;
  extern const bfd_arch_info_type bfd_rl78_arch;
  extern const bfd_arch_info_type bfd_rx_arch;
-@@ -683,6 +684,7 @@ static const bfd_arch_info_type * const
+@@ -701,6 +702,7 @@ static const bfd_arch_info_type * const
      &bfd_or1k_arch,
      &bfd_pdp11_arch,
      &bfd_powerpc_arch,
@@ -9967,22 +9218,22 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
      &bfd_rl78_arch,
      &bfd_rx_arch,
 --- original-binutils/bfd/bfd-in2.h
-+++ binutils-2.25/bfd/bfd-in2.h
-@@ -2043,6 +2043,9 @@ enum bfd_architecture
++++ binutils-2.26/bfd/bfd-in2.h
+@@ -2073,6 +2073,9 @@ enum bfd_architecture
  #define bfd_mach_ppc_e6500     5007
  #define bfd_mach_ppc_titan     83
  #define bfd_mach_ppc_vle       84
-+  bfd_arch_riscv, /* RISC-V */
-+#define bfd_mach_riscv32 132
-+#define bfd_mach_riscv64 164
++  bfd_arch_riscv,     /* RISC-V */
++#define bfd_mach_riscv32       132
++#define bfd_mach_riscv64       164
    bfd_arch_rs6000,    /* IBM RS/6000 */
  #define bfd_mach_rs6k          6000
  #define bfd_mach_rs6k_rs1      6001
-@@ -5531,6 +5534,43 @@ relative offset from _GLOBAL_OFFSET_TABL
+@@ -5652,6 +5655,46 @@ relative offset from _GLOBAL_OFFSET_TABL
  value in a word.  The relocation is relative offset from  */
    BFD_RELOC_MICROBLAZE_32_GOTOFF,
  
-+/* RISC-V relocations */
++/* RISC-V relocations.  */
 +  BFD_RELOC_RISCV_HI20,
 +  BFD_RELOC_RISCV_PCREL_HI20,
 +  BFD_RELOC_RISCV_PCREL_LO12_I,
@@ -10018,13 +9269,16 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +  BFD_RELOC_RISCV_ALIGN,
 +  BFD_RELOC_RISCV_RVC_BRANCH,
 +  BFD_RELOC_RISCV_RVC_JUMP,
++  BFD_RELOC_RISCV_RVC_LUI,
++  BFD_RELOC_RISCV_GPREL_I,
++  BFD_RELOC_RISCV_GPREL_S,
 +
  /* This is used to tell the dynamic linker to copy the value out of
  the dynamic object into the runtime process image.  */
    BFD_RELOC_MICROBLAZE_COPY,
 --- original-binutils/bfd/config.bfd
-+++ binutils-2.25/bfd/config.bfd
-@@ -119,6 +119,7 @@ or1k*|or1knd*)	 targ_archs=bfd_or1k_arch
++++ binutils-2.26/bfd/config.bfd
+@@ -120,6 +120,7 @@ or1k*|or1knd*)	 targ_archs=bfd_or1k_arch
  pdp11*)		 targ_archs=bfd_pdp11_arch ;;
  pj*)		 targ_archs="bfd_pj_arch bfd_i386_arch";;
  powerpc*)	 targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
@@ -10032,46 +9286,50 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  rs6000)		 targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
  s390*)		 targ_archs=bfd_s390_arch ;;
  sh*)		 targ_archs=bfd_sh_arch ;;
-@@ -1319,6 +1320,14 @@ case "${targ}" in
+@@ -1344,6 +1345,18 @@ case "${targ}" in
      targ_defvec=rl78_elf32_vec
      ;;
  
-+#ifdef BFD64
-+  riscv*-*-*)
++  riscv32-*-*)
++    targ_defvec=riscv_elf32_vec
++    targ_selvecs="riscv_elf32_vec"
++    want64=true
++    ;;
++
++  riscv64-*-*)
 +    targ_defvec=riscv_elf64_vec
 +    targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
 +    want64=true
 +    ;;
-+#endif
 +
    rx-*-elf)
      targ_defvec=rx_elf32_le_vec
      targ_selvecs="rx_elf32_be_vec rx_elf32_le_vec rx_elf32_be_ns_vec"
 --- original-binutils/bfd/configure
-+++ binutils-2.25/bfd/configure
-@@ -15506,6 +15506,8 @@ do
-     powerpc_pei_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
-     powerpc_pei_le_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
-     powerpc_xcoff_vec)		 tb="$tb coff-rs6000.lo xcofflink.lo" ;;
++++ binutils-2.26/bfd/configure
+@@ -15472,6 +15472,8 @@ do
+     powerpc_pei_vec)		 tb="$tb pei-ppc.lo peigen.lo $coff" ;;
+     powerpc_pei_le_vec)		 tb="$tb pei-ppc.lo peigen.lo $coff" ;;
+     powerpc_xcoff_vec)		 tb="$tb coff-rs6000.lo $xcoff" ;;
 +    riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
 +    riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
      rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
-     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
-     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
+     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
+     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
 --- original-binutils/bfd/configure.ac
-+++ binutils-2.25/bfd/configure.ac
-@@ -907,6 +907,8 @@ do
-     powerpc_pei_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
-     powerpc_pei_le_vec)		 tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;;
-     powerpc_xcoff_vec)		 tb="$tb coff-rs6000.lo xcofflink.lo" ;;
++++ binutils-2.26/bfd/configure.ac
+@@ -918,6 +918,8 @@ do
+     powerpc_pei_vec)		 tb="$tb pei-ppc.lo peigen.lo $coff" ;;
+     powerpc_pei_le_vec)		 tb="$tb pei-ppc.lo peigen.lo $coff" ;;
+     powerpc_xcoff_vec)		 tb="$tb coff-rs6000.lo $xcoff" ;;
 +    riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
 +    riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
      rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
-     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
-     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
+     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
+     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
 --- original-binutils/bfd/elf-bfd.h
-+++ binutils-2.25/bfd/elf-bfd.h
-@@ -433,6 +433,7 @@ enum elf_target_id
++++ binutils-2.26/bfd/elf-bfd.h
+@@ -475,6 +475,7 @@ enum elf_target_id
    XGATE_ELF_DATA,
    TILEGX_ELF_DATA,
    TILEPRO_ELF_DATA,
@@ -10080,9 +9338,9 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  };
  
 --- original-binutils/bfd/Makefile.am
-+++ binutils-2.25/bfd/Makefile.am
-@@ -931,6 +931,18 @@ elf64-ia64.c : elfnn-ia64.c
- 	sed -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
++++ binutils-2.26/bfd/Makefile.am
+@@ -949,6 +949,18 @@ elf64-ia64.c : elfnn-ia64.c
+ 	$(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
  	mv -f elf64-ia64.new elf64-ia64.c
  
 +elf32-riscv.c : elfnn-riscv.c
@@ -10099,11 +9357,27 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +
  peigen.c : peXXigen.c
  	rm -f peigen.c
- 	sed -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
+ 	$(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
 --- original-binutils/bfd/Makefile.in
-+++ binutils-2.25/bfd/Makefile.in
-@@ -2009,6 +2009,18 @@ elf64-ia64.c : elfnn-ia64.c
- 	sed -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
++++ binutils-2.26/bfd/Makefile.in
+@@ -450,6 +450,7 @@ ALL_MACHINES = \
+ 	cpu-pj.lo \
+ 	cpu-plugin.lo \
+ 	cpu-powerpc.lo \
++	cpu-riscv.lo \
+ 	cpu-rs6000.lo \
+ 	cpu-rl78.lo \
+ 	cpu-rx.lo \
+@@ -537,6 +538,7 @@ ALL_MACHINES_CFILES = \
+ 	cpu-pj.c \
+ 	cpu-plugin.c \
+ 	cpu-powerpc.c \
++	cpu-riscv.c \
+ 	cpu-rs6000.c \
+ 	cpu-rl78.c \
+ 	cpu-rx.c \
+@@ -2035,6 +2037,18 @@ elf64-ia64.c : elfnn-ia64.c
+ 	$(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
  	mv -f elf64-ia64.new elf64-ia64.c
  
 +elf32-riscv.c : elfnn-riscv.c
@@ -10120,10 +9394,10 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
 +
  peigen.c : peXXigen.c
  	rm -f peigen.c
- 	sed -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
+ 	$(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
 --- original-binutils/bfd/targets.c
-+++ binutils-2.25/bfd/targets.c
-@@ -784,6 +784,8 @@ extern const bfd_target powerpc_pe_le_ve
++++ binutils-2.26/bfd/targets.c
+@@ -793,6 +793,8 @@ extern const bfd_target powerpc_pe_le_ve
  extern const bfd_target powerpc_pei_vec;
  extern const bfd_target powerpc_pei_le_vec;
  extern const bfd_target powerpc_xcoff_vec;
@@ -10133,8 +9407,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  extern const bfd_target rs6000_xcoff64_vec;
  extern const bfd_target rs6000_xcoff64_aix_vec;
 --- original-binutils/binutils/readelf.c
-+++ binutils-2.25/binutils/readelf.c
-@@ -125,6 +125,7 @@
++++ binutils-2.26/binutils/readelf.c
+@@ -124,6 +124,7 @@
  #include "elf/metag.h"
  #include "elf/microblaze.h"
  #include "elf/mips.h"
@@ -10142,7 +9416,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  #include "elf/mmix.h"
  #include "elf/mn10200.h"
  #include "elf/mn10300.h"
-@@ -720,6 +721,7 @@ guess_is_rela (unsigned int e_machine)
+@@ -771,6 +772,7 @@ guess_is_rela (unsigned int e_machine)
      case EM_OR1K:
      case EM_PPC64:
      case EM_PPC:
@@ -10150,7 +9424,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
      case EM_RL78:
      case EM_RX:
      case EM_S390:
-@@ -1252,6 +1254,10 @@ dump_relocations (FILE * file,
+@@ -1309,6 +1311,10 @@ dump_relocations (FILE * file,
  	  rtype = elf_mips_reloc_type (type);
  	  break;
  
@@ -10161,7 +9435,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	case EM_ALPHA:
  	  rtype = elf_alpha_reloc_type (type);
  	  break;
-@@ -2164,6 +2170,7 @@ get_machine_name (unsigned e_machine)
+@@ -2250,6 +2256,7 @@ get_machine_name (unsigned e_machine)
      case EM_CR16:
      case EM_MICROBLAZE:
      case EM_MICROBLAZE_OLD:	return "Xilinx MicroBlaze";
@@ -10169,26 +9443,21 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
      case EM_RL78:		return "Renesas RL78";
      case EM_RX:			return "Renesas RX";
      case EM_METAG:		return "Imagination Technologies Meta processor architecture";
-@@ -2951,6 +2958,18 @@ get_machine_flags (unsigned e_flags, uns
+@@ -3193,6 +3200,13 @@ get_machine_flags (unsigned e_flags, uns
  	  decode_NDS32_machine_flags (e_flags, buf, sizeof buf);
  	  break;
  
 +	case EM_RISCV:
-+          {
-+	    if (e_flags & EF_RISCV_RVC)
-+	      strcat (buf, ", RVC");
-+
-+	    if (!EF_GET_RISCV_EXT (e_flags))
-+	      break;
-+	    strcat (buf, ", ");
-+	    strcat (buf, riscv_elf_flag_to_name (EF_GET_RISCV_EXT (e_flags)));
-+          }
++	  if (e_flags & EF_RISCV_RVC)
++	    strcat (buf, ", RVC");
++	  if (e_flags & EF_RISCV_SOFT_FLOAT)
++	    strcat (buf, ", soft-float ABI");
 +	  break;
 +
  	case EM_SH:
  	  switch ((e_flags & EF_SH_MACH_MASK))
  	    {
-@@ -10789,6 +10808,8 @@ is_32bit_abs_reloc (unsigned int reloc_t
+@@ -11430,6 +11444,8 @@ is_32bit_abs_reloc (unsigned int reloc_t
        return reloc_type == 1; /* R_PPC64_ADDR32.  */
      case EM_PPC:
        return reloc_type == 1; /* R_PPC_ADDR32.  */
@@ -10197,7 +9466,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
      case EM_RL78:
        return reloc_type == 1; /* R_RL78_DIR32.  */
      case EM_RX:
-@@ -10924,6 +10945,8 @@ is_64bit_abs_reloc (unsigned int reloc_t
+@@ -11576,6 +11592,8 @@ is_64bit_abs_reloc (unsigned int reloc_t
        return reloc_type == 80; /* R_PARISC_DIR64.  */
      case EM_PPC64:
        return reloc_type == 38; /* R_PPC64_ADDR64.  */
@@ -10206,60 +9475,48 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
      case EM_SPARC32PLUS:
      case EM_SPARCV9:
      case EM_SPARC:
-@@ -11072,6 +11095,7 @@ is_none_reloc (unsigned int reloc_type)
+@@ -11730,6 +11748,7 @@ is_none_reloc (unsigned int reloc_type)
      case EM_ADAPTEVA_EPIPHANY:
      case EM_PPC:     /* R_PPC_NONE.  */
      case EM_PPC64:   /* R_PPC64_NONE.  */
 +    case EM_RISCV:   /* R_RISCV_NONE.  */
-     case EM_ARM:     /* R_ARM_NONE.  */
-     case EM_IA_64:   /* R_IA64_NONE.  */
-     case EM_SH:      /* R_SH_NONE.  */
---- original-binutils/config.sub
-+++ binutils-2.25/config.sub
-@@ -335,6 +335,9 @@ case $basic_machine in
- 	ms1)
- 		basic_machine=mt-unknown
- 		;;
-+	riscv)
-+		basic_machine=riscv-ucb
-+		;;
- 
- 	strongarm | thumb | xscale)
- 		basic_machine=arm-unknown
---- original-binutils/gas/configure.ac
-+++ binutils-2.25/gas/configure.ac
-@@ -453,7 +453,7 @@ changequote([,])dnl
- 	AC_MSG_RESULT($enable_audio_ext)
+     case EM_ARC:     /* R_ARC_NONE.  */
+     case EM_ARC_COMPACT: /* R_ARC_NONE.  */
+     case EM_ARC_COMPACT2: /* R_ARC_NONE.  */
+--- original-binutils/gas/configure
++++ binutils-2.26/gas/configure
+@@ -12418,7 +12418,7 @@ $as_echo "#define NDS32_DEFAULT_AUDIO_EX
+ $as_echo "$enable_audio_ext" >&6; }
  	;;
  
 -      i386 | s390 | sparc)
 +      i386 | riscv | s390 | sparc)
  	if test $this_target = $target ; then
- 	  AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
- 	fi
---- original-binutils/gas/configure
-+++ binutils-2.25/gas/configure
-@@ -12402,7 +12402,7 @@ $as_echo "#define NDS32_DEFAULT_AUDIO_EXT 1" >>confdefs.h
- $as_echo "$enable_audio_ext" >&6; }
+ 
+ cat >>confdefs.h <<_ACEOF
+--- original-binutils/gas/configure.ac
++++ binutils-2.26/gas/configure.ac
+@@ -466,7 +466,7 @@ changequote([,])dnl
+ 	AC_MSG_RESULT($enable_audio_ext)
  	;;
  
 -      i386 | s390 | sparc)
 +      i386 | riscv | s390 | sparc)
  	if test $this_target = $target ; then
- 
- cat >>confdefs.h <<_ACEOF
+ 	  AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
+ 	fi
 --- original-binutils/gas/configure.tgt
-+++ binutils-2.25/gas/configure.tgt
-@@ -86,6 +86,8 @@ case ${cpu} in
++++ binutils-2.26/gas/configure.tgt
+@@ -87,6 +87,8 @@ case ${cpu} in
    pj*)			cpu_type=pj endian=big ;;
    powerpc*le*)		cpu_type=ppc endian=little ;;
    powerpc*)		cpu_type=ppc endian=big ;;
 +  riscv32*)		cpu_type=riscv endian=little arch=riscv32 ;;
-+  riscv*)		cpu_type=riscv endian=little arch=riscv64 ;;
++  riscv64*)		cpu_type=riscv endian=little arch=riscv64 ;;
    rs6000*)		cpu_type=ppc ;;
    rl78*)		cpu_type=rl78 ;;
    rx)			cpu_type=rx ;;
-@@ -384,6 +385,8 @@ case ${generic_target} in
+@@ -391,6 +393,8 @@ case ${generic_target} in
    ppc-*-kaos*)				fmt=elf ;;
    ppc-*-lynxos*)			fmt=elf em=lynx ;;
  
@@ -10268,7 +9525,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
    s390-*-linux-*)			fmt=elf em=linux ;;
    s390-*-tpf*)				fmt=elf ;;
  
-@@ -489,7 +490,7 @@ case ${generic_target} in
+@@ -488,7 +492,7 @@ case ${generic_target} in
  esac
  
  case ${cpu_type} in
@@ -10278,8 +9535,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
      ;;
  esac
 --- original-binutils/gas/Makefile.am
-+++ binutils-2.25/gas/Makefile.am
-@@ -171,6 +171,7 @@ TARGET_CPU_CFILES = \
++++ binutils-2.26/gas/Makefile.am
+@@ -177,6 +177,7 @@ TARGET_CPU_CFILES = \
  	config/tc-pdp11.c \
  	config/tc-pj.c \
  	config/tc-ppc.c \
@@ -10287,7 +9544,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	config/tc-rl78.c \
  	config/tc-rx.c \
  	config/tc-s390.c \
-@@ -242,6 +243,7 @@ TARGET_CPU_HFILES = \
+@@ -250,6 +251,7 @@ TARGET_CPU_HFILES = \
  	config/tc-pdp11.h \
  	config/tc-pj.h \
  	config/tc-ppc.h \
@@ -10296,8 +9553,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	config/tc-rx.h \
  	config/tc-s390.h \
 --- original-binutils/gas/Makefile.in
-+++ binutils-2.25/gas/Makefile.in
-@@ -440,6 +440,7 @@ TARGET_CPU_CFILES = \
++++ binutils-2.26/gas/Makefile.in
+@@ -448,6 +448,7 @@ TARGET_CPU_CFILES = \
  	config/tc-pdp11.c \
  	config/tc-pj.c \
  	config/tc-ppc.c \
@@ -10305,7 +9562,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	config/tc-rl78.c \
  	config/tc-rx.c \
  	config/tc-s390.c \
-@@ -511,6 +512,7 @@ TARGET_CPU_HFILES = \
+@@ -521,6 +522,7 @@ TARGET_CPU_HFILES = \
  	config/tc-pdp11.h \
  	config/tc-pj.h \
  	config/tc-ppc.h \
@@ -10313,7 +9570,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	config/tc-rl78.h \
  	config/tc-rx.h \
  	config/tc-s390.h \
-@@ -866,6 +868,7 @@ distclean-compile:
+@@ -878,6 +880,7 @@ distclean-compile:
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@
@@ -10321,7 +9578,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rl78.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-rx.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s390.Po@am__quote@
-@@ -1571,6 +1574,20 @@ tc-ppc.obj: config/tc-ppc.c
+@@ -1598,6 +1601,20 @@ tc-ppc.obj: config/tc-ppc.c
  @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
  @am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ppc.obj `if test -f 'config/tc-ppc.c'; then $(CYGPATH_W) 'config/tc-ppc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ppc.c'; fi`
  
@@ -10343,8 +9600,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  @am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-rl78.o -MD -MP -MF $(DEPDIR)/tc-rl78.Tpo -c -o tc-rl78.o `test -f 'config/tc-rl78.c' || echo '$(srcdir)/'`config/tc-rl78.c
  @am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/tc-rl78.Tpo $(DEPDIR)/tc-rl78.Po
 --- original-binutils/include/dis-asm.h
-+++ binutils-2.25/include/dis-asm.h
-@@ -254,6 +254,7 @@ extern int print_insn_little_arm	(bfd_vm
++++ binutils-2.26/include/dis-asm.h
+@@ -263,6 +263,7 @@ extern int print_insn_little_arm	(bfd_vm
  extern int print_insn_little_mips	(bfd_vma, disassemble_info *);
  extern int print_insn_little_nios2	(bfd_vma, disassemble_info *);
  extern int print_insn_little_powerpc	(bfd_vma, disassemble_info *);
@@ -10352,7 +9609,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  extern int print_insn_little_score      (bfd_vma, disassemble_info *); 
  extern int print_insn_lm32		(bfd_vma, disassemble_info *);
  extern int print_insn_m32c	        (bfd_vma, disassemble_info *);
-@@ -313,6 +314,7 @@ extern void print_aarch64_disassembler_o
+@@ -327,6 +328,7 @@ extern void print_aarch64_disassembler_o
  extern void print_i386_disassembler_options (FILE *);
  extern void print_mips_disassembler_options (FILE *);
  extern void print_ppc_disassembler_options (FILE *);
@@ -10361,33 +9618,33 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  extern void parse_arm_disassembler_option (char *);
  extern void print_s390_disassembler_options (FILE *);
 --- original-binutils/include/elf/common.h
-+++ binutils-2.25/include/elf/common.h
-@@ -301,6 +301,7 @@
- #define EM_INTEL207	207	/* Reserved by Intel */
- #define EM_INTEL208	208	/* Reserved by Intel */
- #define EM_INTEL209	209	/* Reserved by Intel */
-+#define EM_RISCV	243	/* Reserved by Intel */
++++ binutils-2.26/include/elf/common.h
+@@ -306,6 +306,7 @@
+ #define EM_VISIUM	221	/* Controls and Data Services VISIUMcore processor */
+ #define EM_FT32         222     /* FTDI Chip FT32 high performance 32-bit RISC architecture */
+ #define EM_MOXIE        223     /* Moxie processor family */
++#define EM_RISCV	243	/* RISC-V */
  
  /* If it is necessary to assign new unofficial EM_* values, please pick large
     random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
 --- original-binutils/ld/configure.tgt
-+++ binutils-2.25/ld/configure.tgt
-@@ -604,6 +604,12 @@ powerpc-*-aix*)		targ_emul=aixppc ;;
++++ binutils-2.26/ld/configure.tgt
+@@ -638,6 +638,12 @@ powerpc-*-aix*)		targ_emul=aixppc ;;
  powerpc-*-beos*)	targ_emul=aixppc ;;
  powerpc-*-windiss*)	targ_emul=elf32ppcwindiss ;;
  powerpc-*-lynxos*)	targ_emul=ppclynx ;;
 +riscv32*-*-*)		targ_emul=elf32lriscv
 +			targ_extra_emuls="elf64lriscv"
 +			targ_extra_libpath=$targ_extra_emuls ;;
-+riscv*-*-*)		targ_emul=elf64lriscv
++riscv64*-*-*)		targ_emul=elf64lriscv
 +			targ_extra_emuls="elf32lriscv"
 +			targ_extra_libpath=$targ_extra_emuls ;;
  rs6000-*-aix[5-9]*)	targ_emul=aix5rs6 ;;
  rs6000-*-aix*)		targ_emul=aixrs6
  			;;
 --- original-binutils/ld/Makefile.am
-+++ binutils-2.25/ld/Makefile.am
-@@ -258,6 +258,7 @@ ALL_EMULATION_SOURCES = \
++++ binutils-2.26/ld/Makefile.am
+@@ -267,6 +267,7 @@ ALL_EMULATION_SOURCES = \
  	eelf32ppcsim.c \
  	eelf32ppcvxworks.c \
  	eelf32ppcwindiss.c \
@@ -10395,7 +9652,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	eelf32rl78.c \
  	eelf32rx.c \
  	eelf32tilegx.c \
-@@ -464,6 +465,7 @@ ALL_64_EMULATION_SOURCES = \
+@@ -483,6 +484,7 @@ ALL_64_EMULATION_SOURCES = \
  	eelf64btsmip_fbsd.c \
  	eelf64hppa.c \
  	eelf64lppc.c \
@@ -10403,8 +9660,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	eelf64ltsmip.c \
  	eelf64ltsmip_fbsd.c \
  	eelf64mmix.c \
-@@ -1104,6 +1106,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/el
-   ldemul-list.h \
+@@ -1144,6 +1146,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/el
+   $(srcdir)/emultempl/ppc32elf.em ldemul-list.h \
    $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
  
 +eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
@@ -10415,7 +9672,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
    $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
    $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
-@@ -1861,6 +1868,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64
+@@ -1937,6 +1944,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64
    ldemul-list.h \
    $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
  
@@ -10429,8 +9686,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
    $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
    $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \
 --- original-binutils/ld/Makefile.in
-+++ binutils-2.25/ld/Makefile.in
-@@ -546,6 +546,7 @@ ALL_EMULATION_SOURCES = \
++++ binutils-2.26/ld/Makefile.in
+@@ -577,6 +577,7 @@ ALL_EMULATION_SOURCES = \
  	eelf32lppclinux.c \
  	eelf32lppcnto.c \
  	eelf32lppcsim.c \
@@ -10438,7 +9695,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	eelf32m32c.c \
  	eelf32mb_linux.c \
  	eelf32mbel_linux.c \
-@@ -771,6 +772,7 @@ ALL_64_EMULATION_SOURCES = \
+@@ -812,6 +813,7 @@ ALL_64_EMULATION_SOURCES = \
  	eelf64btsmip_fbsd.c \
  	eelf64hppa.c \
  	eelf64lppc.c \
@@ -10446,7 +9703,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	eelf64ltsmip.c \
  	eelf64ltsmip_fbsd.c \
  	eelf64mmix.c \
-@@ -1157,6 +1159,7 @@ distclean-compile:
+@@ -1219,6 +1221,7 @@ distclean-compile:
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppclinux.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcnto.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lppcsim.Po@am__quote@
@@ -10454,7 +9711,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900n32.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lsmip.Po@am__quote@
-@@ -1211,6 +1214,7 @@ distclean-compile:
+@@ -1274,6 +1277,7 @@ distclean-compile:
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@
@@ -10462,8 +9719,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Po@am__quote@
  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@
-@@ -2545,6 +2549,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/el
-   ldemul-list.h \
+@@ -2650,6 +2654,11 @@ eelf32lppcsim.c: $(srcdir)/emulparams/el
+   $(srcdir)/emultempl/ppc32elf.em ldemul-list.h \
    $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
  
 +eelf32lriscv.c: $(srcdir)/emulparams/elf32lriscv.sh \
@@ -10474,7 +9731,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \
    $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \
    $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \
-@@ -3302,6 +3311,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64
+@@ -3443,6 +3452,12 @@ eelf64lppc.c: $(srcdir)/emulparams/elf64
    ldemul-list.h \
    $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
  
@@ -10488,8 +9745,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
    $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \
    $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \
 --- original-binutils/opcodes/configure
-+++ binutils-2.25/opcodes/configure
-@@ -12590,6 +12590,7 @@ if test x${all_targets} = xfalse ; then
++++ binutils-2.26/opcodes/configure
+@@ -12603,6 +12603,7 @@ if test x${all_targets} = xfalse ; then
  	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
  	bfd_powerpc_64_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
  	bfd_pyramid_arch)	;;
@@ -10498,8 +9755,8 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  	bfd_rs6000_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
  	bfd_rl78_arch)		ta="$ta rl78-dis.lo rl78-decode.lo";;
 --- original-binutils/opcodes/disassemble.c
-+++ binutils-2.25/opcodes/disassemble.c
-@@ -373,6 +373,11 @@ disassembler (abfd)
++++ binutils-2.26/opcodes/disassemble.c
+@@ -376,6 +376,11 @@ disassembler (abfd)
  	disassemble = print_insn_little_powerpc;
        break;
  #endif
@@ -10511,7 +9768,7 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  #ifdef ARCH_rs6000
      case bfd_arch_rs6000:
        if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
-@@ -545,6 +550,9 @@ disassembler_usage (stream)
+@@ -558,6 +563,9 @@ disassembler_usage (stream)
  #ifdef ARCH_powerpc
    print_ppc_disassembler_options (stream);
  #endif
@@ -10521,21 +9778,3 @@ diff -urN empty/opcodes/riscv-opc.c binutils-2.25/opcodes/riscv-opc.c
  #ifdef ARCH_i386
    print_i386_disassembler_options (stream);
  #endif
---- original-binutils/bfd/Makefile.in	2014-10-14 00:32:02.000000000 -0700
-+++ binutils-2.25/bfd/Makefile.in	2015-03-31 06:53:23.253426230 -0700
-@@ -442,6 +442,7 @@
- 	cpu-pj.lo \
- 	cpu-plugin.lo \
- 	cpu-powerpc.lo \
-+	cpu-riscv.lo \
- 	cpu-rs6000.lo \
- 	cpu-rl78.lo \
- 	cpu-rx.lo \
-@@ -526,6 +527,7 @@
- 	cpu-pj.c \
- 	cpu-plugin.c \
- 	cpu-powerpc.c \
-+	cpu-riscv.c \
- 	cpu-rs6000.c \
- 	cpu-rl78.c \
- 	cpu-rx.c \
diff --git a/util/crossgcc/patches/cfe-3.7.1.src_frontend.patch b/util/crossgcc/patches/cfe-3.8.0.src_frontend.patch
index 781878dc74..3b8e6b70b7 100644
--- a/util/crossgcc/patches/cfe-3.7.1.src_frontend.patch
+++ b/util/crossgcc/patches/cfe-3.8.0.src_frontend.patch
@@ -5,8 +5,8 @@ https://llvm.org/bugs/show_bug.cgi?id=21538
 Index: include/clang/Driver/Driver.h
 ===================================================================
 --- cfe-3.7.1.src/include/clang/Driver/Driver.h	(revision 211898)
-+++ cfe-3.7.1.src/include/clang/Driver/Driver.h	(working copy)
-@@ -325,6 +325,14 @@
++++ cfe-3.8.0.src/include/clang/Driver/Driver.h	(working copy)
+@@ -357,6 +357,14 @@
    // FIXME: This should be in CompilationInfo.
    std::string GetFilePath(const char *Name, const ToolChain &TC) const;
  
@@ -24,8 +24,8 @@ Index: include/clang/Driver/Driver.h
 Index: include/clang/Driver/Options.td
 ===================================================================
 --- cfe-3.7.1.src/include/clang/Driver/Options.td	(revision 211898)
-+++ cfe-3.7.1.src/include/clang/Driver/Options.td	(working copy)
-@@ -1269,6 +1269,8 @@
++++ cfe-3.8.0.src/include/clang/Driver/Options.td	(working copy)
+@@ -1669,6 +1669,8 @@
    HelpText<"Enable Objective-C Ivar layout bitmap print trace">;
  def print_libgcc_file_name : Flag<["-", "--"], "print-libgcc-file-name">,
    HelpText<"Print the library path for \"libgcc.a\"">;
@@ -37,8 +37,8 @@ Index: include/clang/Driver/Options.td
 Index: lib/Driver/Driver.cpp
 ===================================================================
 --- cfe-3.7.1.src/lib/Driver/Driver.cpp	(revision 211898)
-+++ cfe-3.7.1.src/lib/Driver/Driver.cpp	(working copy)
-@@ -756,6 +756,11 @@
++++ cfe-3.8.0.src/lib/Driver/Driver.cpp	(working copy)
+@@ -910,6 +910,11 @@
      return false;
    }
  
@@ -48,10 +48,10 @@ Index: lib/Driver/Driver.cpp
 +  }
 +
    if (C.getArgs().hasArg(options::OPT_print_multi_lib)) {
-     const MultilibSet &Multilibs = TC.getMultilibs();
- 
-@@ -1820,6 +1825,26 @@
-   return Name;
+     for (const Multilib &Multilib : TC.getMultilibs())
+       llvm::outs() << Multilib << "\n";
+@@ -2153,6 +2158,26 @@
+   return false;
  }
  
 +std::string Driver::GetCompilerRTPath(const ToolChain &TC) const {
@@ -76,4 +76,4 @@ Index: lib/Driver/Driver.cpp
 +
  std::string Driver::GetProgramPath(const char *Name,
                                     const ToolChain &TC) const {
-   // FIXME: Needs a better variable than DefaultTargetTriple
+   SmallVector<std::string, 2> TargetSpecificExecutables;
diff --git a/util/crossgcc/patches/gcc-5.2.0_elf_biarch.patch b/util/crossgcc/patches/gcc-5.3.0_elf_biarch.patch
index 196081601c..574e151c2c 100644
--- a/util/crossgcc/patches/gcc-5.2.0_elf_biarch.patch
+++ b/util/crossgcc/patches/gcc-5.3.0_elf_biarch.patch
@@ -1,6 +1,6 @@
 diff -urN gcc-4.9.2/gcc/config/i386/t-elf64 gcc-4.9.2/gcc/config/i386/t-elf64
 --- gcc-4.9.2/gcc/config/i386/t-elf64	1969-12-31 16:00:00.000000000 -0800
-+++ gcc-5.2.0/gcc/config/i386/t-elf64	2015-06-17 11:20:08.032513005 -0700
++++ gcc-5.3.0/gcc/config/i386/t-elf64	2015-06-17 11:20:08.032513005 -0700
 @@ -0,0 +1,38 @@
 +# Copyright (C) 2002-2014 Free Software Foundation, Inc.
 +#
@@ -42,7 +42,7 @@ diff -urN gcc-4.9.2/gcc/config/i386/t-elf64 gcc-4.9.2/gcc/config/i386/t-elf64
 +MULTILIB_OSDIRNAMES+= mx32=../libx32$(call if_multiarch,:x86_64-elf-x32)
 diff -urN gcc-4.9.2/gcc/config.gcc gcc-4.9.2/gcc/config.gcc
 --- gcc-4.9.2/gcc/config.gcc	2015-06-17 11:20:57.841008182 -0700
-+++ gcc-5.2.0/gcc/config.gcc	2015-06-17 11:17:24.818890200 -0700
++++ gcc-5.3.0/gcc/config.gcc	2015-06-17 11:17:24.818890200 -0700
 @@ -1353,6 +1353,30 @@
  	;;
  x86_64-*-elf*)
@@ -74,8 +74,8 @@ diff -urN gcc-4.9.2/gcc/config.gcc gcc-4.9.2/gcc/config.gcc
  	;;
  i[34567]86-*-rdos*)
      tm_file="${tm_file} i386/unix.h i386/att.h dbxelf.h elfos.h newlib-stdint.h i386/i386elf.h i386/rdos.h"
---- gcc-5.2.0/gcc/config/i386/x86-64.h.orig	2015-08-20 17:17:34.555919593 +0200
-+++ gcc-5.2.0/gcc/config/i386/x86-64.h	2015-08-20 17:17:42.615908670 +0200
+--- gcc-5.3.0/gcc/config/i386/x86-64.h.orig	2015-08-20 17:17:34.555919593 +0200
++++ gcc-5.3.0/gcc/config/i386/x86-64.h	2015-08-20 17:17:42.615908670 +0200
 @@ -49,7 +49,7 @@
  #define WCHAR_TYPE_SIZE 32
  
diff --git a/util/crossgcc/patches/gcc-5.2.0_gnat.patch b/util/crossgcc/patches/gcc-5.3.0_gnat.patch
index 1e0a5bbbff..167d118975 100644
--- a/util/crossgcc/patches/gcc-5.2.0_gnat.patch
+++ b/util/crossgcc/patches/gcc-5.3.0_gnat.patch
@@ -1,5 +1,5 @@
---- gcc-5.2.0/gcc/ada/gcc-interface/Make-lang.in.bak	2015-08-24 16:23:25.004493665 +0200
-+++ gcc-5.2.0/gcc/ada/gcc-interface/Make-lang.in	2015-08-24 17:53:52.496636113 +0200
+--- gcc-5.3.0/gcc/ada/gcc-interface/Make-lang.in.bak	2015-08-24 16:23:25.004493665 +0200
++++ gcc-5.3.0/gcc/ada/gcc-interface/Make-lang.in	2015-08-24 17:53:52.496636113 +0200
 @@ -45,7 +45,7 @@
  
  
diff --git a/util/crossgcc/patches/gcc-5.2.0_libgcc.patch b/util/crossgcc/patches/gcc-5.3.0_libgcc.patch
index b844802801..fd4b2545db 100644
--- a/util/crossgcc/patches/gcc-5.2.0_libgcc.patch
+++ b/util/crossgcc/patches/gcc-5.3.0_libgcc.patch
@@ -1,6 +1,6 @@
 diff -urN gcc-5.2.0.orig/libgcc/config/t-hardfp gcc-5.2.0/libgcc/config/t-hardfp
 --- gcc-5.2.0.orig/libgcc/config/t-hardfp	2015-01-05 04:33:28.000000000 -0800
-+++ gcc-5.2.0/libgcc/config/t-hardfp	2016-04-06 12:04:51.000000000 -0700
++++ gcc-5.3.0/libgcc/config/t-hardfp	2016-04-06 12:04:51.000000000 -0700
 @@ -59,21 +59,52 @@
  
  hardfp_func_list := $(filter-out $(hardfp_exclusions),$(hardfp_func_list))
diff --git a/util/crossgcc/patches/gcc-5.2.0_nds32.patch b/util/crossgcc/patches/gcc-5.3.0_nds32.patch
index 3b772fa7d3..34f2573cfe 100644
--- a/util/crossgcc/patches/gcc-5.2.0_nds32.patch
+++ b/util/crossgcc/patches/gcc-5.3.0_nds32.patch
@@ -1,6 +1,6 @@
-diff -urN gcc-5.2.0.orig/gcc/config/nds32/nds32.md gcc-5.2.0/gcc/config/nds32/nds32.md
---- gcc-5.2.0.orig/gcc/config/nds32/nds32.md	2015-01-15 22:45:09.000000000 -0800
-+++ gcc-5.2.0/gcc/config/nds32/nds32.md	2016-04-14 22:09:09.000000000 -0700
+diff -urN gcc-5.3.0.orig/gcc/config/nds32/nds32.md gcc-5.3.0/gcc/config/nds32/nds32.md
+--- gcc-5.3.0.orig/gcc/config/nds32/nds32.md	2015-01-15 22:45:09.000000000 -0800
++++ gcc-5.3.0/gcc/config/nds32/nds32.md	2016-04-14 22:09:09.000000000 -0700
 @@ -2289,11 +2289,11 @@
    emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
  				  operands[4]));
diff --git a/util/crossgcc/patches/gcc-5.2.0_riscv.patch b/util/crossgcc/patches/gcc-5.3.0_riscv.patch
index 55ad1895e5..7e2e828325 100644
--- a/util/crossgcc/patches/gcc-5.2.0_riscv.patch
+++ b/util/crossgcc/patches/gcc-5.3.0_riscv.patch
@@ -1,17 +1,5 @@
---- original-gcc/config.sub
-+++ gcc-5.2.0/config.sub
-@@ -340,6 +340,9 @@ case $basic_machine in
- 	ms1)
- 		basic_machine=mt-unknown
- 		;;
-+	riscv)
-+		basic_machine=riscv-ucb
-+		;;
- 
- 	strongarm | thumb | xscale)
- 		basic_machine=arm-unknown
 --- original-gcc/gcc/config.gcc
-+++ gcc-5.2.0/gcc/config.gcc
++++ gcc-5.3.0/gcc/config.gcc
 @@ -439,6 +439,10 @@ powerpc*-*-*)
  	esac
  	extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
@@ -23,25 +11,32 @@
  rs6000*-*-*)
  	extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
  	;;
-@@ -1976,6 +1980,27 @@ microblaze*-*-elf)
+@@ -1982,6 +1986,34 @@ microblaze*-*-elf)
  	cxx_target_objs="${cxx_target_objs} microblaze-c.o"
  	tmake_file="${tmake_file} microblaze/t-microblaze"
          ;;
-+riscv32*-*-linux*)				# Linux RISC-V
++riscv32*-*-linux*)
 +	tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h riscv/default-32.h ${tm_file} riscv/linux.h riscv/linux64.h"
 +	tmake_file="${tmake_file} riscv/t-linux64"
 +	gnu_ld=yes
 +	gas=yes
 +	gcc_cv_initfini_array=yes
 +	;;
-+riscv*-*-linux*)				# Linux RISC-V
++riscv*-*-linux*)
 +	tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} riscv/linux.h riscv/linux64.h"
 +	tmake_file="${tmake_file} riscv/t-linux64"
 +	gnu_ld=yes
 +	gas=yes
 +	gcc_cv_initfini_array=yes
 +	;;
-+riscv*-*-elf*)				# Linux RISC-V
++riscv32*-*-elf*)
++	tm_file="elfos.h newlib-stdint.h riscv/default-32.h ${tm_file} riscv/elf.h"
++	tmake_file="${tmake_file} riscv/t-elf"
++	gnu_ld=yes
++	gas=yes
++	gcc_cv_initfini_array=yes
++	;;
++riscv*-*-elf*)
 +	tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
 +	tmake_file="${tmake_file} riscv/t-elf"
 +	gnu_ld=yes
@@ -51,7 +46,7 @@
  mips*-*-netbsd*)			# NetBSD/mips, either endian.
  	target_cpu_default="MASK_ABICALLS"
  	tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h"
-@@ -3851,6 +3876,31 @@ case "${target}" in
+@@ -3866,6 +3898,31 @@ case "${target}" in
  		done
  		;;
  
@@ -84,8 +79,8 @@
  		supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci"
  
 --- original-gcc/gcc/configure
-+++ gcc-5.2.0/gcc/configure
-@@ -23708,6 +23708,25 @@ x3:	.space 4
++++ gcc-5.3.0/gcc/configure
+@@ -23717,6 +23717,25 @@ x3:	.space 4
  	tls_first_minor=14
  	tls_as_opt="-a32 --fatal-warnings"
  	;;
@@ -112,7 +107,7 @@
      conftest_s='
  	.section ".tdata","awT",@progbits
 --- original-gcc/gcc/configure.ac
-+++ gcc-5.2.0/gcc/configure.ac
++++ gcc-5.3.0/gcc/configure.ac
 @@ -3263,6 +3263,25 @@ x3:	.space 4
  	tls_first_minor=14
  	tls_as_opt="-a32 --fatal-warnings"
@@ -140,7 +135,7 @@
      conftest_s='
  	.section ".tdata","awT",@progbits
 --- original-gcc/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
-+++ gcc-5.2.0/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
++++ gcc-5.3.0/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
 @@ -6,6 +6,9 @@
  #elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) || defined (__POWERPC__) || defined (__ppc)
    /* On PPC division by zero does not trap.  */
@@ -152,7 +147,7 @@
    /* On SPU division by zero does not trap.  */
  # define DO_TEST 0
 --- original-gcc/gcc/testsuite/gcc.dg/20020312-2.c
-+++ gcc-5.2.0/gcc/testsuite/gcc.dg/20020312-2.c
++++ gcc-5.3.0/gcc/testsuite/gcc.dg/20020312-2.c
 @@ -66,6 +66,8 @@ extern void abort (void);
  # else
  #  define PIC_REG  "30"
@@ -163,7 +158,7 @@
  /* No pic register.  */
  #elif defined(__s390__)
 --- original-gcc/gcc/testsuite/gcc.dg/20040813-1.c
-+++ gcc-5.2.0/gcc/testsuite/gcc.dg/20040813-1.c
++++ gcc-5.3.0/gcc/testsuite/gcc.dg/20040813-1.c
 @@ -2,7 +2,7 @@
  /* Contributed by Devang Patel  <dpatel@apple.com>  */
  
@@ -174,7 +169,7 @@
  
  int
 --- original-gcc/gcc/testsuite/gcc.dg/stack-usage-1.c
-+++ gcc-5.2.0/gcc/testsuite/gcc.dg/stack-usage-1.c
++++ gcc-5.3.0/gcc/testsuite/gcc.dg/stack-usage-1.c
 @@ -61,6 +61,8 @@
  #  else
  #    define SIZE 240
@@ -185,7 +180,7 @@
  #  define SIZE 254
  #elif defined (__s390x__)
 --- original-gcc/libatomic/configure.tgt
-+++ gcc-5.2.0/libatomic/configure.tgt
++++ gcc-5.3.0/libatomic/configure.tgt
 @@ -33,6 +33,7 @@ case "${target_cpu}" in
  	ARCH=alpha
  	;;
@@ -195,7 +190,7 @@
  
    arm*)
 --- original-gcc/libgcc/config.host
-+++ gcc-5.2.0/libgcc/config.host
++++ gcc-5.3.0/libgcc/config.host
 @@ -167,6 +167,9 @@ powerpc*-*-*)
  	;;
  rs6000*-*-*)
@@ -206,27 +201,23 @@
  sparc64*-*-*)
  	cpu_type=sparc
  	;;
-@@ -1057,6 +1060,18 @@ powerpcle-*-eabi*)
+@@ -1064,6 +1067,14 @@ powerpcle-*-eabi*)
  	tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-crtstuff t-crtstuff-pic t-fdpbit"
  	extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o"
  	;;
-+riscv32*-*-linux*)
-+	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-elf riscv/t-elf32"
-+	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o crtbeginT.o"
-+	;;
 +riscv*-*-linux*)
-+	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-elf"
++	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-tpbit riscv/t-elf riscv/t-elf${host_address}"
 +	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o crtbeginT.o"
 +	;;
 +riscv*-*-*)
-+	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-elf"
++	tmake_file="${tmake_file} riscv/t-fpbit riscv/t-dpbit riscv/t-elf riscv/t-elf${host_address}"
 +	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
 +	;;
  rs6000-ibm-aix4.[3456789]* | powerpc-ibm-aix4.[3456789]*)
  	md_unwind_header=rs6000/aix-unwind.h
  	tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix rs6000/t-ibm-ldouble"
 --- original-gcc/libsanitizer/asan/asan_linux.cc
-+++ gcc-5.2.0/libsanitizer/asan/asan_linux.cc
++++ gcc-5.3.0/libsanitizer/asan/asan_linux.cc
 @@ -213,6 +213,11 @@ void GetPcSpBp(void *context, uptr *pc,
    *pc = ucontext->uc_mcontext.gregs[31];
    *bp = ucontext->uc_mcontext.gregs[30];
@@ -240,7 +231,7 @@
  # error "Unsupported arch"
  #endif
 --- original-gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
-+++ gcc-5.2.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
++++ gcc-5.3.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
 @@ -61,7 +61,8 @@ namespace __sanitizer {
  }  // namespace __sanitizer
  
@@ -252,7 +243,7 @@
  #endif
  
 --- original-gcc/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
-+++ gcc-5.2.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
++++ gcc-5.3.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
 @@ -72,6 +72,10 @@ namespace __sanitizer {
    const unsigned struct_kernel_stat_sz = 144;
    #endif
@@ -275,7 +266,7 @@
  #else
 diff -ru gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform.h gcc-5.1.0/libsanitizer/sanitizer_common/sanitizer_platform.h
 --- gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform.h	2015-05-13 19:36:27.061421043 -0700
-+++ gcc-5.2.0/libsanitizer/sanitizer_common/sanitizer_platform.h	2015-05-13 19:44:19.274355577 -0700
++++ gcc-5.3.0/libsanitizer/sanitizer_common/sanitizer_platform.h	2015-05-13 19:44:19.274355577 -0700
 @@ -98,9 +98,9 @@
  
  // The AArch64 linux port uses the canonical syscall set as mandated by
@@ -290,7 +281,7 @@ diff -ru gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform.h gcc-5
  # define SANITIZER_USES_CANONICAL_LINUX_SYSCALLS 0
 diff -ru gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h gcc-5.1.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
 --- gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	2015-05-13 19:36:27.061421043 -0700
-+++ gcc-5.2.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	2015-05-13 19:39:13.515487834 -0700
++++ gcc-5.3.0/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h	2015-05-13 19:39:13.515487834 -0700
 @@ -73,7 +73,6 @@
    #endif
    const unsigned struct_kernel_stat64_sz = 104;
@@ -308,10 +299,34 @@ diff -ru gcc-5.1.0.orig/libsanitizer/sanitizer_common/sanitizer_platform_limits_
    const unsigned struct___old_kernel_stat_sz = 0;
  #elif !defined(__sparc__)
    const unsigned struct___old_kernel_stat_sz = 32;
-diff -urN empty/gcc/common/config/riscv/riscv-common.c gcc-5.2.0/gcc/common/config/riscv/riscv-common.c
---- gcc-5.2.0/gcc/common/config/riscv/riscv-common.c	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/common/config/riscv/riscv-common.c	2015-07-17 22:36:52.315705931 +0200
-@@ -0,0 +1,140 @@
+--- original-gcc/libstdc++-v3/configure
++++ gcc-5.3.0/libstdc++-v3/configure
+@@ -16646,7 +16646,7 @@ ac_compiler_gnu=$ac_cv_cxx_compiler_gnu
+   # Long term, -std=c++0x could be even better, could manage to explicitly
+   # request C99 facilities to the underlying C headers.
+   ac_save_CXXFLAGS="$CXXFLAGS"
+-  CXXFLAGS="$CXXFLAGS -std=c++98"
++  CXXFLAGS="$CXXFLAGS -std=gnu++98"
+   ac_save_LIBS="$LIBS"
+   ac_save_gcc_no_link="$gcc_no_link"
+ 
+@@ -17268,9 +17268,11 @@ rm -f core conftest.err conftest.$ac_obj
+ $as_echo "$glibcxx_cv_c99_wchar" >&6; }
+   fi
+ 
++  # For newlib, don't check complex since missing c99 functions, but
++  #   rest of c99 stuff is there so don't loose it
+   # Option parsed, now set things appropriately.
+   if test x"$glibcxx_cv_c99_math" = x"no" ||
+-     test x"$glibcxx_cv_c99_complex" = x"no" ||
++     # test x"$glibcxx_cv_c99_complex" = x"no" ||
+      test x"$glibcxx_cv_c99_stdio" = x"no" ||
+      test x"$glibcxx_cv_c99_stdlib" = x"no" ||
+      test x"$glibcxx_cv_c99_wchar" = x"no"; then
+diff -urN empty/gcc/common/config/riscv/riscv-common.c gcc-5.3.0/gcc/common/config/riscv/riscv-common.c
+--- empty/gcc/common/config/riscv/riscv-common.c	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/common/config/riscv/riscv-common.c	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,139 @@
 +/* Common hooks for RISC-V.
 +   Copyright (C) 1989-2014 Free Software Foundation, Inc.
 +
@@ -435,7 +450,6 @@ diff -urN empty/gcc/common/config/riscv/riscv-common.c gcc-5.2.0/gcc/common/conf
 +  {
 +    { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
 +    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
-+    { OPT_LEVELS_SIZE, OPT_msave_restore, NULL, 1 },
 +    { OPT_LEVELS_NONE, 0, NULL, 0 }
 +  };
 +
@@ -452,10 +466,10 @@ diff -urN empty/gcc/common/config/riscv/riscv-common.c gcc-5.2.0/gcc/common/conf
 +#define TARGET_HANDLE_OPTION riscv_handle_option
 +
 +struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
-diff -urN empty/gcc/config/riscv/constraints.md gcc-5.2.0/gcc/config/riscv/constraints.md
---- gcc-5.2.0/gcc/config/riscv/constraints.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/constraints.md	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,90 @@
+diff -urN empty/gcc/config/riscv/constraints.md gcc-5.3.0/gcc/config/riscv/constraints.md
+--- empty/gcc/config/riscv/constraints.md	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/constraints.md	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,93 @@
 +;; Constraint definitions for RISC-V target.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -488,6 +502,9 @@ diff -urN empty/gcc/config/riscv/constraints.md gcc-5.2.0/gcc/config/riscv/const
 +(define_register_constraint "j" "T_REGS"
 +  "@internal")
 +
++(define_register_constraint "l" "JALR_REGS"
++  "@internal")
++
 +;; Integer constraints
 +
 +(define_constraint "Z"
@@ -546,9 +563,9 @@ diff -urN empty/gcc/config/riscv/constraints.md gcc-5.2.0/gcc/config/riscv/const
 +   A vector zero."
 +  (and (match_code "const_vector")
 +       (match_test "op == CONST0_RTX (mode)")))
-diff -urN empty/gcc/config/riscv/default-32.h gcc-5.2.0/gcc/config/riscv/default-32.h
---- gcc-5.2.0/gcc/config/riscv/default-32.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/default-32.h	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/gcc/config/riscv/default-32.h gcc-5.3.0/gcc/config/riscv/default-32.h
+--- empty/gcc/config/riscv/default-32.h	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/default-32.h	2016-04-02 14:07:12.469104719 +0800
 @@ -0,0 +1,22 @@
 +/* Definitions of target machine for GCC, for RISC-V,
 +   defaulting to 32-bit code generation.
@@ -572,9 +589,9 @@ diff -urN empty/gcc/config/riscv/default-32.h gcc-5.2.0/gcc/config/riscv/default
 +<http://www.gnu.org/licenses/>.  */
 +
 +#define TARGET_64BIT_DEFAULT 0
-diff -urN empty/gcc/config/riscv/elf.h gcc-5.2.0/gcc/config/riscv/elf.h
---- gcc-5.2.0/gcc/config/riscv/elf.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/elf.h	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/gcc/config/riscv/elf.h gcc-5.3.0/gcc/config/riscv/elf.h
+--- empty/gcc/config/riscv/elf.h	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/elf.h	2016-04-02 14:07:12.469104719 +0800
 @@ -0,0 +1,31 @@
 +/* Target macros for riscv*-elf targets.
 +   Copyright (C) 1994, 1997, 1999, 2000, 2002, 2003, 2004, 2007, 2010
@@ -607,10 +624,10 @@ diff -urN empty/gcc/config/riscv/elf.h gcc-5.2.0/gcc/config/riscv/elf.h
 +#define ENDFILE_SPEC "crtend%O%s"
 +
 +#define NO_IMPLICIT_EXTERN_C 1
-diff -urN empty/gcc/config/riscv/generic.md gcc-5.2.0/gcc/config/riscv/generic.md
---- gcc-5.2.0/gcc/config/riscv/generic.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/generic.md	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,98 @@
+diff -urN empty/gcc/config/riscv/generic.md gcc-5.3.0/gcc/config/riscv/generic.md
+--- empty/gcc/config/riscv/generic.md	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/generic.md	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,78 @@
 +;; Generic DFA-based pipeline description for RISC-V targets.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -633,85 +650,112 @@ diff -urN empty/gcc/config/riscv/generic.md gcc-5.2.0/gcc/config/riscv/generic.m
 +;; <http://www.gnu.org/licenses/>.
 +
 +
-+;; This file is derived from the old define_function_unit description.
-+;; Each reservation can be overridden on a processor-by-processor basis.
++(define_automaton "pipe0")
++(define_cpu_unit "alu" "pipe0")
++(define_cpu_unit "imuldiv" "pipe0")
++(define_cpu_unit "fdivsqrt" "pipe0")
 +
 +(define_insn_reservation "generic_alu" 1
 +  (eq_attr "type" "unknown,const,arith,shift,slt,multi,nop,logical,move")
 +  "alu")
 +
 +(define_insn_reservation "generic_load" 3
-+  (eq_attr "type" "load,fpload,fpidxload")
++  (eq_attr "type" "load,fpload")
 +  "alu")
 +
 +(define_insn_reservation "generic_store" 1
-+  (eq_attr "type" "store,fpstore,fpidxstore")
++  (eq_attr "type" "store,fpstore")
 +  "alu")
 +
-+(define_insn_reservation "generic_xfer" 2
-+  (eq_attr "type" "mfc,mtc")
++(define_insn_reservation "generic_xfer" 3
++  (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp")
 +  "alu")
 +
 +(define_insn_reservation "generic_branch" 1
 +  (eq_attr "type" "branch,jump,call")
 +  "alu")
 +
-+(define_insn_reservation "generic_imul" 17
++(define_insn_reservation "generic_imul" 10
 +  (eq_attr "type" "imul")
-+  "imuldiv*17")
++  "imuldiv*10")
 +
-+(define_insn_reservation "generic_idiv" 38
-+  (eq_attr "type" "idiv")
-+  "imuldiv*38")
++(define_insn_reservation "generic_idivsi" 34
++  (and (eq_attr "type" "idiv")
++       (eq_attr "mode" "SI"))
++  "imuldiv*34")
 +
-+(define_insn_reservation "generic_fcvt" 1
-+  (eq_attr "type" "fcvt")
-+  "alu")
++(define_insn_reservation "generic_idivdi" 66
++  (and (eq_attr "type" "idiv")
++       (eq_attr "mode" "DI"))
++  "imuldiv*66")
 +
-+(define_insn_reservation "generic_fmove" 2
-+  (eq_attr "type" "fmove")
++(define_insn_reservation "generic_fmul_single" 5
++  (and (eq_attr "type" "fadd,fmul,fmadd")
++       (eq_attr "mode" "SF"))
 +  "alu")
 +
-+(define_insn_reservation "generic_fcmp" 3
-+  (eq_attr "type" "fcmp")
++(define_insn_reservation "generic_fmul_double" 7
++  (and (eq_attr "type" "fadd,fmul,fmadd")
++       (eq_attr "mode" "DF"))
 +  "alu")
 +
-+(define_insn_reservation "generic_fadd" 4
-+  (eq_attr "type" "fadd")
-+  "alu")
++(define_insn_reservation "generic_fdiv" 20
++  (eq_attr "type" "fdiv")
++  "fdivsqrt*20")
 +
-+(define_insn_reservation "generic_fmul_single" 7
-+  (and (eq_attr "type" "fmul,fmadd")
-+       (eq_attr "mode" "SF"))
-+  "alu")
++(define_insn_reservation "generic_fsqrt" 25
++  (eq_attr "type" "fsqrt")
++  "fdivsqrt*25")
+diff -urN empty/gcc/config/riscv/linux64.h gcc-5.3.0/gcc/config/riscv/linux64.h
+--- empty/gcc/config/riscv/linux64.h	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/linux64.h	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,43 @@
++/* Definitions for 64-bit RISC-V GNU/Linux systems with ELF format.
++   Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011
++   Free Software Foundation, Inc.
 +
-+(define_insn_reservation "generic_fmul_double" 8
-+  (and (eq_attr "type" "fmul,fmadd")
-+       (eq_attr "mode" "DF"))
-+  "alu")
++This file is part of GCC.
 +
-+(define_insn_reservation "generic_fdiv_single" 23
-+  (and (eq_attr "type" "fdiv")
-+       (eq_attr "mode" "SF"))
-+  "alu")
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
 +
-+(define_insn_reservation "generic_fdiv_double" 36
-+  (and (eq_attr "type" "fdiv")
-+       (eq_attr "mode" "DF"))
-+  "alu")
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
 +
-+(define_insn_reservation "generic_fsqrt_single" 54
-+  (and (eq_attr "type" "fsqrt")
-+       (eq_attr "mode" "SF"))
-+  "alu")
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
 +
-+(define_insn_reservation "generic_fsqrt_double" 112
-+  (and (eq_attr "type" "fsqrt")
-+       (eq_attr "mode" "DF"))
-+  "alu")
-diff -urN empty/gcc/config/riscv/linux.h gcc-5.2.0/gcc/config/riscv/linux.h
---- gcc-5.2.0/gcc/config/riscv/linux.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/linux.h	2015-07-17 22:36:52.319705931 +0200
++/* Force the default ABI flags onto the command line
++   in order to make the other specs easier to write.  */
++#undef LIB_SPEC
++#define LIB_SPEC "\
++%{pthread:-lpthread} \
++%{shared:-lc} \
++%{!shared: \
++  %{profile:-lc_p} %{!profile:-lc}}"
++
++#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1"
++
++#undef LINK_SPEC
++#define LINK_SPEC "\
++%{shared} \
++  %{!shared: \
++    %{!static: \
++      %{rdynamic:-export-dynamic} \
++      %{" OPT_ARCH64 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "} \
++      %{" OPT_ARCH32 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
++    %{static:-static}} \
++%{" OPT_ARCH64 ":-melf64lriscv} \
++%{" OPT_ARCH32 ":-melf32lriscv}"
+diff -urN empty/gcc/config/riscv/linux.h gcc-5.3.0/gcc/config/riscv/linux.h
+--- empty/gcc/config/riscv/linux.h	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/linux.h	2016-04-02 14:07:12.469104719 +0800
 @@ -0,0 +1,60 @@
 +/* Definitions for RISC-V GNU/Linux systems with ELF format.
 +   Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
@@ -773,210 +817,10 @@ diff -urN empty/gcc/config/riscv/linux.h gcc-5.2.0/gcc/config/riscv/linux.h
 +#undef  ENDFILE_SPEC
 +#define ENDFILE_SPEC \
 +   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
-diff -urN empty/gcc/config/riscv/linux64.h gcc-5.2.0/gcc/config/riscv/linux64.h
---- gcc-5.2.0/gcc/config/riscv/linux64.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/linux64.h	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,43 @@
-+/* Definitions for 64-bit RISC-V GNU/Linux systems with ELF format.
-+   Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011
-+   Free Software Foundation, Inc.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3.  If not see
-+<http://www.gnu.org/licenses/>.  */
-+
-+/* Force the default ABI flags onto the command line
-+   in order to make the other specs easier to write.  */
-+#undef LIB_SPEC
-+#define LIB_SPEC "\
-+%{pthread:-lpthread} \
-+%{shared:-lc} \
-+%{!shared: \
-+  %{profile:-lc_p} %{!profile:-lc}}"
-+
-+#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1"
-+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1"
-+
-+#undef LINK_SPEC
-+#define LINK_SPEC "\
-+%{shared} \
-+  %{!shared: \
-+    %{!static: \
-+      %{rdynamic:-export-dynamic} \
-+      %{" OPT_ARCH64 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER64 "} \
-+      %{" OPT_ARCH32 ": -dynamic-linker " GNU_USER_DYNAMIC_LINKER32 "}} \
-+    %{static:-static}} \
-+%{" OPT_ARCH64 ":-melf64lriscv} \
-+%{" OPT_ARCH32 ":-melf32lriscv}"
-diff -urN empty/gcc/config/riscv/opcode-riscv.h gcc-5.2.0/gcc/config/riscv/opcode-riscv.h
---- gcc-5.2.0/gcc/config/riscv/opcode-riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/opcode-riscv.h	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,149 @@
-+/* RISC-V ISA encoding.
-+   Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+   Based on MIPS target for GNU compiler.
-+
-+This file is part of GDB, GAS, and the GNU binutils.
-+
-+GDB, GAS, and the GNU binutils are free software; you can redistribute
-+them and/or modify them under the terms of the GNU General Public
-+License as published by the Free Software Foundation; either version
-+1, or (at your option) any later version.
-+
-+GDB, GAS, and the GNU binutils are distributed in the hope that they
-+will be useful, but WITHOUT ANY WARRANTY; without even the implied
-+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-+the GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with this file; see the file COPYING.  If not, write to the Free
-+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-+
-+#ifndef _RISCV_H_
-+#define _RISCV_H_
-+
-+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
-+#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
-+
-+#define EXTRACT_ITYPE_IMM(x) \
-+  (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
-+#define EXTRACT_STYPE_IMM(x) \
-+  (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
-+#define EXTRACT_SBTYPE_IMM(x) \
-+  ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
-+#define EXTRACT_UTYPE_IMM(x) \
-+  ((RV_X(x, 12, 20) << 20) | (RV_IMM_SIGN(x) << 32))
-+#define EXTRACT_UJTYPE_IMM(x) \
-+  ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
-+
-+#define ENCODE_ITYPE_IMM(x) \
-+  (RV_X(x, 0, 12) << 20)
-+#define ENCODE_STYPE_IMM(x) \
-+  ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
-+#define ENCODE_SBTYPE_IMM(x) \
-+  ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
-+#define ENCODE_UTYPE_IMM(x) \
-+  (RV_X(x, 12, 20) << 12)
-+#define ENCODE_UJTYPE_IMM(x) \
-+  ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
-+
-+#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
-+#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
-+#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
-+#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
-+#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
-+
-+#define RISCV_RTYPE(insn, rd, rs1, rs2) \
-+  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
-+#define RISCV_ITYPE(insn, rd, rs1, imm) \
-+  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
-+#define RISCV_STYPE(insn, rs1, rs2, imm) \
-+  ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
-+#define RISCV_SBTYPE(insn, rs1, rs2, target) \
-+  ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
-+#define RISCV_UTYPE(insn, rd, bigimm) \
-+  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
-+#define RISCV_UJTYPE(insn, rd, target) \
-+  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
-+
-+#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
-+
-+#define RISCV_CONST_HIGH_PART(VALUE) \
-+  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
-+#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
-+
-+/* RV fields */
-+
-+#define OP_MASK_OP		0x7f
-+#define OP_SH_OP		0
-+#define OP_MASK_RS2		0x1f
-+#define OP_SH_RS2		20
-+#define OP_MASK_RS1		0x1f
-+#define OP_SH_RS1		15
-+#define OP_MASK_RS3		0x1f
-+#define OP_SH_RS3		27
-+#define OP_MASK_RD		0x1f
-+#define OP_SH_RD		7
-+#define OP_MASK_SHAMT		0x3f
-+#define OP_SH_SHAMT		20
-+#define OP_MASK_SHAMTW		0x1f
-+#define OP_SH_SHAMTW		20
-+#define OP_MASK_RM		0x7
-+#define OP_SH_RM		12
-+#define OP_MASK_PRED		0xf
-+#define OP_SH_PRED		24
-+#define OP_MASK_SUCC		0xf
-+#define OP_SH_SUCC		20
-+#define OP_MASK_AQ		0x1
-+#define OP_SH_AQ		26
-+#define OP_MASK_RL		0x1
-+#define OP_SH_RL		25
-+
-+#define OP_MASK_VRD		0x1f
-+#define OP_SH_VRD		7
-+#define OP_MASK_VRS		0x1f
-+#define OP_SH_VRS		15
-+#define OP_MASK_VRT		0x1f
-+#define OP_SH_VRT		20
-+#define OP_MASK_VRR		0x1f
-+#define OP_SH_VRR		25
-+
-+#define OP_MASK_VFD		0x1f
-+#define OP_SH_VFD		7
-+#define OP_MASK_VFS		0x1f
-+#define OP_SH_VFS		15
-+#define OP_MASK_VFT		0x1f
-+#define OP_SH_VFT		20
-+#define OP_MASK_VFR		0x1f
-+#define OP_SH_VFR		25
-+
-+#define OP_MASK_IMMNGPR         0x3f
-+#define OP_SH_IMMNGPR           20
-+#define OP_MASK_IMMNFPR         0x3f
-+#define OP_SH_IMMNFPR           26
-+#define OP_MASK_IMMSEGNELM      0x1f
-+#define OP_SH_IMMSEGNELM        17
-+#define OP_MASK_IMMSEGSTNELM    0x1f
-+#define OP_SH_IMMSEGSTNELM      12
-+#define OP_MASK_CUSTOM_IMM      0x7f
-+#define OP_SH_CUSTOM_IMM        25
-+
-+#define LINK_REG 1
-+
-+#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
-+#define RISCV_JUMP_ALIGN_BITS 1
-+#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
-+#define RISCV_JUMP_REACH ((1ULL<<RISCV_JUMP_BITS)*RISCV_JUMP_ALIGN)
-+
-+#define RISCV_IMM_BITS 12
-+#define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS)
-+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
-+#define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS)
-+#define RISCV_BRANCH_BITS RISCV_IMM_BITS
-+#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
-+#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
-+#define RISCV_BRANCH_REACH (RISCV_IMM_REACH*RISCV_BRANCH_ALIGN)
-+
-+#include "riscv-opc.h"
-+
-+#endif /* _RISCV_H_ */
-diff -urN empty/gcc/config/riscv/peephole.md gcc-5.2.0/gcc/config/riscv/peephole.md
---- gcc-5.2.0/gcc/config/riscv/peephole.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/peephole.md	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,100 @@
+diff -urN empty/gcc/config/riscv/peephole.md gcc-5.3.0/gcc/config/riscv/peephole.md
+--- empty/gcc/config/riscv/peephole.md	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/peephole.md	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,121 @@
 +;;........................
 +;; DI -> SI optimizations
 +;;........................
@@ -988,11 +832,11 @@ diff -urN empty/gcc/config/riscv/peephole.md gcc-5.2.0/gcc/config/riscv/peephole
 +	  [(match_operand:DI 1 "register_operand")
 +	   (match_operand:DI 2 "arith_operand")]))
 +   (set (match_operand:SI 3 "register_operand")
-+        (truncate:SI (match_dup 0)))]
++	(truncate:SI (match_dup 0)))]
 +  "TARGET_64BIT && (REGNO (operands[0]) == REGNO (operands[3]) || peep2_reg_dead_p (2, operands[0]))
 +   && (GET_CODE (operands[4]) != ASHIFT || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32))"
 +  [(set (match_dup 3)
-+          (truncate:SI
++	  (truncate:SI
 +	     (match_op_dup:DI 4 
 +	       [(match_operand:DI 1 "register_operand")
 +		(match_operand:DI 2 "arith_operand")])))])
@@ -1000,7 +844,7 @@ diff -urN empty/gcc/config/riscv/peephole.md gcc-5.2.0/gcc/config/riscv/peephole
 +;; Simplify (int)a + 1, etc.
 +(define_peephole2
 +  [(set (match_operand:SI 0 "register_operand")
-+        (truncate:SI (match_operand:DI 1 "register_operand")))
++	(truncate:SI (match_operand:DI 1 "register_operand")))
 +   (set (match_operand:SI 3 "register_operand")
 +	(match_operator:SI 4 "modular_operator"
 +	  [(match_dup 0)
@@ -1012,7 +856,7 @@ diff -urN empty/gcc/config/riscv/peephole.md gcc-5.2.0/gcc/config/riscv/peephole
 +;; Simplify -(int)a, etc.
 +(define_peephole2
 +  [(set (match_operand:SI 0 "register_operand")
-+        (truncate:SI (match_operand:DI 2 "register_operand")))
++	(truncate:SI (match_operand:DI 2 "register_operand")))
 +   (set (match_operand:SI 3 "register_operand")
 +	(match_operator:SI 4 "modular_operator"
 +	  [(match_operand:SI 1 "reg_or_0_operand")
@@ -1021,31 +865,52 @@ diff -urN empty/gcc/config/riscv/peephole.md gcc-5.2.0/gcc/config/riscv/peephole
 +  [(set (match_dup 3)
 +	(match_op_dup:SI 4 [(match_dup 1) (match_dup 2)]))])
 +
++;; Simplify (unsigned long)(unsigned int)a << const
++(define_peephole2
++  [(set (match_operand:DI 0 "register_operand")
++	(ashift:DI (match_operand:DI 1 "register_operand")
++		   (match_operand 2 "const_int_operand")))
++   (set (match_operand:DI 3 "register_operand")
++	(lshiftrt:DI (match_dup 0) (match_dup 2)))
++   (set (match_operand:DI 4 "register_operand")
++	(ashift:DI (match_dup 3) (match_operand 5 "const_int_operand")))]
++  "TARGET_64BIT
++   && INTVAL (operands[5]) < INTVAL (operands[2])
++   && (REGNO (operands[3]) == REGNO (operands[4])
++       || peep2_reg_dead_p (3, operands[3]))"
++  [(set (match_dup 0)
++	(ashift:DI (match_dup 1) (match_dup 2)))
++   (set (match_dup 4)
++	(lshiftrt:DI (match_dup 0) (match_operand 5)))]
++{
++  operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5]));
++})
++
 +;; Simplify PIC loads to static variables.
 +;; These will go away once we figure out how to emit auipc discretely.
 +(define_insn "*local_pic_load<mode>"
 +  [(set (match_operand:ANYI 0 "register_operand" "=r")
-+        (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))]
++	(mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))]
 +  "flag_pic && SYMBOL_REF_LOCAL_P (operands[1])"
 +  "<load>\t%0,%1"
 +  [(set (attr "length") (const_int 8))])
 +(define_insn "*local_pic_load<mode>"
 +  [(set (match_operand:ANYF 0 "register_operand" "=f")
-+        (mem:ANYF (match_operand 1 "absolute_symbolic_operand" "")))
++	(mem:ANYF (match_operand 1 "absolute_symbolic_operand" "")))
 +   (clobber (match_scratch:DI 2 "=&r"))]
 +  "TARGET_HARD_FLOAT && TARGET_64BIT && flag_pic && SYMBOL_REF_LOCAL_P (operands[1])"
 +  "<load>\t%0,%1,%2"
 +  [(set (attr "length") (const_int 8))])
 +(define_insn "*local_pic_load<mode>"
 +  [(set (match_operand:ANYF 0 "register_operand" "=f")
-+        (mem:ANYF (match_operand 1 "absolute_symbolic_operand" "")))
++	(mem:ANYF (match_operand 1 "absolute_symbolic_operand" "")))
 +   (clobber (match_scratch:SI 2 "=&r"))]
 +  "TARGET_HARD_FLOAT && !TARGET_64BIT && flag_pic && SYMBOL_REF_LOCAL_P (operands[1])"
 +  "<load>\t%0,%1,%2"
 +  [(set (attr "length") (const_int 8))])
 +(define_insn "*local_pic_loadu<mode>"
 +  [(set (match_operand:SUPERQI 0 "register_operand" "=r")
-+        (zero_extend:SUPERQI (mem:SUBDI (match_operand 1 "absolute_symbolic_operand" ""))))]
++	(zero_extend:SUPERQI (mem:SUBDI (match_operand 1 "absolute_symbolic_operand" ""))))]
 +  "flag_pic && SYMBOL_REF_LOCAL_P (operands[1])"
 +  "<load>u\t%0,%1"
 +  [(set (attr "length") (const_int 8))])
@@ -1077,10 +942,10 @@ diff -urN empty/gcc/config/riscv/peephole.md gcc-5.2.0/gcc/config/riscv/peephole
 +  "TARGET_HARD_FLOAT && !TARGET_64BIT && (flag_pic && SYMBOL_REF_LOCAL_P (operands[0]))"
 +  "<store>\t%1,%0,%2"
 +  [(set (attr "length") (const_int 8))])
-diff -urN empty/gcc/config/riscv/predicates.md gcc-5.2.0/gcc/config/riscv/predicates.md
---- gcc-5.2.0/gcc/config/riscv/predicates.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/predicates.md	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,187 @@
+diff -urN empty/gcc/config/riscv/predicates.md gcc-5.3.0/gcc/config/riscv/predicates.md
+--- empty/gcc/config/riscv/predicates.md	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/predicates.md	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,184 @@
 +;; Predicate description for RISC-V target.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -1137,7 +1002,7 @@ diff -urN empty/gcc/config/riscv/predicates.md gcc-5.2.0/gcc/config/riscv/predic
 +;; Only use branch-on-bit sequences when the mask is not an ANDI immediate.
 +(define_predicate "branch_on_bit_operand"
 +  (and (match_code "const_int")
-+       (match_test "INTVAL (op) >= RISCV_IMM_BITS - 1")))
++       (match_test "INTVAL (op) >= IMM_BITS - 1")))
 +
 +;; This is used for indexing into vectors, and hence only accepts const_int.
 +(define_predicate "const_0_or_1_operand"
@@ -1160,7 +1025,7 @@ diff -urN empty/gcc/config/riscv/predicates.md gcc-5.2.0/gcc/config/riscv/predic
 +
 +  /* Otherwise check whether the constant can be loaded in a single
 +     instruction.  */
-+  return !LUI_INT (op) && !SMALL_INT (op);
++  return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op));
 +})
 +
 +(define_predicate "move_operand"
@@ -1264,1539 +1129,11 @@ diff -urN empty/gcc/config/riscv/predicates.md gcc-5.2.0/gcc/config/riscv/predic
 +  (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu"))
 +
 +(define_predicate "fp_order_operator"
-+  (match_code "eq,lt,le,gt,ge"))
-+
-+(define_predicate "fp_unorder_operator"
-+  (match_code "ordered,unordered"))
-diff -urN empty/gcc/config/riscv/riscv-ftypes.def gcc-5.2.0/gcc/config/riscv/riscv-ftypes.def
---- gcc-5.2.0/gcc/config/riscv/riscv-ftypes.def	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/riscv-ftypes.def	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,39 @@
-+/* Definitions of prototypes for RISC-V built-in functions.
-+   Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+   Based on MIPS target for GNU compiler.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3.  If not see
-+<http://www.gnu.org/licenses/>.  */
-+
-+/* Invoke DEF_RISCV_FTYPE (NARGS, LIST) for each prototype used by
-+   MIPS built-in functions, where:
-+
-+      NARGS is the number of arguments.
-+      LIST contains the return-type code followed by the codes for each
-+        argument type.
-+
-+   Argument- and return-type codes are either modes or one of the following:
-+
-+      VOID for void_type_node
-+      INT for integer_type_node
-+      POINTER for ptr_type_node
-+
-+   (we don't use PTR because that's a ANSI-compatibillity macro).
-+
-+   Please keep this list lexicographically sorted by the LIST argument.  */
-+
-+DEF_RISCV_FTYPE (1, (VOID, VOID))
-diff -urN empty/gcc/config/riscv/riscv-modes.def gcc-5.2.0/gcc/config/riscv/riscv-modes.def
---- gcc-5.2.0/gcc/config/riscv/riscv-modes.def	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/riscv-modes.def	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,26 @@
-+/* Extra machine modes for RISC-V target.
-+   Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+   Based on MIPS target for GNU compiler.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3.  If not see
-+<http://www.gnu.org/licenses/>.  */
-+
-+FLOAT_MODE (TF, 16, ieee_quad_format);
-+
-+/* Vector modes.  */
-+VECTOR_MODES (INT, 4);        /*       V8QI V4HI V2SI */
-+VECTOR_MODES (FLOAT, 4);      /*            V4HF V2SF */
-diff -urN empty/gcc/config/riscv/riscv-opc.h gcc-5.2.0/gcc/config/riscv/riscv-opc.h
---- gcc-5.2.0/gcc/config/riscv/riscv-opc.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/riscv-opc.h	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,1348 @@
-+/* Automatically generated by parse-opcodes */
-+#ifndef RISCV_ENCODING_H
-+#define RISCV_ENCODING_H
-+#define MATCH_ADD 0x33
-+#define MASK_ADD  0xfe00707f
-+#define MATCH_ADDI 0x13
-+#define MASK_ADDI  0x707f
-+#define MATCH_ADDIW 0x1b
-+#define MASK_ADDIW  0x707f
-+#define MATCH_ADDW 0x3b
-+#define MASK_ADDW  0xfe00707f
-+#define MATCH_AMOADD_D 0x302f
-+#define MASK_AMOADD_D  0xf800707f
-+#define MATCH_AMOADD_W 0x202f
-+#define MASK_AMOADD_W  0xf800707f
-+#define MATCH_AMOAND_D 0x6000302f
-+#define MASK_AMOAND_D  0xf800707f
-+#define MATCH_AMOAND_W 0x6000202f
-+#define MASK_AMOAND_W  0xf800707f
-+#define MATCH_AMOMAX_D 0xa000302f
-+#define MASK_AMOMAX_D  0xf800707f
-+#define MATCH_AMOMAX_W 0xa000202f
-+#define MASK_AMOMAX_W  0xf800707f
-+#define MATCH_AMOMAXU_D 0xe000302f
-+#define MASK_AMOMAXU_D  0xf800707f
-+#define MATCH_AMOMAXU_W 0xe000202f
-+#define MASK_AMOMAXU_W  0xf800707f
-+#define MATCH_AMOMIN_D 0x8000302f
-+#define MASK_AMOMIN_D  0xf800707f
-+#define MATCH_AMOMIN_W 0x8000202f
-+#define MASK_AMOMIN_W  0xf800707f
-+#define MATCH_AMOMINU_D 0xc000302f
-+#define MASK_AMOMINU_D  0xf800707f
-+#define MATCH_AMOMINU_W 0xc000202f
-+#define MASK_AMOMINU_W  0xf800707f
-+#define MATCH_AMOOR_D 0x4000302f
-+#define MASK_AMOOR_D  0xf800707f
-+#define MATCH_AMOOR_W 0x4000202f
-+#define MASK_AMOOR_W  0xf800707f
-+#define MATCH_AMOSWAP_D 0x800302f
-+#define MASK_AMOSWAP_D  0xf800707f
-+#define MATCH_AMOSWAP_W 0x800202f
-+#define MASK_AMOSWAP_W  0xf800707f
-+#define MATCH_AMOXOR_D 0x2000302f
-+#define MASK_AMOXOR_D  0xf800707f
-+#define MATCH_AMOXOR_W 0x2000202f
-+#define MASK_AMOXOR_W  0xf800707f
-+#define MATCH_AND 0x7033
-+#define MASK_AND  0xfe00707f
-+#define MATCH_ANDI 0x7013
-+#define MASK_ANDI  0x707f
-+#define MATCH_AUIPC 0x17
-+#define MASK_AUIPC  0x7f
-+#define MATCH_BEQ 0x63
-+#define MASK_BEQ  0x707f
-+#define MATCH_BGE 0x5063
-+#define MASK_BGE  0x707f
-+#define MATCH_BGEU 0x7063
-+#define MASK_BGEU  0x707f
-+#define MATCH_BLT 0x4063
-+#define MASK_BLT  0x707f
-+#define MATCH_BLTU 0x6063
-+#define MASK_BLTU  0x707f
-+#define MATCH_BNE 0x1063
-+#define MASK_BNE  0x707f
-+#define MATCH_C_ADD 0x1000
-+#define MASK_C_ADD  0xf003
-+#define MATCH_C_ADD3 0xa000
-+#define MASK_C_ADD3  0xe063
-+#define MATCH_C_ADDI 0xc002
-+#define MASK_C_ADDI  0xe003
-+#define MATCH_C_ADDI16SP 0xc002
-+#define MASK_C_ADDI16SP  0xef83
-+#define MATCH_C_ADDI4SPN 0xa001
-+#define MASK_C_ADDI4SPN  0xe003
-+#define MATCH_C_ADDIN 0x8001
-+#define MASK_C_ADDIN  0xe063
-+#define MATCH_C_ADDIW 0xe002
-+#define MASK_C_ADDIW  0xe003
-+#define MATCH_C_ADDW 0x9000
-+#define MASK_C_ADDW  0xf003
-+#define MATCH_C_AND3 0xa060
-+#define MASK_C_AND3  0xe063
-+#define MATCH_C_ANDI 0xe002
-+#define MASK_C_ANDI  0xe003
-+#define MATCH_C_ANDIN 0x8061
-+#define MASK_C_ANDIN  0xe063
-+#define MATCH_C_BEQZ 0x4002
-+#define MASK_C_BEQZ  0xe003
-+#define MATCH_C_BGEZ 0xe001
-+#define MASK_C_BGEZ  0xe003
-+#define MATCH_C_BLTZ 0x6001
-+#define MASK_C_BLTZ  0xe003
-+#define MATCH_C_BNEZ 0x6002
-+#define MASK_C_BNEZ  0xe003
-+#define MATCH_C_EBREAK 0x1000
-+#define MASK_C_EBREAK  0xffff
-+#define MATCH_C_J 0x2
-+#define MASK_C_J  0xe003
-+#define MATCH_C_JAL 0x2002
-+#define MASK_C_JAL  0xe003
-+#define MATCH_C_JALR 0xa002
-+#define MASK_C_JALR  0xf07f
-+#define MATCH_C_JR 0x8002
-+#define MASK_C_JR  0xf07f
-+#define MATCH_C_LD 0xe000
-+#define MASK_C_LD  0xe003
-+#define MATCH_C_LDSP 0xe001
-+#define MASK_C_LDSP  0xe003
-+#define MATCH_C_LI 0x8002
-+#define MASK_C_LI  0xe003
-+#define MATCH_C_LUI 0xa002
-+#define MASK_C_LUI  0xe003
-+#define MATCH_C_LW 0xc000
-+#define MASK_C_LW  0xe003
-+#define MATCH_C_LWSP 0xc001
-+#define MASK_C_LWSP  0xe003
-+#define MATCH_C_MV 0x0
-+#define MASK_C_MV  0xf003
-+#define MATCH_C_OR3 0xa040
-+#define MASK_C_OR3  0xe063
-+#define MATCH_C_ORIN 0x8041
-+#define MASK_C_ORIN  0xe063
-+#define MATCH_C_SD 0x6000
-+#define MASK_C_SD  0xe003
-+#define MATCH_C_SDSP 0x6001
-+#define MASK_C_SDSP  0xe003
-+#define MATCH_C_SLL 0x6400
-+#define MASK_C_SLL  0xfc63
-+#define MATCH_C_SLLI 0x1
-+#define MASK_C_SLLI  0xe003
-+#define MATCH_C_SLLIW 0x8001
-+#define MASK_C_SLLIW  0xe003
-+#define MATCH_C_SLLR 0x6c00
-+#define MASK_C_SLLR  0xfc63
-+#define MATCH_C_SLT 0x6440
-+#define MASK_C_SLT  0xfc63
-+#define MATCH_C_SLTR 0x6c40
-+#define MASK_C_SLTR  0xfc63
-+#define MATCH_C_SLTU 0x6460
-+#define MASK_C_SLTU  0xfc63
-+#define MATCH_C_SLTUR 0x6c60
-+#define MASK_C_SLTUR  0xfc63
-+#define MATCH_C_SRA 0x6020
-+#define MASK_C_SRA  0xfc63
-+#define MATCH_C_SRAI 0x2000
-+#define MASK_C_SRAI  0xe003
-+#define MATCH_C_SRL 0x6420
-+#define MASK_C_SRL  0xfc63
-+#define MATCH_C_SRLI 0x2001
-+#define MASK_C_SRLI  0xe003
-+#define MATCH_C_SRLR 0x6c20
-+#define MASK_C_SRLR  0xfc63
-+#define MATCH_C_SUB 0x8000
-+#define MASK_C_SUB  0xf003
-+#define MATCH_C_SUB3 0xa020
-+#define MASK_C_SUB3  0xe063
-+#define MATCH_C_SW 0x4000
-+#define MASK_C_SW  0xe003
-+#define MATCH_C_SWSP 0x4001
-+#define MASK_C_SWSP  0xe003
-+#define MATCH_C_XOR 0x6000
-+#define MASK_C_XOR  0xfc63
-+#define MATCH_C_XORIN 0x8021
-+#define MASK_C_XORIN  0xe063
-+#define MATCH_CSRRC 0x3073
-+#define MASK_CSRRC  0x707f
-+#define MATCH_CSRRCI 0x7073
-+#define MASK_CSRRCI  0x707f
-+#define MATCH_CSRRS 0x2073
-+#define MASK_CSRRS  0x707f
-+#define MATCH_CSRRSI 0x6073
-+#define MASK_CSRRSI  0x707f
-+#define MATCH_CSRRW 0x1073
-+#define MASK_CSRRW  0x707f
-+#define MATCH_CSRRWI 0x5073
-+#define MASK_CSRRWI  0x707f
-+#define MATCH_CUSTOM0 0xb
-+#define MASK_CUSTOM0  0x707f
-+#define MATCH_CUSTOM0_RD 0x400b
-+#define MASK_CUSTOM0_RD  0x707f
-+#define MATCH_CUSTOM0_RD_RS1 0x600b
-+#define MASK_CUSTOM0_RD_RS1  0x707f
-+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
-+#define MATCH_CUSTOM0_RS1 0x200b
-+#define MASK_CUSTOM0_RS1  0x707f
-+#define MATCH_CUSTOM0_RS1_RS2 0x300b
-+#define MASK_CUSTOM0_RS1_RS2  0x707f
-+#define MATCH_CUSTOM1 0x2b
-+#define MASK_CUSTOM1  0x707f
-+#define MATCH_CUSTOM1_RD 0x402b
-+#define MASK_CUSTOM1_RD  0x707f
-+#define MATCH_CUSTOM1_RD_RS1 0x602b
-+#define MASK_CUSTOM1_RD_RS1  0x707f
-+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
-+#define MATCH_CUSTOM1_RS1 0x202b
-+#define MASK_CUSTOM1_RS1  0x707f
-+#define MATCH_CUSTOM1_RS1_RS2 0x302b
-+#define MASK_CUSTOM1_RS1_RS2  0x707f
-+#define MATCH_CUSTOM2 0x5b
-+#define MASK_CUSTOM2  0x707f
-+#define MATCH_CUSTOM2_RD 0x405b
-+#define MASK_CUSTOM2_RD  0x707f
-+#define MATCH_CUSTOM2_RD_RS1 0x605b
-+#define MASK_CUSTOM2_RD_RS1  0x707f
-+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
-+#define MATCH_CUSTOM2_RS1 0x205b
-+#define MASK_CUSTOM2_RS1  0x707f
-+#define MATCH_CUSTOM2_RS1_RS2 0x305b
-+#define MASK_CUSTOM2_RS1_RS2  0x707f
-+#define MATCH_CUSTOM3 0x7b
-+#define MASK_CUSTOM3  0x707f
-+#define MATCH_CUSTOM3_RD 0x407b
-+#define MASK_CUSTOM3_RD  0x707f
-+#define MATCH_CUSTOM3_RD_RS1 0x607b
-+#define MASK_CUSTOM3_RD_RS1  0x707f
-+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
-+#define MATCH_CUSTOM3_RS1 0x207b
-+#define MASK_CUSTOM3_RS1  0x707f
-+#define MATCH_CUSTOM3_RS1_RS2 0x307b
-+#define MASK_CUSTOM3_RS1_RS2  0x707f
-+#define MATCH_DIV 0x2004033
-+#define MASK_DIV  0xfe00707f
-+#define MATCH_DIVU 0x2005033
-+#define MASK_DIVU  0xfe00707f
-+#define MATCH_DIVUW 0x200503b
-+#define MASK_DIVUW  0xfe00707f
-+#define MATCH_DIVW 0x200403b
-+#define MASK_DIVW  0xfe00707f
-+#define MATCH_EBREAK 0x100073
-+#define MASK_EBREAK  0xffffffff
-+#define MATCH_ECALL 0x73
-+#define MASK_ECALL  0xffffffff
-+#define MATCH_ERET 0x10000073
-+#define MASK_ERET  0xffffffff
-+#define MATCH_FADD_D 0x2000053
-+#define MASK_FADD_D  0xfe00007f
-+#define MATCH_FADD_H 0x4000053
-+#define MASK_FADD_H  0xfe00007f
-+#define MATCH_FADD_S 0x53
-+#define MASK_FADD_S  0xfe00007f
-+#define MATCH_FCLASS_D 0xe2001053
-+#define MASK_FCLASS_D  0xfff0707f
-+#define MATCH_FCLASS_S 0xe0001053
-+#define MASK_FCLASS_S  0xfff0707f
-+#define MATCH_FCVT_D_H 0x8c000053
-+#define MASK_FCVT_D_H  0xfff0007f
-+#define MATCH_FCVT_D_L 0xd2200053
-+#define MASK_FCVT_D_L  0xfff0007f
-+#define MATCH_FCVT_D_LU 0xd2300053
-+#define MASK_FCVT_D_LU  0xfff0007f
-+#define MATCH_FCVT_D_S 0x42000053
-+#define MASK_FCVT_D_S  0xfff0007f
-+#define MATCH_FCVT_D_W 0xd2000053
-+#define MASK_FCVT_D_W  0xfff0007f
-+#define MATCH_FCVT_D_WU 0xd2100053
-+#define MASK_FCVT_D_WU  0xfff0007f
-+#define MATCH_FCVT_H_D 0x92000053
-+#define MASK_FCVT_H_D  0xfff0007f
-+#define MATCH_FCVT_H_L 0x64000053
-+#define MASK_FCVT_H_L  0xfff0007f
-+#define MATCH_FCVT_H_LU 0x6c000053
-+#define MASK_FCVT_H_LU  0xfff0007f
-+#define MATCH_FCVT_H_S 0x90000053
-+#define MASK_FCVT_H_S  0xfff0007f
-+#define MATCH_FCVT_H_W 0x74000053
-+#define MASK_FCVT_H_W  0xfff0007f
-+#define MATCH_FCVT_H_WU 0x7c000053
-+#define MASK_FCVT_H_WU  0xfff0007f
-+#define MATCH_FCVT_L_D 0xc2200053
-+#define MASK_FCVT_L_D  0xfff0007f
-+#define MATCH_FCVT_L_H 0x44000053
-+#define MASK_FCVT_L_H  0xfff0007f
-+#define MATCH_FCVT_L_S 0xc0200053
-+#define MASK_FCVT_L_S  0xfff0007f
-+#define MATCH_FCVT_LU_D 0xc2300053
-+#define MASK_FCVT_LU_D  0xfff0007f
-+#define MATCH_FCVT_LU_H 0x4c000053
-+#define MASK_FCVT_LU_H  0xfff0007f
-+#define MATCH_FCVT_LU_S 0xc0300053
-+#define MASK_FCVT_LU_S  0xfff0007f
-+#define MATCH_FCVT_S_D 0x40100053
-+#define MASK_FCVT_S_D  0xfff0007f
-+#define MATCH_FCVT_S_H 0x84000053
-+#define MASK_FCVT_S_H  0xfff0007f
-+#define MATCH_FCVT_S_L 0xd0200053
-+#define MASK_FCVT_S_L  0xfff0007f
-+#define MATCH_FCVT_S_LU 0xd0300053
-+#define MASK_FCVT_S_LU  0xfff0007f
-+#define MATCH_FCVT_S_W 0xd0000053
-+#define MASK_FCVT_S_W  0xfff0007f
-+#define MATCH_FCVT_S_WU 0xd0100053
-+#define MASK_FCVT_S_WU  0xfff0007f
-+#define MATCH_FCVT_W_D 0xc2000053
-+#define MASK_FCVT_W_D  0xfff0007f
-+#define MATCH_FCVT_W_H 0x54000053
-+#define MASK_FCVT_W_H  0xfff0007f
-+#define MATCH_FCVT_W_S 0xc0000053
-+#define MASK_FCVT_W_S  0xfff0007f
-+#define MATCH_FCVT_WU_D 0xc2100053
-+#define MASK_FCVT_WU_D  0xfff0007f
-+#define MATCH_FCVT_WU_H 0x5c000053
-+#define MASK_FCVT_WU_H  0xfff0007f
-+#define MATCH_FCVT_WU_S 0xc0100053
-+#define MASK_FCVT_WU_S  0xfff0007f
-+#define MATCH_FDIV_D 0x1a000053
-+#define MASK_FDIV_D  0xfe00007f
-+#define MATCH_FDIV_H 0x1c000053
-+#define MASK_FDIV_H  0xfe00007f
-+#define MATCH_FDIV_S 0x18000053
-+#define MASK_FDIV_S  0xfe00007f
-+#define MATCH_FENCE 0xf
-+#define MASK_FENCE  0x707f
-+#define MATCH_FENCE_I 0x100f
-+#define MASK_FENCE_I  0x707f
-+#define MATCH_FEQ_D 0xa2002053
-+#define MASK_FEQ_D  0xfe00707f
-+#define MATCH_FEQ_H 0xac000053
-+#define MASK_FEQ_H  0xfe00707f
-+#define MATCH_FEQ_S 0xa0002053
-+#define MASK_FEQ_S  0xfe00707f
-+#define MATCH_FLD 0x3007
-+#define MASK_FLD  0x707f
-+#define MATCH_FLE_D 0xa2000053
-+#define MASK_FLE_D  0xfe00707f
-+#define MATCH_FLE_H 0xbc000053
-+#define MASK_FLE_H  0xfe00707f
-+#define MATCH_FLE_S 0xa0000053
-+#define MASK_FLE_S  0xfe00707f
-+#define MATCH_FLH 0x1007
-+#define MASK_FLH  0x707f
-+#define MATCH_FLT_D 0xa2001053
-+#define MASK_FLT_D  0xfe00707f
-+#define MATCH_FLT_H 0xb4000053
-+#define MASK_FLT_H  0xfe00707f
-+#define MATCH_FLT_S 0xa0001053
-+#define MASK_FLT_S  0xfe00707f
-+#define MATCH_FLW 0x2007
-+#define MASK_FLW  0x707f
-+#define MATCH_FMADD_D 0x2000043
-+#define MASK_FMADD_D  0x600007f
-+#define MATCH_FMADD_H 0x4000043
-+#define MASK_FMADD_H  0x600007f
-+#define MATCH_FMADD_S 0x43
-+#define MASK_FMADD_S  0x600007f
-+#define MATCH_FMAX_D 0x2a001053
-+#define MASK_FMAX_D  0xfe00707f
-+#define MATCH_FMAX_H 0xcc000053
-+#define MASK_FMAX_H  0xfe00707f
-+#define MATCH_FMAX_S 0x28001053
-+#define MASK_FMAX_S  0xfe00707f
-+#define MATCH_FMIN_D 0x2a000053
-+#define MASK_FMIN_D  0xfe00707f
-+#define MATCH_FMIN_H 0xc4000053
-+#define MASK_FMIN_H  0xfe00707f
-+#define MATCH_FMIN_S 0x28000053
-+#define MASK_FMIN_S  0xfe00707f
-+#define MATCH_FMOVN 0x6007077
-+#define MASK_FMOVN  0xfe00707f
-+#define MATCH_FMOVZ 0x4007077
-+#define MASK_FMOVZ  0xfe00707f
-+#define MATCH_FMSUB_D 0x2000047
-+#define MASK_FMSUB_D  0x600007f
-+#define MATCH_FMSUB_H 0x4000047
-+#define MASK_FMSUB_H  0x600007f
-+#define MATCH_FMSUB_S 0x47
-+#define MASK_FMSUB_S  0x600007f
-+#define MATCH_FMUL_D 0x12000053
-+#define MASK_FMUL_D  0xfe00007f
-+#define MATCH_FMUL_H 0x14000053
-+#define MASK_FMUL_H  0xfe00007f
-+#define MATCH_FMUL_S 0x10000053
-+#define MASK_FMUL_S  0xfe00007f
-+#define MATCH_FMV_D_X 0xf2000053
-+#define MASK_FMV_D_X  0xfff0707f
-+#define MATCH_FMV_H_X 0xf4000053
-+#define MASK_FMV_H_X  0xfff0707f
-+#define MATCH_FMV_S_X 0xf0000053
-+#define MASK_FMV_S_X  0xfff0707f
-+#define MATCH_FMV_X_D 0xe2000053
-+#define MASK_FMV_X_D  0xfff0707f
-+#define MATCH_FMV_X_H 0xe4000053
-+#define MASK_FMV_X_H  0xfff0707f
-+#define MATCH_FMV_X_S 0xe0000053
-+#define MASK_FMV_X_S  0xfff0707f
-+#define MATCH_FNMADD_D 0x200004f
-+#define MASK_FNMADD_D  0x600007f
-+#define MATCH_FNMADD_H 0x400004f
-+#define MASK_FNMADD_H  0x600007f
-+#define MATCH_FNMADD_S 0x4f
-+#define MASK_FNMADD_S  0x600007f
-+#define MATCH_FNMSUB_D 0x200004b
-+#define MASK_FNMSUB_D  0x600007f
-+#define MATCH_FNMSUB_H 0x400004b
-+#define MASK_FNMSUB_H  0x600007f
-+#define MATCH_FNMSUB_S 0x4b
-+#define MASK_FNMSUB_S  0x600007f
-+#define MATCH_FRCSR 0x302073
-+#define MASK_FRCSR  0xfffff07f
-+#define MATCH_FRFLAGS 0x102073
-+#define MASK_FRFLAGS  0xfffff07f
-+#define MATCH_FRRM 0x202073
-+#define MASK_FRRM  0xfffff07f
-+#define MATCH_FSCSR 0x301073
-+#define MASK_FSCSR  0xfff0707f
-+#define MATCH_FSD 0x3027
-+#define MASK_FSD  0x707f
-+#define MATCH_FSFLAGS 0x101073
-+#define MASK_FSFLAGS  0xfff0707f
-+#define MATCH_FSFLAGSI 0x105073
-+#define MASK_FSFLAGSI  0xfff0707f
-+#define MATCH_FSGNJ_D 0x22000053
-+#define MASK_FSGNJ_D  0xfe00707f
-+#define MATCH_FSGNJ_H 0x2c000053
-+#define MASK_FSGNJ_H  0xfe00707f
-+#define MATCH_FSGNJ_S 0x20000053
-+#define MASK_FSGNJ_S  0xfe00707f
-+#define MATCH_FSGNJN_D 0x22001053
-+#define MASK_FSGNJN_D  0xfe00707f
-+#define MATCH_FSGNJN_H 0x34000053
-+#define MASK_FSGNJN_H  0xfe00707f
-+#define MATCH_FSGNJN_S 0x20001053
-+#define MASK_FSGNJN_S  0xfe00707f
-+#define MATCH_FSGNJX_D 0x22002053
-+#define MASK_FSGNJX_D  0xfe00707f
-+#define MATCH_FSGNJX_H 0x3c000053
-+#define MASK_FSGNJX_H  0xfe00707f
-+#define MATCH_FSGNJX_S 0x20002053
-+#define MASK_FSGNJX_S  0xfe00707f
-+#define MATCH_FSH 0x1027
-+#define MASK_FSH  0x707f
-+#define MATCH_FSQRT_D 0x5a000053
-+#define MASK_FSQRT_D  0xfff0007f
-+#define MATCH_FSQRT_H 0x24000053
-+#define MASK_FSQRT_H  0xfff0007f
-+#define MATCH_FSQRT_S 0x58000053
-+#define MASK_FSQRT_S  0xfff0007f
-+#define MATCH_FSRM 0x201073
-+#define MASK_FSRM  0xfff0707f
-+#define MATCH_FSRMI 0x205073
-+#define MASK_FSRMI  0xfff0707f
-+#define MATCH_FSUB_D 0xa000053
-+#define MASK_FSUB_D  0xfe00007f
-+#define MATCH_FSUB_H 0xc000053
-+#define MASK_FSUB_H  0xfe00007f
-+#define MATCH_FSUB_S 0x8000053
-+#define MASK_FSUB_S  0xfe00007f
-+#define MATCH_FSW 0x2027
-+#define MASK_FSW  0x707f
-+#define MATCH_HRTS 0x20500073
-+#define MASK_HRTS  0xffffffff
-+#define MATCH_JAL 0x6f
-+#define MASK_JAL  0x7f
-+#define MATCH_JALR 0x67
-+#define MASK_JALR  0x707f
-+#define MATCH_LB 0x3
-+#define MASK_LB  0x707f
-+#define MATCH_LBU 0x4003
-+#define MASK_LBU  0x707f
-+#define MATCH_LD 0x3003
-+#define MASK_LD  0x707f
-+#define MATCH_LH 0x1003
-+#define MASK_LH  0x707f
-+#define MATCH_LHU 0x5003
-+#define MASK_LHU  0x707f
-+#define MATCH_LR_D 0x1000302f
-+#define MASK_LR_D  0xf9f0707f
-+#define MATCH_LR_W 0x1000202f
-+#define MASK_LR_W  0xf9f0707f
-+#define MATCH_LUI 0x37
-+#define MASK_LUI  0x7f
-+#define MATCH_LW 0x2003
-+#define MASK_LW  0x707f
-+#define MATCH_LWU 0x6003
-+#define MASK_LWU  0x707f
-+#define MATCH_MOVN 0x2007077
-+#define MASK_MOVN  0xfe00707f
-+#define MATCH_MOVZ 0x7077
-+#define MASK_MOVZ  0xfe00707f
-+#define MATCH_MRTH 0x30600073
-+#define MASK_MRTH  0xffffffff
-+#define MATCH_MRTS 0x30500073
-+#define MASK_MRTS  0xffffffff
-+#define MATCH_MUL 0x2000033
-+#define MASK_MUL  0xfe00707f
-+#define MATCH_MULH 0x2001033
-+#define MASK_MULH  0xfe00707f
-+#define MATCH_MULHSU 0x2002033
-+#define MASK_MULHSU  0xfe00707f
-+#define MATCH_MULHU 0x2003033
-+#define MASK_MULHU  0xfe00707f
-+#define MATCH_MULW 0x200003b
-+#define MASK_MULW  0xfe00707f
-+#define MATCH_OR 0x6033
-+#define MASK_OR  0xfe00707f
-+#define MATCH_ORI 0x6013
-+#define MASK_ORI  0x707f
-+#define MATCH_RDCYCLE 0xc0002073
-+#define MASK_RDCYCLE  0xfffff07f
-+#define MATCH_RDCYCLEH 0xc8002073
-+#define MASK_RDCYCLEH  0xfffff07f
-+#define MATCH_RDINSTRET 0xc0202073
-+#define MASK_RDINSTRET  0xfffff07f
-+#define MATCH_RDINSTRETH 0xc8202073
-+#define MASK_RDINSTRETH  0xfffff07f
-+#define MATCH_RDTIME 0xc0102073
-+#define MASK_RDTIME  0xfffff07f
-+#define MATCH_RDTIMEH 0xc8102073
-+#define MASK_RDTIMEH  0xfffff07f
-+#define MATCH_REM 0x2006033
-+#define MASK_REM  0xfe00707f
-+#define MATCH_REMU 0x2007033
-+#define MASK_REMU  0xfe00707f
-+#define MATCH_REMUW 0x200703b
-+#define MASK_REMUW  0xfe00707f
-+#define MATCH_REMW 0x200603b
-+#define MASK_REMW  0xfe00707f
-+#define MATCH_SB 0x23
-+#define MASK_SB  0x707f
-+#define MATCH_SBREAK 0x100073
-+#define MASK_SBREAK  0xffffffff
-+#define MATCH_SC_D 0x1800302f
-+#define MASK_SC_D  0xf800707f
-+#define MATCH_SC_W 0x1800202f
-+#define MASK_SC_W  0xf800707f
-+#define MATCH_SCALL 0x73
-+#define MASK_SCALL  0xffffffff
-+#define MATCH_SD 0x3023
-+#define MASK_SD  0x707f
-+#define MATCH_SFENCE_VM 0x10100073
-+#define MASK_SFENCE_VM  0xfff07fff
-+#define MATCH_SH 0x1023
-+#define MASK_SH  0x707f
-+#define MATCH_SLL 0x1033
-+#define MASK_SLL  0xfe00707f
-+#define MATCH_SLLI 0x1013
-+#define MASK_SLLI  0xfc00707f
-+#define MATCH_SLLI_RV32 0x1013
-+#define MASK_SLLI_RV32  0xfe00707f
-+#define MATCH_SLLIW 0x101b
-+#define MASK_SLLIW  0xfe00707f
-+#define MATCH_SLLW 0x103b
-+#define MASK_SLLW  0xfe00707f
-+#define MATCH_SLT 0x2033
-+#define MASK_SLT  0xfe00707f
-+#define MATCH_SLTI 0x2013
-+#define MASK_SLTI  0x707f
-+#define MATCH_SLTIU 0x3013
-+#define MASK_SLTIU  0x707f
-+#define MATCH_SLTU 0x3033
-+#define MASK_SLTU  0xfe00707f
-+#define MATCH_SRA 0x40005033
-+#define MASK_SRA  0xfe00707f
-+#define MATCH_SRAI 0x40005013
-+#define MASK_SRAI  0xfc00707f
-+#define MATCH_SRAI_RV32 0x40005013
-+#define MASK_SRAI_RV32  0xfe00707f
-+#define MATCH_SRAIW 0x4000501b
-+#define MASK_SRAIW  0xfe00707f
-+#define MATCH_SRAW 0x4000503b
-+#define MASK_SRAW  0xfe00707f
-+#define MATCH_SRET 0x10000073
-+#define MASK_SRET  0xffffffff
-+#define MATCH_SRL 0x5033
-+#define MASK_SRL  0xfe00707f
-+#define MATCH_SRLI 0x5013
-+#define MASK_SRLI  0xfc00707f
-+#define MATCH_SRLI_RV32 0x5013
-+#define MASK_SRLI_RV32  0xfe00707f
-+#define MATCH_SRLIW 0x501b
-+#define MASK_SRLIW  0xfe00707f
-+#define MATCH_SRLW 0x503b
-+#define MASK_SRLW  0xfe00707f
-+#define MATCH_STOP 0x5077
-+#define MASK_STOP  0xffffffff
-+#define MATCH_SUB 0x40000033
-+#define MASK_SUB  0xfe00707f
-+#define MATCH_SUBW 0x4000003b
-+#define MASK_SUBW  0xfe00707f
-+#define MATCH_SW 0x2023
-+#define MASK_SW  0x707f
-+#define MATCH_UTIDX 0x6077
-+#define MASK_UTIDX  0xfffff07f
-+#define MATCH_VENQCMD 0xa00302b
-+#define MASK_VENQCMD  0xfe007fff
-+#define MATCH_VENQCNT 0x1000302b
-+#define MASK_VENQCNT  0xfe007fff
-+#define MATCH_VENQIMM1 0xc00302b
-+#define MASK_VENQIMM1  0xfe007fff
-+#define MATCH_VENQIMM2 0xe00302b
-+#define MASK_VENQIMM2  0xfe007fff
-+#define MATCH_VF 0x10202b
-+#define MASK_VF  0x1f0707f
-+#define MATCH_VFLD 0x1600205b
-+#define MASK_VFLD  0xfff0707f
-+#define MATCH_VFLSEGD 0x1600205b
-+#define MASK_VFLSEGD  0x1ff0707f
-+#define MATCH_VFLSEGSTD 0x1600305b
-+#define MASK_VFLSEGSTD  0x1e00707f
-+#define MATCH_VFLSEGSTW 0x1400305b
-+#define MASK_VFLSEGSTW  0x1e00707f
-+#define MATCH_VFLSEGW 0x1400205b
-+#define MASK_VFLSEGW  0x1ff0707f
-+#define MATCH_VFLSTD 0x1600305b
-+#define MASK_VFLSTD  0xfe00707f
-+#define MATCH_VFLSTW 0x1400305b
-+#define MASK_VFLSTW  0xfe00707f
-+#define MATCH_VFLW 0x1400205b
-+#define MASK_VFLW  0xfff0707f
-+#define MATCH_VFMSV_D 0x1200202b
-+#define MASK_VFMSV_D  0xfff0707f
-+#define MATCH_VFMSV_S 0x1000202b
-+#define MASK_VFMSV_S  0xfff0707f
-+#define MATCH_VFMVV 0x1000002b
-+#define MASK_VFMVV  0xfff0707f
-+#define MATCH_VFSD 0x1600207b
-+#define MASK_VFSD  0xfff0707f
-+#define MATCH_VFSSEGD 0x1600207b
-+#define MASK_VFSSEGD  0x1ff0707f
-+#define MATCH_VFSSEGSTD 0x1600307b
-+#define MASK_VFSSEGSTD  0x1e00707f
-+#define MATCH_VFSSEGSTW 0x1400307b
-+#define MASK_VFSSEGSTW  0x1e00707f
-+#define MATCH_VFSSEGW 0x1400207b
-+#define MASK_VFSSEGW  0x1ff0707f
-+#define MATCH_VFSSTD 0x1600307b
-+#define MASK_VFSSTD  0xfe00707f
-+#define MATCH_VFSSTW 0x1400307b
-+#define MASK_VFSSTW  0xfe00707f
-+#define MATCH_VFSW 0x1400207b
-+#define MASK_VFSW  0xfff0707f
-+#define MATCH_VGETCFG 0x400b
-+#define MASK_VGETCFG  0xfffff07f
-+#define MATCH_VGETVL 0x200400b
-+#define MASK_VGETVL  0xfffff07f
-+#define MATCH_VLB 0x205b
-+#define MASK_VLB  0xfff0707f
-+#define MATCH_VLBU 0x800205b
-+#define MASK_VLBU  0xfff0707f
-+#define MATCH_VLD 0x600205b
-+#define MASK_VLD  0xfff0707f
-+#define MATCH_VLH 0x200205b
-+#define MASK_VLH  0xfff0707f
-+#define MATCH_VLHU 0xa00205b
-+#define MASK_VLHU  0xfff0707f
-+#define MATCH_VLSEGB 0x205b
-+#define MASK_VLSEGB  0x1ff0707f
-+#define MATCH_VLSEGBU 0x800205b
-+#define MASK_VLSEGBU  0x1ff0707f
-+#define MATCH_VLSEGD 0x600205b
-+#define MASK_VLSEGD  0x1ff0707f
-+#define MATCH_VLSEGH 0x200205b
-+#define MASK_VLSEGH  0x1ff0707f
-+#define MATCH_VLSEGHU 0xa00205b
-+#define MASK_VLSEGHU  0x1ff0707f
-+#define MATCH_VLSEGSTB 0x305b
-+#define MASK_VLSEGSTB  0x1e00707f
-+#define MATCH_VLSEGSTBU 0x800305b
-+#define MASK_VLSEGSTBU  0x1e00707f
-+#define MATCH_VLSEGSTD 0x600305b
-+#define MASK_VLSEGSTD  0x1e00707f
-+#define MATCH_VLSEGSTH 0x200305b
-+#define MASK_VLSEGSTH  0x1e00707f
-+#define MATCH_VLSEGSTHU 0xa00305b
-+#define MASK_VLSEGSTHU  0x1e00707f
-+#define MATCH_VLSEGSTW 0x400305b
-+#define MASK_VLSEGSTW  0x1e00707f
-+#define MATCH_VLSEGSTWU 0xc00305b
-+#define MASK_VLSEGSTWU  0x1e00707f
-+#define MATCH_VLSEGW 0x400205b
-+#define MASK_VLSEGW  0x1ff0707f
-+#define MATCH_VLSEGWU 0xc00205b
-+#define MASK_VLSEGWU  0x1ff0707f
-+#define MATCH_VLSTB 0x305b
-+#define MASK_VLSTB  0xfe00707f
-+#define MATCH_VLSTBU 0x800305b
-+#define MASK_VLSTBU  0xfe00707f
-+#define MATCH_VLSTD 0x600305b
-+#define MASK_VLSTD  0xfe00707f
-+#define MATCH_VLSTH 0x200305b
-+#define MASK_VLSTH  0xfe00707f
-+#define MATCH_VLSTHU 0xa00305b
-+#define MASK_VLSTHU  0xfe00707f
-+#define MATCH_VLSTW 0x400305b
-+#define MASK_VLSTW  0xfe00707f
-+#define MATCH_VLSTWU 0xc00305b
-+#define MASK_VLSTWU  0xfe00707f
-+#define MATCH_VLW 0x400205b
-+#define MASK_VLW  0xfff0707f
-+#define MATCH_VLWU 0xc00205b
-+#define MASK_VLWU  0xfff0707f
-+#define MATCH_VMSV 0x200202b
-+#define MASK_VMSV  0xfff0707f
-+#define MATCH_VMVV 0x200002b
-+#define MASK_VMVV  0xfff0707f
-+#define MATCH_VSB 0x207b
-+#define MASK_VSB  0xfff0707f
-+#define MATCH_VSD 0x600207b
-+#define MASK_VSD  0xfff0707f
-+#define MATCH_VSETCFG 0x200b
-+#define MASK_VSETCFG  0x7fff
-+#define MATCH_VSETVL 0x600b
-+#define MASK_VSETVL  0xfff0707f
-+#define MATCH_VSH 0x200207b
-+#define MASK_VSH  0xfff0707f
-+#define MATCH_VSSEGB 0x207b
-+#define MASK_VSSEGB  0x1ff0707f
-+#define MATCH_VSSEGD 0x600207b
-+#define MASK_VSSEGD  0x1ff0707f
-+#define MATCH_VSSEGH 0x200207b
-+#define MASK_VSSEGH  0x1ff0707f
-+#define MATCH_VSSEGSTB 0x307b
-+#define MASK_VSSEGSTB  0x1e00707f
-+#define MATCH_VSSEGSTD 0x600307b
-+#define MASK_VSSEGSTD  0x1e00707f
-+#define MATCH_VSSEGSTH 0x200307b
-+#define MASK_VSSEGSTH  0x1e00707f
-+#define MATCH_VSSEGSTW 0x400307b
-+#define MASK_VSSEGSTW  0x1e00707f
-+#define MATCH_VSSEGW 0x400207b
-+#define MASK_VSSEGW  0x1ff0707f
-+#define MATCH_VSSTB 0x307b
-+#define MASK_VSSTB  0xfe00707f
-+#define MATCH_VSSTD 0x600307b
-+#define MASK_VSSTD  0xfe00707f
-+#define MATCH_VSSTH 0x200307b
-+#define MASK_VSSTH  0xfe00707f
-+#define MATCH_VSSTW 0x400307b
-+#define MASK_VSSTW  0xfe00707f
-+#define MATCH_VSW 0x400207b
-+#define MASK_VSW  0xfff0707f
-+#define MATCH_VXCPTAUX 0x200402b
-+#define MASK_VXCPTAUX  0xfffff07f
-+#define MATCH_VXCPTCAUSE 0x402b
-+#define MASK_VXCPTCAUSE  0xfffff07f
-+#define MATCH_VXCPTEVAC 0x600302b
-+#define MASK_VXCPTEVAC  0xfff07fff
-+#define MATCH_VXCPTHOLD 0x800302b
-+#define MASK_VXCPTHOLD  0xfff07fff
-+#define MATCH_VXCPTKILL 0x400302b
-+#define MASK_VXCPTKILL  0xffffffff
-+#define MATCH_VXCPTRESTORE 0x200302b
-+#define MASK_VXCPTRESTORE  0xfff07fff
-+#define MATCH_VXCPTSAVE 0x302b
-+#define MASK_VXCPTSAVE  0xfff07fff
-+#define MATCH_WFI 0x10200073
-+#define MASK_WFI  0xffffffff
-+#define MATCH_XOR 0x4033
-+#define MASK_XOR  0xfe00707f
-+#define MATCH_XORI 0x4013
-+#define MASK_XORI  0x707f
-+#define CSR_FFLAGS 0x1
-+#define CSR_FRM 0x2
-+#define CSR_FCSR 0x3
-+#define CSR_CYCLE 0xc00
-+#define CSR_TIME 0xc01
-+#define CSR_INSTRET 0xc02
-+#define CSR_STATS 0xc0
-+#define CSR_UARCH0 0xcc0
-+#define CSR_UARCH1 0xcc1
-+#define CSR_UARCH2 0xcc2
-+#define CSR_UARCH3 0xcc3
-+#define CSR_UARCH4 0xcc4
-+#define CSR_UARCH5 0xcc5
-+#define CSR_UARCH6 0xcc6
-+#define CSR_UARCH7 0xcc7
-+#define CSR_UARCH8 0xcc8
-+#define CSR_UARCH9 0xcc9
-+#define CSR_UARCH10 0xcca
-+#define CSR_UARCH11 0xccb
-+#define CSR_UARCH12 0xccc
-+#define CSR_UARCH13 0xccd
-+#define CSR_UARCH14 0xcce
-+#define CSR_UARCH15 0xccf
-+#define CSR_SSTATUS 0x100
-+#define CSR_STVEC 0x101
-+#define CSR_SIE 0x104
-+#define CSR_SSCRATCH 0x140
-+#define CSR_SEPC 0x141
-+#define CSR_SIP 0x144
-+#define CSR_SPTBR 0x180
-+#define CSR_SASID 0x181
-+#define CSR_CYCLEW 0x900
-+#define CSR_TIMEW 0x901
-+#define CSR_INSTRETW 0x902
-+#define CSR_STIME 0xd01
-+#define CSR_SCAUSE 0xd42
-+#define CSR_SBADADDR 0xd43
-+#define CSR_STIMEW 0xa01
-+#define CSR_MSTATUS 0x300
-+#define CSR_MTVEC 0x301
-+#define CSR_MTDELEG 0x302
-+#define CSR_MIE 0x304
-+#define CSR_MTIMECMP 0x321
-+#define CSR_MSCRATCH 0x340
-+#define CSR_MEPC 0x341
-+#define CSR_MCAUSE 0x342
-+#define CSR_MBADADDR 0x343
-+#define CSR_MIP 0x344
-+#define CSR_MTIME 0x701
-+#define CSR_MCPUID 0xf00
-+#define CSR_MIMPID 0xf01
-+#define CSR_MHARTID 0xf10
-+#define CSR_MTOHOST 0x780
-+#define CSR_MFROMHOST 0x781
-+#define CSR_MRESET 0x782
-+#define CSR_SEND_IPI 0x783
-+#define CSR_CYCLEH 0xc80
-+#define CSR_TIMEH 0xc81
-+#define CSR_INSTRETH 0xc82
-+#define CSR_CYCLEHW 0x980
-+#define CSR_TIMEHW 0x981
-+#define CSR_INSTRETHW 0x982
-+#define CSR_STIMEH 0xd81
-+#define CSR_STIMEHW 0xa81
-+#define CSR_MTIMECMPH 0x361
-+#define CSR_MTIMEH 0x741
-+#define CAUSE_MISALIGNED_FETCH 0x0
-+#define CAUSE_FAULT_FETCH 0x1
-+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
-+#define CAUSE_BREAKPOINT 0x3
-+#define CAUSE_MISALIGNED_LOAD 0x4
-+#define CAUSE_FAULT_LOAD 0x5
-+#define CAUSE_MISALIGNED_STORE 0x6
-+#define CAUSE_FAULT_STORE 0x7
-+#define CAUSE_USER_ECALL 0x8
-+#define CAUSE_SUPERVISOR_ECALL 0x9
-+#define CAUSE_HYPERVISOR_ECALL 0xa
-+#define CAUSE_MACHINE_ECALL 0xb
-+#endif
-+#ifdef DECLARE_INSN
-+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
-+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
-+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
-+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
-+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
-+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
-+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
-+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
-+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
-+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
-+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
-+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
-+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
-+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
-+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
-+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
-+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
-+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
-+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
-+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
-+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
-+DECLARE_INSN(and, MATCH_AND, MASK_AND)
-+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
-+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
-+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
-+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
-+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
-+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
-+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
-+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
-+DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
-+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
-+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
-+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
-+DECLARE_INSN(c_addin, MATCH_C_ADDIN, MASK_C_ADDIN)
-+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
-+DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
-+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
-+DECLARE_INSN(c_andin, MATCH_C_ANDIN, MASK_C_ANDIN)
-+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
-+DECLARE_INSN(c_bgez, MATCH_C_BGEZ, MASK_C_BGEZ)
-+DECLARE_INSN(c_bltz, MATCH_C_BLTZ, MASK_C_BLTZ)
-+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
-+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
-+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
-+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
-+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
-+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
-+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
-+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
-+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
-+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
-+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
-+DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
-+DECLARE_INSN(c_orin, MATCH_C_ORIN, MASK_C_ORIN)
-+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
-+DECLARE_INSN(c_sll, MATCH_C_SLL, MASK_C_SLL)
-+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
-+DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
-+DECLARE_INSN(c_sllr, MATCH_C_SLLR, MASK_C_SLLR)
-+DECLARE_INSN(c_slt, MATCH_C_SLT, MASK_C_SLT)
-+DECLARE_INSN(c_sltr, MATCH_C_SLTR, MASK_C_SLTR)
-+DECLARE_INSN(c_sltu, MATCH_C_SLTU, MASK_C_SLTU)
-+DECLARE_INSN(c_sltur, MATCH_C_SLTUR, MASK_C_SLTUR)
-+DECLARE_INSN(c_sra, MATCH_C_SRA, MASK_C_SRA)
-+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
-+DECLARE_INSN(c_srl, MATCH_C_SRL, MASK_C_SRL)
-+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
-+DECLARE_INSN(c_srlr, MATCH_C_SRLR, MASK_C_SRLR)
-+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
-+DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
-+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
-+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
-+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
-+DECLARE_INSN(c_xorin, MATCH_C_XORIN, MASK_C_XORIN)
-+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
-+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
-+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
-+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
-+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
-+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
-+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
-+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
-+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
-+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
-+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
-+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
-+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
-+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
-+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
-+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
-+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
-+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
-+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
-+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
-+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
-+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
-+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
-+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
-+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
-+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
-+DECLARE_INSN(eret, MATCH_ERET, MASK_ERET)
-+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
-+DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
-+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
-+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
-+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-+DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
-+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
-+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-+DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
-+DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
-+DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
-+DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
-+DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
-+DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
-+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-+DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
-+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-+DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
-+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
-+DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
-+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-+DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
-+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-+DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
-+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
-+DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
-+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
-+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
-+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
-+DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
-+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
-+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-+DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
-+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-+DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
-+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-+DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
-+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-+DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
-+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
-+DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
-+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
-+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
-+DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
-+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
-+DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
-+DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
-+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-+DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
-+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
-+DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
-+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
-+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
-+DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
-+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
-+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-+DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
-+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
-+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
-+DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
-+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-+DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
-+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
-+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
-+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
-+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
-+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
-+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
-+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
-+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
-+DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
-+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
-+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
-+DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
-+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
-+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
-+DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
-+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
-+DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
-+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
-+DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
-+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
-+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
-+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
-+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
-+DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
-+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
-+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-+DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS)
-+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
-+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
-+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
-+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
-+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
-+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
-+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
-+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-+DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
-+DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
-+DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH)
-+DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
-+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
-+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
-+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
-+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
-+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
-+DECLARE_INSN(or, MATCH_OR, MASK_OR)
-+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
-+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
-+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
-+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
-+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
-+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
-+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
-+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
-+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
-+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
-+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
-+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
-+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
-+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
-+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
-+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
-+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
-+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
-+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
-+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
-+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
-+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
-+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
-+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
-+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
-+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
-+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
-+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
-+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
-+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
-+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
-+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
-+DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
-+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
-+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
-+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-+DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
-+DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
-+DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
-+DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
-+DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
-+DECLARE_INSN(vf, MATCH_VF, MASK_VF)
-+DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
-+DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
-+DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
-+DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
-+DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
-+DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
-+DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
-+DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
-+DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
-+DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
-+DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
-+DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
-+DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
-+DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
-+DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
-+DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
-+DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
-+DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
-+DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
-+DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
-+DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
-+DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
-+DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
-+DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
-+DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
-+DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
-+DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
-+DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
-+DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
-+DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
-+DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
-+DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
-+DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
-+DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
-+DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
-+DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
-+DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
-+DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
-+DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
-+DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
-+DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
-+DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
-+DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
-+DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
-+DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
-+DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
-+DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
-+DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
-+DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
-+DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
-+DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
-+DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
-+DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
-+DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
-+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
-+DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
-+DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
-+DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
-+DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
-+DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
-+DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
-+DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
-+DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
-+DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
-+DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
-+DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
-+DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
-+DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
-+DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
-+DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
-+DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
-+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
-+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
-+DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
-+DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
-+DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
-+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
-+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
-+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-+#endif
-+#ifdef DECLARE_CSR
-+DECLARE_CSR(fflags, CSR_FFLAGS)
-+DECLARE_CSR(frm, CSR_FRM)
-+DECLARE_CSR(fcsr, CSR_FCSR)
-+DECLARE_CSR(cycle, CSR_CYCLE)
-+DECLARE_CSR(time, CSR_TIME)
-+DECLARE_CSR(instret, CSR_INSTRET)
-+DECLARE_CSR(stats, CSR_STATS)
-+DECLARE_CSR(uarch0, CSR_UARCH0)
-+DECLARE_CSR(uarch1, CSR_UARCH1)
-+DECLARE_CSR(uarch2, CSR_UARCH2)
-+DECLARE_CSR(uarch3, CSR_UARCH3)
-+DECLARE_CSR(uarch4, CSR_UARCH4)
-+DECLARE_CSR(uarch5, CSR_UARCH5)
-+DECLARE_CSR(uarch6, CSR_UARCH6)
-+DECLARE_CSR(uarch7, CSR_UARCH7)
-+DECLARE_CSR(uarch8, CSR_UARCH8)
-+DECLARE_CSR(uarch9, CSR_UARCH9)
-+DECLARE_CSR(uarch10, CSR_UARCH10)
-+DECLARE_CSR(uarch11, CSR_UARCH11)
-+DECLARE_CSR(uarch12, CSR_UARCH12)
-+DECLARE_CSR(uarch13, CSR_UARCH13)
-+DECLARE_CSR(uarch14, CSR_UARCH14)
-+DECLARE_CSR(uarch15, CSR_UARCH15)
-+DECLARE_CSR(sstatus, CSR_SSTATUS)
-+DECLARE_CSR(stvec, CSR_STVEC)
-+DECLARE_CSR(sie, CSR_SIE)
-+DECLARE_CSR(sscratch, CSR_SSCRATCH)
-+DECLARE_CSR(sepc, CSR_SEPC)
-+DECLARE_CSR(sip, CSR_SIP)
-+DECLARE_CSR(sptbr, CSR_SPTBR)
-+DECLARE_CSR(sasid, CSR_SASID)
-+DECLARE_CSR(cyclew, CSR_CYCLEW)
-+DECLARE_CSR(timew, CSR_TIMEW)
-+DECLARE_CSR(instretw, CSR_INSTRETW)
-+DECLARE_CSR(stime, CSR_STIME)
-+DECLARE_CSR(scause, CSR_SCAUSE)
-+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
-+DECLARE_CSR(stimew, CSR_STIMEW)
-+DECLARE_CSR(mstatus, CSR_MSTATUS)
-+DECLARE_CSR(mtvec, CSR_MTVEC)
-+DECLARE_CSR(mtdeleg, CSR_MTDELEG)
-+DECLARE_CSR(mie, CSR_MIE)
-+DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
-+DECLARE_CSR(mscratch, CSR_MSCRATCH)
-+DECLARE_CSR(mepc, CSR_MEPC)
-+DECLARE_CSR(mcause, CSR_MCAUSE)
-+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
-+DECLARE_CSR(mip, CSR_MIP)
-+DECLARE_CSR(mtime, CSR_MTIME)
-+DECLARE_CSR(mcpuid, CSR_MCPUID)
-+DECLARE_CSR(mimpid, CSR_MIMPID)
-+DECLARE_CSR(mhartid, CSR_MHARTID)
-+DECLARE_CSR(mtohost, CSR_MTOHOST)
-+DECLARE_CSR(mfromhost, CSR_MFROMHOST)
-+DECLARE_CSR(mreset, CSR_MRESET)
-+DECLARE_CSR(send_ipi, CSR_SEND_IPI)
-+DECLARE_CSR(cycleh, CSR_CYCLEH)
-+DECLARE_CSR(timeh, CSR_TIMEH)
-+DECLARE_CSR(instreth, CSR_INSTRETH)
-+DECLARE_CSR(cyclehw, CSR_CYCLEHW)
-+DECLARE_CSR(timehw, CSR_TIMEHW)
-+DECLARE_CSR(instrethw, CSR_INSTRETHW)
-+DECLARE_CSR(stimeh, CSR_STIMEH)
-+DECLARE_CSR(stimehw, CSR_STIMEHW)
-+DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
-+DECLARE_CSR(mtimeh, CSR_MTIMEH)
-+#endif
-+#ifdef DECLARE_CAUSE
-+DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
-+DECLARE_CAUSE("frm", CAUSE_FRM)
-+DECLARE_CAUSE("fcsr", CAUSE_FCSR)
-+DECLARE_CAUSE("cycle", CAUSE_CYCLE)
-+DECLARE_CAUSE("time", CAUSE_TIME)
-+DECLARE_CAUSE("instret", CAUSE_INSTRET)
-+DECLARE_CAUSE("stats", CAUSE_STATS)
-+DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
-+DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
-+DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
-+DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
-+DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
-+DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
-+DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
-+DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
-+DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
-+DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
-+DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
-+DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
-+DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
-+DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
-+DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
-+DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
-+DECLARE_CAUSE("sstatus", CAUSE_SSTATUS)
-+DECLARE_CAUSE("stvec", CAUSE_STVEC)
-+DECLARE_CAUSE("sie", CAUSE_SIE)
-+DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH)
-+DECLARE_CAUSE("sepc", CAUSE_SEPC)
-+DECLARE_CAUSE("sip", CAUSE_SIP)
-+DECLARE_CAUSE("sptbr", CAUSE_SPTBR)
-+DECLARE_CAUSE("sasid", CAUSE_SASID)
-+DECLARE_CAUSE("cyclew", CAUSE_CYCLEW)
-+DECLARE_CAUSE("timew", CAUSE_TIMEW)
-+DECLARE_CAUSE("instretw", CAUSE_INSTRETW)
-+DECLARE_CAUSE("stime", CAUSE_STIME)
-+DECLARE_CAUSE("scause", CAUSE_SCAUSE)
-+DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR)
-+DECLARE_CAUSE("stimew", CAUSE_STIMEW)
-+DECLARE_CAUSE("mstatus", CAUSE_MSTATUS)
-+DECLARE_CAUSE("mtvec", CAUSE_MTVEC)
-+DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG)
-+DECLARE_CAUSE("mie", CAUSE_MIE)
-+DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP)
-+DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH)
-+DECLARE_CAUSE("mepc", CAUSE_MEPC)
-+DECLARE_CAUSE("mcause", CAUSE_MCAUSE)
-+DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR)
-+DECLARE_CAUSE("mip", CAUSE_MIP)
-+DECLARE_CAUSE("mtime", CAUSE_MTIME)
-+DECLARE_CAUSE("mcpuid", CAUSE_MCPUID)
-+DECLARE_CAUSE("mimpid", CAUSE_MIMPID)
-+DECLARE_CAUSE("mhartid", CAUSE_MHARTID)
-+DECLARE_CAUSE("mtohost", CAUSE_MTOHOST)
-+DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST)
-+DECLARE_CAUSE("mreset", CAUSE_MRESET)
-+DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
-+DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
-+DECLARE_CAUSE("timeh", CAUSE_TIMEH)
-+DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
-+DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW)
-+DECLARE_CAUSE("timehw", CAUSE_TIMEHW)
-+DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW)
-+DECLARE_CAUSE("stimeh", CAUSE_STIMEH)
-+DECLARE_CAUSE("stimehw", CAUSE_STIMEHW)
-+DECLARE_CAUSE("mtimecmph", CAUSE_MTIMECMPH)
-+DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH)
-+#endif
-diff -urN empty/gcc/config/riscv/riscv-protos.h gcc-5.2.0/gcc/config/riscv/riscv-protos.h
---- gcc-5.2.0/gcc/config/riscv/riscv-protos.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/riscv-protos.h	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,96 @@
-+/* Definition of RISC-V target for GNU compiler.
-+   Copyright (C) 2011-2014 Free Software Foundation, Inc.
-+   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
-+   Based on MIPS target for GNU compiler.
-+
-+This file is part of GCC.
-+
-+GCC is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 3, or (at your option)
-+any later version.
-+
-+GCC is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with GCC; see the file COPYING3.  If not see
-+<http://www.gnu.org/licenses/>.  */
-+
-+#ifndef GCC_RISCV_PROTOS_H
-+#define GCC_RISCV_PROTOS_H
-+
-+enum riscv_symbol_type {
-+  SYMBOL_ABSOLUTE,
-+  SYMBOL_GOT_DISP,
-+  SYMBOL_TLS,
-+  SYMBOL_TLS_LE,
-+  SYMBOL_TLS_IE,
-+  SYMBOL_TLS_GD
-+};
-+#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
-+
-+enum riscv_code_model {
-+  CM_MEDLOW,
-+  CM_MEDANY,
-+  CM_PIC
-+};
-+extern enum riscv_code_model riscv_cmodel;
-+
-+extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
-+extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
-+extern int riscv_address_insns (rtx, enum machine_mode, bool);
-+extern int riscv_const_insns (rtx);
-+extern int riscv_split_const_insns (rtx);
-+extern int riscv_load_store_insns (rtx, rtx_insn *);
-+extern rtx riscv_emit_move (rtx, rtx);
-+extern bool riscv_split_symbol (rtx, rtx, enum machine_mode, rtx *);
-+extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
-+extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
-+extern bool riscv_legitimize_move (enum machine_mode, rtx, rtx);
-+extern bool riscv_legitimize_vector_move (enum machine_mode, rtx, rtx);
-+
-+extern rtx riscv_subword (rtx, bool);
-+extern bool riscv_split_64bit_move_p (rtx, rtx);
-+extern void riscv_split_doubleword_move (rtx, rtx);
-+extern const char *riscv_output_move (rtx, rtx);
-+extern const char *riscv_output_gpr_save (unsigned);
-+#ifdef RTX_CODE
-+extern void riscv_expand_scc (rtx *);
-+extern void riscv_expand_conditional_branch (rtx *);
-+#endif
-+extern rtx riscv_expand_call (bool, rtx, rtx, rtx);
-+extern void riscv_expand_fcc_reload (rtx, rtx, rtx);
-+extern void riscv_set_return_address (rtx, rtx);
-+extern bool riscv_expand_block_move (rtx, rtx, rtx);
-+extern void riscv_expand_synci_loop (rtx, rtx);
-+
-+extern bool riscv_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT,
-+					       HOST_WIDE_INT);
-+extern bool riscv_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT,
-+						HOST_WIDE_INT);
-+extern void riscv_order_regs_for_local_alloc (void);
-+
-+extern rtx riscv_return_addr (int, rtx);
-+extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
-+extern void riscv_expand_prologue (void);
-+extern void riscv_expand_epilogue (bool);
-+extern bool riscv_can_use_return_insn (void);
-+extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
-+
-+extern enum reg_class riscv_secondary_reload_class (enum reg_class,
-+						   enum machine_mode,
-+						   rtx, bool);
-+extern int riscv_class_max_nregs (enum reg_class, enum machine_mode);
-+
-+extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
-+
-+extern void irix_asm_output_align (FILE *, unsigned);
-+extern const char *current_section_name (void);
-+extern unsigned int current_section_flags (void);
-+
-+extern void riscv_expand_vector_init (rtx, rtx);
-+
-+#endif /* ! GCC_RISCV_PROTOS_H */
-diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
---- gcc-5.2.0/gcc/config/riscv/riscv.c	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/riscv.c	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,4439 @@
++  (match_code "eq,ne,lt,le,gt,ge"))
+diff -urN empty/gcc/config/riscv/riscv.c gcc-5.3.0/gcc/config/riscv/riscv.c
+--- empty/gcc/config/riscv/riscv.c	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/riscv.c	2016-04-02 14:07:12.472438058 +0800
+@@ -0,0 +1,4311 @@
 +/* Subroutines used for code generation for RISC-V.
 +   Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -2919,7 +1256,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +/* The maximum distance between the top of the stack frame and the
 +   value sp has when we save and restore registers.  This is set by the
 +   range  of load/store offsets and must also preserve stack alignment. */
-+#define RISCV_MAX_FIRST_STACK_STEP (RISCV_IMM_REACH/2 - 16)
++#define RISCV_MAX_FIRST_STACK_STEP (IMM_REACH/2 - 16)
 +
 +/* True if INSN is a riscv.md pattern or asm statement.  */
 +#define USEFUL_INSN_P(INSN)						\
@@ -3100,7 +1437,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  unsigned short int_div[2];
 +  unsigned short issue_rate;
 +  unsigned short branch_cost;
-+  unsigned short fp_to_int_cost;
 +  unsigned short memory_cost;
 +};
 +
@@ -3162,7 +1498,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},	/* int_div */
 +  1,						/* issue_rate */
 +  3,						/* branch_cost */
-+  COSTS_N_INSNS (2),				/* fp_to_int_cost */
 +  5						/* memory_cost */
 +};
 +
@@ -3175,7 +1510,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  {COSTS_N_INSNS (1), COSTS_N_INSNS (1)},	/* int_div */
 +  1,						/* issue_rate */
 +  1,						/* branch_cost */
-+  COSTS_N_INSNS (1),				/* fp_to_int_cost */
 +  1						/* memory_cost */
 +};
 +
@@ -3207,7 +1541,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +riscv_build_integer_1 (struct riscv_integer_op *codes, HOST_WIDE_INT value,
 +		       enum machine_mode mode)
 +{
-+  HOST_WIDE_INT low_part = RISCV_CONST_LOW_PART (value);
++  HOST_WIDE_INT low_part = CONST_LOW_PART (value);
 +  int cost = INT_MAX, alt_cost;
 +  struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS];
 +
@@ -3425,13 +1759,13 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +static int riscv_symbol_insns (enum riscv_symbol_type type)
 +{
 +  switch (type)
-+  {
++    {
 +    case SYMBOL_TLS: return 0; /* Depends on the TLS model. */
 +    case SYMBOL_ABSOLUTE: return 2; /* LUI + the reference itself */
 +    case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference itself */
 +    case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference itself */
 +    default: gcc_unreachable();
-+  }
++    }
 +}
 +
 +/* Implement TARGET_LEGITIMATE_CONSTANT_P.  */
@@ -3460,7 +1794,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +    {
 +      /* As an optimization, don't spill symbolic constants that are as
 +	 cheap to rematerialize as to access in the constant pool.  */
-+      if (SMALL_INT (offset) && riscv_symbol_insns (type) > 0)
++      if (SMALL_OPERAND (INTVAL (offset)) && riscv_symbol_insns (type) > 0)
 +	return true;
 +
 +      /* As an optimization, avoid needlessly generate dynamic relocations.  */
@@ -3602,7 +1936,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +      /* Small-integer addresses don't occur very often, but they
 +	 are legitimate if $0 is a valid base register.  */
 +      info->type = ADDRESS_CONST_INT;
-+      return SMALL_INT (x);
++      return SMALL_OPERAND (INTVAL (x));
 +
 +    default:
 +      return false;
@@ -3681,25 +2015,13 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +      if (riscv_symbolic_constant_p (x, &symbol_type))
 +	return riscv_symbol_insns (symbol_type);
 +
-+      /* Otherwise try splitting the constant into a base and offset.
-+	 If the offset is a 16-bit value, we can load the base address
-+	 into a register and then use (D)ADDIU to add in the offset.
-+	 If the offset is larger, we can load the base and offset
-+	 into separate registers and add them together with (D)ADDU.
-+	 However, the latter is only possible before reload; during
-+	 and after reload, we must have the option of forcing the
-+	 constant into the pool instead.  */
++      /* Otherwise try splitting the constant into a base and offset.  */
 +      split_const (x, &x, &offset);
 +      if (offset != 0)
 +	{
 +	  int n = riscv_const_insns (x);
 +	  if (n != 0)
-+	    {
-+	      if (SMALL_INT (offset))
-+		return n + 1;
-+	      else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
-+		return n + 1 + riscv_integer_cost (INTVAL (offset));
-+	    }
++	    return n + riscv_integer_cost (INTVAL (offset));
 +	}
 +      return 0;
 +
@@ -3930,8 +2252,8 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +      /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
 +         The addition inside the macro CONST_HIGH_PART may cause an
 +         overflow, so we need to force a sign-extension check.  */
-+      high = gen_int_mode (RISCV_CONST_HIGH_PART (offset), Pmode);
-+      offset = RISCV_CONST_LOW_PART (offset);
++      high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
++      offset = CONST_LOW_PART (offset);
 +      high = riscv_force_temporary (temp, high);
 +      reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
 +    }
@@ -4555,6 +2877,34 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  if (dbl_p && riscv_split_64bit_move_p (dest, src))
 +    return "#";
 +
++  if (dest_code == REG && GP_REG_P (REGNO (dest)))
++    {
++      if (src_code == REG && FP_REG_P (REGNO (src)))
++	return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1";
++
++      if (src_code == MEM)
++	switch (GET_MODE_SIZE (mode))
++	  {
++	  case 1: return "lbu\t%0,%1";
++	  case 2: return "lhu\t%0,%1";
++	  case 4: return "lw\t%0,%1";
++	  case 8: return "ld\t%0,%1";
++	  }
++
++      if (src_code == CONST_INT)
++	return "li\t%0,%1";
++
++      if (src_code == HIGH)
++	return "lui\t%0,%h1";
++
++      if (symbolic_operand (src, VOIDmode))
++	switch (riscv_classify_symbolic_expression (src))
++	  {
++	  case SYMBOL_GOT_DISP: return "la\t%0,%1";
++	  case SYMBOL_ABSOLUTE: return "lla\t%0,%1";
++	  default: gcc_unreachable();
++	  }
++    }
 +  if ((src_code == REG && GP_REG_P (REGNO (src)))
 +      || (src == CONST0_RTX (mode)))
 +    {
@@ -4583,37 +2933,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +	  case 8: return "sd\t%z1,%0";
 +	  }
 +    }
-+  if (dest_code == REG && GP_REG_P (REGNO (dest)))
-+    {
-+      if (src_code == REG)
-+	{
-+	  if (FP_REG_P (REGNO (src)))
-+	    return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1";
-+	}
-+
-+      if (src_code == MEM)
-+	switch (GET_MODE_SIZE (mode))
-+	  {
-+	  case 1: return "lbu\t%0,%1";
-+	  case 2: return "lhu\t%0,%1";
-+	  case 4: return "lw\t%0,%1";
-+	  case 8: return "ld\t%0,%1";
-+	  }
-+
-+      if (src_code == CONST_INT)
-+	return "li\t%0,%1";
-+
-+      if (src_code == HIGH)
-+	return "lui\t%0,%h1";
-+
-+      if (symbolic_operand (src, VOIDmode))
-+	switch (riscv_classify_symbolic_expression (src))
-+	  {
-+	  case SYMBOL_GOT_DISP: return "la\t%0,%1";
-+	  case SYMBOL_ABSOLUTE: return "lla\t%0,%1";
-+	  default: gcc_unreachable();
-+	  }
-+    }
 +  if (src_code == REG && FP_REG_P (REGNO (src)))
 +    {
 +      if (dest_code == REG && FP_REG_P (REGNO (dest)))
@@ -5409,7 +3728,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +
 +  if (!call_insn_operand (addr, VOIDmode))
 +    {
-+      rtx reg = RISCV_EPILOGUE_TEMP (Pmode);
++      rtx reg = RISCV_PROLOGUE_TEMP (Pmode);
 +      riscv_emit_move (reg, addr);
 +      addr = reg;
 +    }
@@ -5642,15 +3961,20 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +    {
 +      case MEMMODEL_ACQ_REL:
 +      case MEMMODEL_SEQ_CST:
++      case MEMMODEL_SYNC_SEQ_CST:
 +	return ".sc";
 +      case MEMMODEL_ACQUIRE:
 +      case MEMMODEL_CONSUME:
++      case MEMMODEL_SYNC_ACQUIRE:
 +	return ".aq";
 +      case MEMMODEL_RELEASE:
++      case MEMMODEL_SYNC_RELEASE:
 +	return ".rl";
 +      case MEMMODEL_RELAXED:
 +	return "";
-+      default: gcc_unreachable();
++      default:
++        fprintf(stderr, "riscv_memory_model_suffix(%ld)\n", model);
++        gcc_unreachable();
 +    }
 +}
 +
@@ -5790,7 +4114,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +      if (strncmp (s->named.name, ".rodata.cst", strlen (".rodata.cst")) == 0)
 +	{
 +	  /* Rename .rodata.cst* to .srodata.cst*. */
-+	  char name[32];
++	  char *name = (char *) alloca (strlen (s->named.name) + 2);
 +	  sprintf (name, ".s%s", s->named.name + 1);
 +	  return get_section (name, s->named.common.flags, NULL);
 +	}
@@ -5953,7 +4277,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +      frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
 +
 +  /* Find out which FPRs we need to save.  This loop must iterate over
-+     the same space as its companion in riscv_for_each_saved_gpr_and_fpr.  */
++     the same space as its companion in riscv_for_each_saved_reg.  */
 +  if (TARGET_HARD_FLOAT)
 +    for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
 +      if (riscv_save_reg_p (regno))
@@ -6086,8 +4410,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +   of the frame.  */
 +
 +static void
-+riscv_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
-+				 riscv_save_restore_fn fn)
++riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn)
 +{
 +  HOST_WIDE_INT offset;
 +  int regno;
@@ -6112,49 +4435,21 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +      }
 +}
 +
-+/* Emit a move from SRC to DEST, given that one of them is a register
-+   save slot and that the other is a register.  TEMP is a temporary
-+   GPR of the same mode that is available if need be.  */
++/* Save register REG to MEM.  Make the instruction frame-related.  */
 +
 +static void
-+riscv_emit_save_slot_move (rtx dest, rtx src, rtx temp)
++riscv_save_reg (rtx reg, rtx mem)
 +{
-+  unsigned int regno;
-+  rtx mem;
-+  enum reg_class rclass;
-+
-+  if (REG_P (src))
-+    {
-+      regno = REGNO (src);
-+      mem = dest;
-+    }
-+  else
-+    {
-+      regno = REGNO (dest);
-+      mem = src;
-+    }
-+
-+  rclass = riscv_secondary_reload_class (REGNO_REG_CLASS (regno),
-+					 GET_MODE (mem), mem, mem == src);
-+
-+  if (rclass == NO_REGS)
-+    riscv_emit_move (dest, src);
-+  else
-+    {
-+      gcc_assert (!reg_overlap_mentioned_p (dest, temp));
-+      riscv_emit_move (temp, src);
-+      riscv_emit_move (dest, temp);
-+    }
-+  if (MEM_P (dest))
-+    riscv_set_frame_expr (riscv_frame_set (dest, src));
++  riscv_emit_move (mem, reg);
++  riscv_set_frame_expr (riscv_frame_set (mem, reg));
 +}
 +
-+/* Save register REG to MEM.  Make the instruction frame-related.  */
++/* Restore register REG from MEM.  */
 +
 +static void
-+riscv_save_reg (rtx reg, rtx mem)
++riscv_restore_reg (rtx reg, rtx mem)
 +{
-+  riscv_emit_save_slot_move (mem, reg, RISCV_PROLOGUE_TEMP (GET_MODE (reg)));
++  riscv_emit_move (reg, mem);
 +}
 +
 +/* Return the code to invoke the GPR save routine.  */
@@ -6219,7 +4514,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +			    GEN_INT (-step1));
 +      RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
 +      size -= step1;
-+      riscv_for_each_saved_gpr_and_fpr (size, riscv_save_reg);
++      riscv_for_each_saved_reg (size, riscv_save_reg);
 +    }
 +
 +  frame->mask = mask; /* Undo the above fib.  */
@@ -6236,33 +4531,25 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  if (size > 0)
 +    {
 +      if (SMALL_OPERAND (-size))
-+	emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
-+				  GEN_INT (-size)));
++	{
++	  insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
++				GEN_INT (-size));
++	  RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
++	}
 +      else
 +	{
 +	  riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-size));
 +	  emit_insn (gen_add3_insn (stack_pointer_rtx,
 +				    stack_pointer_rtx,
 +				    RISCV_PROLOGUE_TEMP (Pmode)));
-+	}
-+    }
 +
-+  if (frame->total_size > 0)
-+    {
-+      /* Describe the effect of the instructions that adjusted sp.  */
-+      insn = plus_constant (Pmode, stack_pointer_rtx, -frame->total_size);
-+      insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx, insn);
-+      riscv_set_frame_expr (insn);
++	  /* Describe the effect of the previous instructions.  */
++	  insn = plus_constant (Pmode, stack_pointer_rtx, -size);
++	  insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx, insn);
++	  riscv_set_frame_expr (insn);
++	}
 +    }
 +}
-+
-+/* Emit instructions to restore register REG from slot MEM.  */
-+
-+static void
-+riscv_restore_reg (rtx reg, rtx mem)
-+{
-+  riscv_emit_save_slot_move (reg, mem, RISCV_EPILOGUE_TEMP (GET_MODE (reg)));
-+}
 +
 +/* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
 +   says which.  */
@@ -6292,13 +4579,14 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  if (cfun->calls_alloca)
 +    {
 +      rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset);
-+      if (!SMALL_INT (adjust))
++      if (!SMALL_OPERAND (INTVAL (adjust)))
 +	{
-+	  riscv_emit_move (RISCV_EPILOGUE_TEMP (Pmode), adjust);
-+	  adjust = RISCV_EPILOGUE_TEMP (Pmode);
++	  riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
++	  adjust = RISCV_PROLOGUE_TEMP (Pmode);
 +	}
 +
-+      emit_insn (gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, adjust));
++      emit_insn (gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx,
++				adjust));
 +    }
 +
 +  /* If we need to restore registers, deallocate as much stack as
@@ -6316,8 +4604,8 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +      rtx adjust = GEN_INT (step1);
 +      if (!SMALL_OPERAND (step1))
 +	{
-+	  riscv_emit_move (RISCV_EPILOGUE_TEMP (Pmode), adjust);
-+	  adjust = RISCV_EPILOGUE_TEMP (Pmode);
++	  riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
++	  adjust = RISCV_PROLOGUE_TEMP (Pmode);
 +	}
 +
 +      emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
@@ -6327,8 +4615,7 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +    frame->mask = 0; /* Temporarily fib that we need not save GPRs.  */
 +
 +  /* Restore the registers.  */
-+  riscv_for_each_saved_gpr_and_fpr (frame->total_size - step2,
-+				    riscv_restore_reg);
++  riscv_for_each_saved_reg (frame->total_size - step2, riscv_restore_reg);
 +
 +  if (use_restore_libcall)
 +    {
@@ -6368,6 +4655,15 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  return reload_completed && cfun->machine->frame.total_size == 0;
 +}
 +
++/* Implement TARGET_REGISTER_MOVE_COST.  */
++
++static int
++riscv_register_move_cost (enum machine_mode mode,
++			  reg_class_t from, reg_class_t to)
++{
++  return SECONDARY_MEMORY_NEEDED (from, to, mode) ? 8 : 2;
++}
++
 +/* Return true if register REGNO can store a value of mode MODE.
 +   The result of this function is cached in riscv_hard_regno_mode_ok.  */
 +
@@ -6414,25 +4710,18 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
 +}
 +
-+/* Implement CLASS_MAX_NREGS, taking the maximum of the cases
-+   in riscv_hard_regno_nregs.  */
++/* Implement CLASS_MAX_NREGS.  */
 +
-+int
-+riscv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
++static unsigned char
++riscv_class_max_nregs (reg_class_t rclass, enum machine_mode mode)
 +{
-+  int size;
-+  HARD_REG_SET left;
++  if (reg_class_subset_p (FP_REGS, rclass))
++    return riscv_hard_regno_nregs (FP_REG_FIRST, mode);
 +
-+  size = 0x8000;
-+  COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
-+  if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
-+    {
-+      size = MIN (size, UNITS_PER_FPREG);
-+      AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
-+    }
-+  if (!hard_reg_set_empty_p (left))
-+    size = MIN (size, UNITS_PER_WORD);
-+  return (GET_MODE_SIZE (mode) + size - 1) / size;
++  if (reg_class_subset_p (GR_REGS, rclass))
++    return riscv_hard_regno_nregs (GP_REG_FIRST, mode);
++
++  return 0;
 +}
 +
 +/* Implement TARGET_PREFERRED_RELOAD_CLASS.  */
@@ -6445,40 +4734,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +	 rclass;
 +}
 +
-+/* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
-+   Return a "canonical" class to represent it in later calculations.  */
-+
-+static reg_class_t
-+riscv_canonicalize_move_class (reg_class_t rclass)
-+{
-+  if (reg_class_subset_p (rclass, GENERAL_REGS))
-+    rclass = GENERAL_REGS;
-+
-+  return rclass;
-+}
-+
-+/* Implement TARGET_REGISTER_MOVE_COST.  Return 0 for classes that are the
-+   maximum of the move costs for subclasses; regclass will work out
-+   the maximum for us.  */
-+
-+static int
-+riscv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
-+			 reg_class_t from, reg_class_t to)
-+{
-+  from = riscv_canonicalize_move_class (from);
-+  to = riscv_canonicalize_move_class (to);
-+
-+  if ((from == GENERAL_REGS && to == GENERAL_REGS)
-+      || (from == GENERAL_REGS && to == FP_REGS)
-+      || (from == FP_REGS && to == FP_REGS))
-+    return COSTS_N_INSNS (1);
-+
-+  if (from == FP_REGS && to == GENERAL_REGS)
-+    return tune_info->fp_to_int_cost;
-+
-+  return 0;
-+}
-+
 +/* Implement TARGET_MEMORY_MOVE_COST.  */
 +
 +static int
@@ -6488,48 +4743,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +	  + memory_move_secondary_cost (mode, rclass, in));
 +} 
 +
-+/* Return the register class required for a secondary register when
-+   copying between one of the registers in RCLASS and value X, which
-+   has mode MODE.  X is the source of the move if IN_P, otherwise it
-+   is the destination.  Return NO_REGS if no secondary register is
-+   needed.  */
-+
-+enum reg_class
-+riscv_secondary_reload_class (enum reg_class rclass,
-+			     enum machine_mode mode, rtx x,
-+			     bool in_p ATTRIBUTE_UNUSED)
-+{
-+  int regno;
-+
-+  regno = true_regnum (x);
-+
-+  if (reg_class_subset_p (rclass, FP_REGS))
-+    {
-+      if (MEM_P (x) && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
-+	/* We can use flw/fld/fsw/fsd. */
-+	return NO_REGS;
-+
-+      if (GP_REG_P (regno) || x == CONST0_RTX (mode))
-+	/* We can use fmv or go through memory when mode > Pmode. */
-+	return NO_REGS;
-+
-+      if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
-+	/* We can force the constant to memory and use flw/fld. */
-+	return NO_REGS;
-+
-+      if (FP_REG_P (regno))
-+	/* We can use fmv.fmt. */
-+	return NO_REGS;
-+
-+      /* Otherwise, we need to reload through an integer register.  */
-+      return GR_REGS;
-+    }
-+  if (FP_REG_P (regno))
-+    return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
-+
-+  return NO_REGS;
-+}
-+
 +/* Implement TARGET_MODE_REP_EXTENDED.  */
 +
 +static int
@@ -6554,18 +4767,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  return default_scalar_mode_supported_p (mode);
 +}
 +
-+/* Implement TARGET_SCHED_ADJUST_COST.  We assume that anti and output
-+   dependencies have no cost. */
-+
-+static int
-+riscv_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link,
-+		   rtx_insn *dep ATTRIBUTE_UNUSED, int cost)
-+{
-+  if (REG_NOTE_KIND (link) != 0)
-+    return 0;
-+  return cost;
-+}
-+
 +/* Return the number of instructions that can be issued per cycle.  */
 +
 +static int
@@ -7021,13 +5222,25 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +    }
 +}
 +
++/* Return a register priority for hard reg REGNO.  */
++static int
++riscv_register_priority (int regno)
++{
++  /* Favor x8-x15/f8-f15 to improve the odds of RVC instruction selection.  */
++  if (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
++		     || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)))
++    return 1;
++
++  return 0;
++}
++
 +/* Implement TARGET_TRAMPOLINE_INIT.  */
 +
 +static void
 +riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
 +{
 +  rtx addr, end_addr, mem;
-+  rtx trampoline[4];
++  uint32_t trampoline[4];
 +  unsigned int i;
 +  HOST_WIDE_INT static_chain_offset, target_function_offset;
 +
@@ -7041,30 +5254,27 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  addr = force_reg (Pmode, XEXP (m_tramp, 0));
 +  end_addr = riscv_force_binary (Pmode, PLUS, addr, GEN_INT (TRAMPOLINE_CODE_SIZE));
 +
-+#define OP(X) gen_int_mode (X, SImode)
-+#define MATCH_LREG ((Pmode) == DImode ? MATCH_LD : MATCH_LW)
-+
 +  /* auipc   t0, 0
 +     l[wd]   t1, target_function_offset(t0)
-+     l[wd]   $static_chain, static_chain_offset(t0)
++     l[wd]   t0, static_chain_offset(t0)
 +     jr      t1
 +  */
-+
-+  trampoline[0] = OP (RISCV_UTYPE (AUIPC, STATIC_CHAIN_REGNUM, 0));
-+  trampoline[1] = OP (RISCV_ITYPE (LREG, RISCV_PROLOGUE_TEMP_REGNUM,
-+		    STATIC_CHAIN_REGNUM, target_function_offset));
-+  trampoline[2] = OP (RISCV_ITYPE (LREG, STATIC_CHAIN_REGNUM,
-+		    STATIC_CHAIN_REGNUM, static_chain_offset));
-+  trampoline[3] = OP (RISCV_ITYPE (JALR, 0, RISCV_PROLOGUE_TEMP_REGNUM, 0));
-+
-+#undef MATCH_LREG
-+#undef OP
-+
-+  /* Copy the trampoline code.  Leave any padding uninitialized.  */
++  trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD);
++  trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW)
++		  | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD)
++		  | (STATIC_CHAIN_REGNUM << SHIFT_RS1)
++		  | (target_function_offset << SHIFT_IMM);
++  trampoline[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW)
++		  | (STATIC_CHAIN_REGNUM << SHIFT_RD)
++		  | (STATIC_CHAIN_REGNUM << SHIFT_RS1)
++		  | (static_chain_offset << SHIFT_IMM);
++  trampoline[3] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1);
++
++  /* Copy the trampoline code.  */
 +  for (i = 0; i < ARRAY_SIZE (trampoline); i++)
 +    {
 +      mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode));
-+      riscv_emit_move (mem, trampoline[i]);
++      riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode));
 +    }
 +
 +  /* Set up the static chain pointer field.  */
@@ -7083,7 +5293,8 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +/* Implement TARGET_FUNCTION_OK_FOR_SIBCALL.  */
 +
 +static bool
-+riscv_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
++riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
++			       tree exp ATTRIBUTE_UNUSED)
 +{
 +  if (TARGET_SAVE_RESTORE)
 +    {
@@ -7097,12 +5308,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +  return true;
 +}
 +
-+static bool
-+riscv_lra_p (void)
-+{
-+  return riscv_lra_flag;
-+}
-+
 +/* Initialize the GCC target structure.  */
 +#undef TARGET_ASM_ALIGNED_HI_OP
 +#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -7117,8 +5322,6 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +#undef TARGET_LEGITIMIZE_ADDRESS
 +#define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
 +
-+#undef TARGET_SCHED_ADJUST_COST
-+#define TARGET_SCHED_ADJUST_COST riscv_adjust_cost
 +#undef TARGET_SCHED_ISSUE_RATE
 +#define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
 +
@@ -7215,6 +5418,9 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +#undef TARGET_CONDITIONAL_REGISTER_USAGE
 +#define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
 +
++#undef TARGET_CLASS_MAX_NREGS
++#define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
++
 +#undef TARGET_TRAMPOLINE_INIT
 +#define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
 +
@@ -7225,21 +5431,67 @@ diff -urN empty/gcc/config/riscv/riscv.c gcc-5.2.0/gcc/config/riscv/riscv.c
 +#define TARGET_ASM_SELECT_RTX_SECTION  riscv_elf_select_rtx_section
 +
 +#undef TARGET_MIN_ANCHOR_OFFSET
-+#define TARGET_MIN_ANCHOR_OFFSET (-RISCV_IMM_REACH/2)
++#define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
 +
 +#undef TARGET_MAX_ANCHOR_OFFSET
-+#define TARGET_MAX_ANCHOR_OFFSET (RISCV_IMM_REACH/2-1)
++#define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
 +
 +#undef TARGET_LRA_P
-+#define TARGET_LRA_P riscv_lra_p
++#define TARGET_LRA_P hook_bool_void_true
++
++#undef TARGET_REGISTER_PRIORITY
++#define TARGET_REGISTER_PRIORITY riscv_register_priority
 +
 +struct gcc_target targetm = TARGET_INITIALIZER;
 +
 +#include "gt-riscv.h"
-diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
---- gcc-5.2.0/gcc/config/riscv/riscv.h	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/riscv.h	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,1109 @@
+diff -urN empty/gcc/config/riscv/riscv-ftypes.def gcc-5.3.0/gcc/config/riscv/riscv-ftypes.def
+--- empty/gcc/config/riscv/riscv-ftypes.def	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/riscv-ftypes.def	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,39 @@
++/* Definitions of prototypes for RISC-V built-in functions.
++   Copyright (C) 2011-2014 Free Software Foundation, Inc.
++   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++   Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++/* Invoke DEF_RISCV_FTYPE (NARGS, LIST) for each prototype used by
++   MIPS built-in functions, where:
++
++      NARGS is the number of arguments.
++      LIST contains the return-type code followed by the codes for each
++        argument type.
++
++   Argument- and return-type codes are either modes or one of the following:
++
++      VOID for void_type_node
++      INT for integer_type_node
++      POINTER for ptr_type_node
++
++   (we don't use PTR because that's a ANSI-compatibillity macro).
++
++   Please keep this list lexicographically sorted by the LIST argument.  */
++
++DEF_RISCV_FTYPE (1, (VOID, VOID))
+diff -urN empty/gcc/config/riscv/riscv.h gcc-5.3.0/gcc/config/riscv/riscv.h
+--- empty/gcc/config/riscv/riscv.h	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/riscv.h	2016-04-02 14:07:12.472438058 +0800
+@@ -0,0 +1,1079 @@
 +/* Definition of RISC-V target for GNU compiler.
 +   Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -7272,20 +5524,24 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +#define TARGET_CPU_CPP_BUILTINS()					\
 +  do									\
 +    {									\
-+      builtin_assert ("machine=riscv");                        	        \
++      builtin_assert ("machine=riscv");					\
 +									\
 +      builtin_assert ("cpu=riscv");					\
-+      builtin_define ("__riscv__");     				\
-+      builtin_define ("__riscv");     					\
++      builtin_define ("__riscv__");					\
++      builtin_define ("__riscv");					\
 +      builtin_define ("_riscv");					\
++      builtin_define ("__riscv");					\
 +									\
 +      if (TARGET_64BIT)							\
 +	{								\
 +	  builtin_define ("__riscv64");					\
-+	  builtin_define ("_RISCV_SIM=_ABI64");			        \
++	  builtin_define ("_RISCV_SIM=_ABI64");				\
++	}								\
++      else								\
++	{								\
++	  builtin_define ("__riscv32");					\
++	  builtin_define ("_RISCV_SIM=_ABI32");				\
 +	}								\
-+      else						        	\
-+	builtin_define ("_RISCV_SIM=_ABI32");			        \
 +									\
 +      builtin_define ("_ABI32=1");					\
 +      builtin_define ("_ABI64=3");					\
@@ -7294,52 +5550,31 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +      builtin_define_with_int_value ("_RISCV_SZINT", INT_TYPE_SIZE);	\
 +      builtin_define_with_int_value ("_RISCV_SZLONG", LONG_TYPE_SIZE);	\
 +      builtin_define_with_int_value ("_RISCV_SZPTR", POINTER_SIZE);	\
-+      builtin_define_with_int_value ("_RISCV_FPSET", 32);		\
 +									\
-+      if (TARGET_ATOMIC) {                                              \
-+        builtin_define ("__riscv_atomic");                              \
-+      }                                                                 \
-+                                                                        \
-+      /* These defines reflect the ABI in use, not whether the  	\
-+	 FPU is directly accessible.  */				\
-+      if (TARGET_HARD_FLOAT_ABI) {					\
-+	builtin_define ("__riscv_hard_float");				\
-+	if (TARGET_FDIV) {						\
-+	  builtin_define ("__riscv_fdiv");				\
-+	  builtin_define ("__riscv_fsqrt");				\
++      if (TARGET_RVC)							\
++	builtin_define ("__riscv_compressed");				\
++									\
++      if (TARGET_ATOMIC)						\
++	builtin_define ("__riscv_atomic");				\
++									\
++      if (TARGET_MULDIV)						\
++	builtin_define ("__riscv_muldiv");				\
++									\
++      if (TARGET_HARD_FLOAT_ABI)					\
++	{								\
++	  builtin_define ("__riscv_hard_float");			\
++	  if (TARGET_FDIV)						\
++	    {								\
++	      builtin_define ("__riscv_fdiv");				\
++	      builtin_define ("__riscv_fsqrt");				\
++	    }								\
 +	}								\
-+      } else								\
++      else								\
 +	builtin_define ("__riscv_soft_float");				\
 +									\
 +      /* The base RISC-V ISA is always little-endian. */		\
 +      builtin_define_std ("RISCVEL");					\
-+      builtin_define ("_RISCVEL");					\
 +									\
-+      /* Macros dependent on the C dialect.  */				\
-+      if (preprocessing_asm_p ())					\
-+	{								\
-+	  builtin_define_std ("LANGUAGE_ASSEMBLY");			\
-+	  builtin_define ("_LANGUAGE_ASSEMBLY");			\
-+	}								\
-+      else if (c_dialect_cxx ())					\
-+	{								\
-+	  builtin_define ("_LANGUAGE_C_PLUS_PLUS");			\
-+	  builtin_define ("__LANGUAGE_C_PLUS_PLUS");			\
-+	  builtin_define ("__LANGUAGE_C_PLUS_PLUS__");			\
-+	}								\
-+      else								\
-+	{								\
-+	  builtin_define_std ("LANGUAGE_C");				\
-+	  builtin_define ("_LANGUAGE_C");				\
-+	}								\
-+      if (c_dialect_objc ())						\
-+	{								\
-+	  builtin_define ("_LANGUAGE_OBJECTIVE_C");			\
-+	  builtin_define ("__LANGUAGE_OBJECTIVE_C");			\
-+	  /* Bizarre, but needed at least for Irix.  */			\
-+	  builtin_define_std ("LANGUAGE_C");				\
-+	  builtin_define ("_LANGUAGE_C");				\
-+	}								\
 +      if (riscv_cmodel == CM_MEDANY)					\
 +	builtin_define ("_RISCV_CMODEL_MEDANY");			\
 +    }									\
@@ -7411,7 +5646,8 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +#define ASM_SPEC "\
 +%(subtarget_asm_debugging_spec) \
 +%{m32} %{m64} %{!m32:%{!m64: %(asm_abi_default_spec)}} \
-+%{mrvc} \
++%{mrvc} %{mno-rvc} \
++%{msoft-float} %{mhard-float} \
 +%{fPIC|fpic|fPIE|fpie:-fpic} \
 +%{march=*} \
 +%(subtarget_asm_spec)"
@@ -7492,10 +5728,6 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +/* We currently require both or neither of the `F' and `D' extensions. */
 +#define UNITS_PER_FPREG 8
 +
-+/* If FP regs aren't wide enough for a given FP argument, it is passed in
-+   integer registers. */
-+#define MIN_FPRS_PER_FMT 1
-+
 +/* The largest size of value that can be held in floating-point
 +   registers and moved with a single instruction.  */
 +#define UNITS_PER_HWFPVALUE \
@@ -7628,11 +5860,11 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +   Extensions of pointers to word_mode must be signed.  */
 +#define POINTERS_EXTEND_UNSIGNED false
 +
-+/* RV32 double-precision FP <-> integer moves go through memory */
-+#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
-+ (!TARGET_64BIT && GET_MODE_SIZE (MODE) == 8 && \
-+   (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
-+   || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS)))
++/* When floating-point registers are wider than integer ones, moves between
++   them must go through memory.  */
++#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE)	\
++  (GET_MODE_SIZE (MODE) > UNITS_PER_WORD		\
++   && ((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS))
 +
 +/* Define if loading short immediate values into registers sign extends.  */
 +#define SHORT_IMMEDIATES_SIGN_EXTEND
@@ -7753,10 +5985,7 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +   the frame pointer, the EH stack adjustment, or the EH data registers. */
 +
 +#define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
-+#define RISCV_EPILOGUE_TEMP_REGNUM RISCV_PROLOGUE_TEMP_REGNUM
-+
 +#define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
-+#define RISCV_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_EPILOGUE_TEMP_REGNUM)
 +
 +#define FUNCTION_PROFILER(STREAM, LABELNO)	\
 +{						\
@@ -7791,6 +6020,7 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +{
 +  NO_REGS,			/* no registers in set */
 +  T_REGS,			/* registers used by indirect sibcalls */
++  JALR_REGS,			/* registers used by indirect calls */
 +  GR_REGS,			/* integer registers */
 +  FP_REGS,			/* floating point registers */
 +  FRAME_REGS,			/* $arg and $frame */
@@ -7810,6 +6040,7 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +{									\
 +  "NO_REGS",								\
 +  "T_REGS",								\
++  "JALR_REGS",								\
 +  "GR_REGS",								\
 +  "FP_REGS",								\
 +  "FRAME_REGS",								\
@@ -7830,7 +6061,8 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +#define REG_CLASS_CONTENTS									\
 +{												\
 +  { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
-+  { 0xf00000e0, 0x00000000, 0x00000000 },	/* T_REGS */		\
++  { 0xf0000040, 0x00000000, 0x00000000 },	/* T_REGS */		\
++  { 0xffffff40, 0x00000000, 0x00000000 },	/* JALR_REGS */		\
 +  { 0xffffffff, 0x00000000, 0x00000000 },	/* GR_REGS */		\
 +  { 0x00000000, 0xffffffff, 0x00000000 },	/* FP_REGS */		\
 +  { 0x00000000, 0x00000000, 0x00000003 },	/* FRAME_REGS */	\
@@ -7864,13 +6096,13 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +#define REG_ALLOC_ORDER							\
 +{ \
 +  /* Call-clobbered GPRs.  */						\
-+  15, 14, 13, 12, 11, 10, 16, 17, 5, 6, 7, 28, 29, 30, 31, 1,		\
++  15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,		\
 +  /* Call-saved GPRs.  */						\
 +  8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,	       			\
 +  /* GPRs that can never be exposed to the register allocator.  */	\
 +  0, 2, 3, 4,								\
 +  /* Call-clobbered FPRs.  */						\
-+  32, 33, 34, 35, 36, 37, 38, 39, 42, 43, 44, 45, 46, 47, 48, 49,	\
++  47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,	\
 +  60, 61, 62, 63,							\
 +  /* Call-saved FPRs.  */						\
 +  40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,			\
@@ -7879,40 +6111,16 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +  64, 65								\
 +}
 +
-+/* True if VALUE is a signed 16-bit number.  */
++/* True if VALUE is a signed 12-bit number.  */
 +
-+#include "opcode-riscv.h"
 +#define SMALL_OPERAND(VALUE) \
-+  ((unsigned HOST_WIDE_INT) (VALUE) + RISCV_IMM_REACH/2 < RISCV_IMM_REACH)
++  ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 +
 +/* True if VALUE can be loaded into a register using LUI.  */
 +
-+#define LUI_OPERAND(VALUE)					\
-+  (((VALUE) | ((1UL<<31) - RISCV_IMM_REACH)) == ((1UL<<31) - RISCV_IMM_REACH) \
-+   || ((VALUE) | ((1UL<<31) - RISCV_IMM_REACH)) + RISCV_IMM_REACH == 0)
-+
-+/* Return a value X with the low 16 bits clear, and such that
-+   VALUE - X is a signed 16-bit value.  */
-+
-+#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
-+#define LUI_INT(X) LUI_OPERAND (INTVAL (X))
-+
-+/* The HI and LO registers can only be reloaded via the general
-+   registers.  Condition code registers can only be loaded to the
-+   general registers, and from the floating point registers.  */
-+
-+#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)			\
-+  riscv_secondary_reload_class (CLASS, MODE, X, true)
-+#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)			\
-+  riscv_secondary_reload_class (CLASS, MODE, X, false)
-+
-+/* Return the maximum number of consecutive registers
-+   needed to represent mode MODE in a register of class CLASS.  */
-+
-+#define CLASS_MAX_NREGS(CLASS, MODE) riscv_class_max_nregs (CLASS, MODE)
-+
-+/* It is undefined to interpret an FP register in a different format than
-+   that which it was created to be. */
++#define LUI_OPERAND(VALUE)						\
++  (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)	\
++   || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 +
 +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
 +  reg_classes_intersect_p (FP_REGS, CLASS)
@@ -8349,10 +6557,24 @@ diff -urN empty/gcc/config/riscv/riscv.h gcc-5.2.0/gcc/config/riscv/riscv.h
 +
 +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 +  (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
-diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
---- gcc-5.2.0/gcc/config/riscv/riscv.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/riscv.md	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,2448 @@
++
++/* ISA constants needed for code generation.  */
++#define OPCODE_LW    0x2003
++#define OPCODE_LD    0x3003
++#define OPCODE_AUIPC 0x17
++#define OPCODE_JALR  0x67
++#define SHIFT_RD  7
++#define SHIFT_RS1 15
++#define SHIFT_IMM 20
++#define IMM_BITS 12
++
++#define IMM_REACH (1LL << IMM_BITS)
++#define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
++#define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
+diff -urN empty/gcc/config/riscv/riscv.md gcc-5.3.0/gcc/config/riscv/riscv.md
+--- empty/gcc/config/riscv/riscv.md	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/riscv.md	2016-04-02 14:07:12.472438058 +0800
+@@ -0,0 +1,2421 @@
 +;; Machine description for RISC-V for GNU compiler.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -8419,11 +6641,6 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +(define_attr "got" "unset,xgot_high,load"
 +  (const_string "unset"))
 +
-+;; For jal instructions, this attribute is DIRECT when the target address
-+;; is symbolic and INDIRECT when it is a register.
-+(define_attr "jal" "unset,direct,indirect"
-+  (const_string "unset"))
-+
 +;; Classification of moves, extensions and truncations.  Most values
 +;; are as for "type" (see below) but there are also the following
 +;; move-specific values:
@@ -8440,9 +6657,6 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +   const,logical,arith,andi,shift_shift"
 +  (const_string "unknown"))
 +
-+(define_attr "alu_type" "unknown,add,sub,and,or,xor"
-+  (const_string "unknown"))
-+
 +;; Main data type used by the insn
 +(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
 +  (const_string "unknown"))
@@ -8464,10 +6678,8 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +;; call		unconditional call
 +;; load		load instruction(s)
 +;; fpload	floating point load
-+;; fpidxload    floating point indexed load
 +;; store	store instruction(s)
 +;; fpstore	floating point store
-+;; fpidxstore	floating point indexed store
 +;; mtc		transfer to coprocessor
 +;; mfc		transfer from coprocessor
 +;; const	load constant
@@ -8490,15 +6702,10 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +;; nop		no operation
 +;; ghost	an instruction that produces no real code
 +(define_attr "type"
-+  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
++  "unknown,branch,jump,call,load,fpload,store,fpstore,
 +   mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
 +   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,nop,ghost"
-+  (cond [(eq_attr "jal" "!unset") (const_string "call")
-+	 (eq_attr "got" "load") (const_string "load")
-+
-+	 (eq_attr "alu_type" "add,sub") (const_string "arith")
-+
-+	 (eq_attr "alu_type" "and,or,xor") (const_string "logical")
++  (cond [(eq_attr "got" "load") (const_string "load")
 +
 +	 ;; If a doubleword move uses these expensive instructions,
 +	 ;; it is usually better to schedule them in the same way
@@ -8564,15 +6771,15 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +	  ;;   auipc t0, %pcrel_hi(target)
 +	  ;;   jalr  ra, t0, %lo(target)
 +	  ;; The linker will relax these into JAL when appropriate.
-+	  (eq_attr "type" "call")
-+	  (const_int 8)
++	  (eq_attr "type" "call") (const_int 8)
 +
 +	  ;; "Ghost" instructions occupy no space.
-+	  (eq_attr "type" "ghost")
-+	  (const_int 0)
++	  (eq_attr "type" "ghost") (const_int 0)
 +
 +	  (eq_attr "got" "load") (const_int 8)
 +
++	  (eq_attr "type" "fcmp") (const_int 8)
++
 +	  ;; SHIFT_SHIFTs are decomposed into two separate instructions.
 +	  (eq_attr "move_type" "shift_shift")
 +		(const_int 8)
@@ -8738,29 +6945,12 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +			(plus "add")
 +			(minus "sub")])
 +
-+;; Pipeline descriptions.
-+;;
-+;; generic.md provides a fallback for processors without a specific
-+;; pipeline description.  It is derived from the old define_function_unit
-+;; version and uses the "alu" and "imuldiv" units declared below.
-+;;
-+;; Some of the processor-specific files are also derived from old
-+;; define_function_unit descriptions and simply override the parts of
-+;; generic.md that don't apply.  The other processor-specific files
-+;; are self-contained.
-+(define_automaton "alu,imuldiv")
-+
-+(define_cpu_unit "alu" "alu")
-+(define_cpu_unit "imuldiv" "imuldiv")
-+
 +;; Ghost instructions produce no real code and introduce no hazards.
 +;; They exist purely to express an effect on dataflow.
 +(define_insn_reservation "ghost" 0
 +  (eq_attr "type" "ghost")
 +  "nothing")
 +
-+(include "generic.md")
-+
 +;;
 +;;  ....................
 +;;
@@ -9810,7 +8000,7 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +		  (match_operand:P 2 "immediate_operand" "")))]
 +  ""
 +  "add\t%0,%1,%R2"
-+  [(set_attr "alu_type" "add")
++  [(set_attr "type" "arith")
 +   (set_attr "mode" "<MODE>")])
 +
 +;; Allow combine to split complex const_int load sequences, using operand 2
@@ -10386,7 +8576,11 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +	      [(match_operand:SCALARF 2 "register_operand" "f")
 +	       (match_operand:SCALARF 3 "register_operand" "f")]))]
 +  "TARGET_HARD_FLOAT"
-+  "f%C1.<fmt>\t%0,%2,%3"
++{
++  if (GET_CODE (operands[1]) == NE)
++    return "feq.<fmt>\t%0,%2,%3; seqz %0, %0";
++  return "f%C1.<fmt>\t%0,%2,%3";
++}
 +  [(set_attr "type" "fcmp")
 +   (set_attr "mode" "<UNITMODE>")])
 +
@@ -10477,7 +8671,7 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +})
 +
 +(define_insn "indirect_jump<mode>"
-+  [(set (pc) (match_operand:P 0 "register_operand" "r"))]
++  [(set (pc) (match_operand:P 0 "register_operand" "l"))]
 +  ""
 +  "jr\t%0"
 +  [(set_attr "type" "jump")
@@ -10501,7 +8695,7 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +})
 +
 +(define_insn "tablejump<mode>"
-+  [(set (pc) (match_operand:GPR 0 "register_operand" "r"))
++  [(set (pc) (match_operand:GPR 0 "register_operand" "l"))
 +   (use (label_ref (match_operand 1 "" "")))]
 +  ""
 +  "jr\t%0"
@@ -10698,14 +8892,14 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +})
 +
 +(define_insn "call_internal"
-+  [(call (mem:SI (match_operand 0 "call_insn_operand" "r,S"))
++  [(call (mem:SI (match_operand 0 "call_insn_operand" "l,S"))
 +	 (match_operand 1 "" ""))
 +   (clobber (reg:SI RETURN_ADDR_REGNUM))]
 +  ""
 +  { return REG_P (operands[0]) ? "jalr\t%0"
 +	   : absolute_symbolic_operand (operands[0], VOIDmode) ? "call\t%0"
 +	   : "call\t%0@"; }
-+  [(set_attr "jal" "indirect,direct")])
++  [(set_attr "type" "call")])
 +
 +(define_expand "call_value"
 +  [(parallel [(set (match_operand 0 "")
@@ -10721,19 +8915,19 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +;; See comment for call_internal.
 +(define_insn "call_value_internal"
 +  [(set (match_operand 0 "register_operand" "")
-+        (call (mem:SI (match_operand 1 "call_insn_operand" "r,S"))
++        (call (mem:SI (match_operand 1 "call_insn_operand" "l,S"))
 +              (match_operand 2 "" "")))
 +   (clobber (reg:SI RETURN_ADDR_REGNUM))]
 +  ""
 +  { return REG_P (operands[1]) ? "jalr\t%1"
 +	   : absolute_symbolic_operand (operands[1], VOIDmode) ? "call\t%1"
 +	   : "call\t%1@"; }
-+  [(set_attr "jal" "indirect,direct")])
++  [(set_attr "type" "call")])
 +
 +;; See comment for call_internal.
 +(define_insn "call_value_multiple_internal"
 +  [(set (match_operand 0 "register_operand" "")
-+        (call (mem:SI (match_operand 1 "call_insn_operand" "r,S"))
++        (call (mem:SI (match_operand 1 "call_insn_operand" "l,S"))
 +              (match_operand 2 "" "")))
 +   (set (match_operand 3 "register_operand" "")
 +	(call (mem:SI (match_dup 1))
@@ -10743,7 +8937,7 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +  { return REG_P (operands[1]) ? "jalr\t%1"
 +	   : absolute_symbolic_operand (operands[1], VOIDmode) ? "call\t%1"
 +	   : "call\t%1@"; }
-+  [(set_attr "jal" "indirect,direct")])
++  [(set_attr "type" "call")])
 +
 +;; Call subroutine returning any type.
 +
@@ -10801,9 +8995,40 @@ diff -urN empty/gcc/config/riscv/riscv.md gcc-5.2.0/gcc/config/riscv/riscv.md
 +
 +(include "sync.md")
 +(include "peephole.md")
-diff -urN empty/gcc/config/riscv/riscv.opt gcc-5.2.0/gcc/config/riscv/riscv.opt
---- gcc-5.2.0/gcc/config/riscv/riscv.opt	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/riscv.opt	2015-07-17 22:36:52.319705931 +0200
++(include "generic.md")
+diff -urN empty/gcc/config/riscv/riscv-modes.def gcc-5.3.0/gcc/config/riscv/riscv-modes.def
+--- empty/gcc/config/riscv/riscv-modes.def	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/riscv-modes.def	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,26 @@
++/* Extra machine modes for RISC-V target.
++   Copyright (C) 2011-2014 Free Software Foundation, Inc.
++   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++   Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++FLOAT_MODE (TF, 16, ieee_quad_format);
++
++/* Vector modes.  */
++VECTOR_MODES (INT, 4);        /*       V8QI V4HI V2SI */
++VECTOR_MODES (FLOAT, 4);      /*            V4HF V2SF */
+diff -urN empty/gcc/config/riscv/riscv.opt gcc-5.3.0/gcc/config/riscv/riscv.opt
+--- empty/gcc/config/riscv/riscv.opt	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/riscv.opt	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,87 @@
 +; Options for the MIPS port of the compiler
 +;
@@ -10853,8 +9078,12 @@ diff -urN empty/gcc/config/riscv/riscv.opt gcc-5.2.0/gcc/config/riscv/riscv.opt
 +Target Report RejectNegative Mask(SOFT_FLOAT_ABI)
 +Prevent the use of all hardware floating-point instructions
 +
++mno-fdiv
++Target Report RejectNegative Mask(NO_FDIV)
++Don't use hardware floating-point divide and square root instructions
++
 +mfdiv
-+Target Report RejectNegative Mask(FDIV)
++Target Report RejectNegative InverseMask(NO_FDIV, FDIV)
 +Use hardware floating-point divide and square root instructions
 +
 +march=
@@ -10885,17 +9114,111 @@ diff -urN empty/gcc/config/riscv/riscv.opt gcc-5.2.0/gcc/config/riscv/riscv.opt
 +Target Report Mask(SAVE_RESTORE)
 +Use smaller but slower prologue and epilogue code
 +
-+mlra
-+Target Report Var(riscv_lra_flag) Init(0) Save
-+Use LRA instead of reload
-+
 +mcmodel=
 +Target RejectNegative Joined Var(riscv_cmodel_string)
 +Use given RISC-V code model (medlow or medany)
-diff -urN empty/gcc/config/riscv/sync.md gcc-5.2.0/gcc/config/riscv/sync.md
---- gcc-5.2.0/gcc/config/riscv/sync.md	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/sync.md	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,198 @@
+diff -urN empty/gcc/config/riscv/riscv-protos.h gcc-5.3.0/gcc/config/riscv/riscv-protos.h
+--- empty/gcc/config/riscv/riscv-protos.h	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/riscv-protos.h	2016-04-02 14:07:12.469104719 +0800
+@@ -0,0 +1,94 @@
++/* Definition of RISC-V target for GNU compiler.
++   Copyright (C) 2011-2014 Free Software Foundation, Inc.
++   Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
++   Based on MIPS target for GNU compiler.
++
++This file is part of GCC.
++
++GCC is free software; you can redistribute it and/or modify
++it under the terms of the GNU General Public License as published by
++the Free Software Foundation; either version 3, or (at your option)
++any later version.
++
++GCC is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING3.  If not see
++<http://www.gnu.org/licenses/>.  */
++
++#ifndef GCC_RISCV_PROTOS_H
++#define GCC_RISCV_PROTOS_H
++
++enum riscv_symbol_type {
++  SYMBOL_ABSOLUTE,
++  SYMBOL_GOT_DISP,
++  SYMBOL_TLS,
++  SYMBOL_TLS_LE,
++  SYMBOL_TLS_IE,
++  SYMBOL_TLS_GD
++};
++#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
++
++enum riscv_code_model {
++  CM_MEDLOW,
++  CM_MEDANY,
++  CM_PIC
++};
++extern enum riscv_code_model riscv_cmodel;
++
++extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
++extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
++extern int riscv_address_insns (rtx, enum machine_mode, bool);
++extern int riscv_const_insns (rtx);
++extern int riscv_split_const_insns (rtx);
++extern int riscv_load_store_insns (rtx, rtx_insn *);
++extern rtx riscv_emit_move (rtx, rtx);
++extern bool riscv_split_symbol (rtx, rtx, enum machine_mode, rtx *);
++extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
++extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
++extern bool riscv_legitimize_move (enum machine_mode, rtx, rtx);
++extern bool riscv_legitimize_vector_move (enum machine_mode, rtx, rtx);
++
++extern rtx riscv_subword (rtx, bool);
++extern bool riscv_split_64bit_move_p (rtx, rtx);
++extern void riscv_split_doubleword_move (rtx, rtx);
++extern const char *riscv_output_move (rtx, rtx);
++extern const char *riscv_output_gpr_save (unsigned);
++#ifdef RTX_CODE
++extern void riscv_expand_scc (rtx *);
++extern void riscv_expand_conditional_branch (rtx *);
++#endif
++extern rtx riscv_expand_call (bool, rtx, rtx, rtx);
++extern void riscv_expand_fcc_reload (rtx, rtx, rtx);
++extern void riscv_set_return_address (rtx, rtx);
++extern bool riscv_expand_block_move (rtx, rtx, rtx);
++extern void riscv_expand_synci_loop (rtx, rtx);
++
++extern bool riscv_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT,
++					       HOST_WIDE_INT);
++extern bool riscv_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT,
++						HOST_WIDE_INT);
++extern void riscv_order_regs_for_local_alloc (void);
++
++extern rtx riscv_return_addr (int, rtx);
++extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
++extern void riscv_expand_prologue (void);
++extern void riscv_expand_epilogue (bool);
++extern bool riscv_can_use_return_insn (void);
++extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
++
++extern enum reg_class riscv_secondary_reload_class (enum reg_class,
++						   enum machine_mode,
++						   rtx, bool);
++extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
++
++extern void irix_asm_output_align (FILE *, unsigned);
++extern const char *current_section_name (void);
++extern unsigned int current_section_flags (void);
++
++extern void riscv_expand_vector_init (rtx, rtx);
++
++#endif /* ! GCC_RISCV_PROTOS_H */
+diff -urN empty/gcc/config/riscv/sync.md gcc-5.3.0/gcc/config/riscv/sync.md
+--- empty/gcc/config/riscv/sync.md	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/sync.md	2016-04-02 14:07:12.472438058 +0800
+@@ -0,0 +1,204 @@
 +;; Machine description for RISC-V atomic operations.
 +;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
 +;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
@@ -10950,17 +9273,23 @@ diff -urN empty/gcc/config/riscv/sync.md gcc-5.2.0/gcc/config/riscv/sync.md
 +   (match_operand:SI 1 "const_int_operand" "")] ;; model
 +  ""
 +{
-+  switch (INTVAL (operands[1]))
++  long model = INTVAL (operands[1]);
++
++  switch (model)
 +    {
 +    case MEMMODEL_SEQ_CST:
++    case MEMMODEL_SYNC_SEQ_CST:
 +    case MEMMODEL_ACQ_REL:
 +      return "fence rw,rw";
 +    case MEMMODEL_ACQUIRE:
++    case MEMMODEL_SYNC_ACQUIRE:
 +    case MEMMODEL_CONSUME:
 +      return "fence r,rw";
 +    case MEMMODEL_RELEASE:
++    case MEMMODEL_SYNC_RELEASE:
 +      return "fence rw,w";
 +    default:
++      fprintf(stderr, "mem_thread_fence_1(%ld)\n", model);
 +      gcc_unreachable();
 +    }
 +})
@@ -11094,36 +9423,36 @@ diff -urN empty/gcc/config/riscv/sync.md gcc-5.2.0/gcc/config/riscv/sync.md
 +				    gen_lowpart (SImode, shmt)));
 +  DONE;
 +})
-diff -urN empty/gcc/config/riscv/t-elf gcc-5.2.0/gcc/config/riscv/t-elf
---- gcc-5.2.0/gcc/config/riscv/t-elf	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/t-elf	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/gcc/config/riscv/t-elf gcc-5.3.0/gcc/config/riscv/t-elf
+--- empty/gcc/config/riscv/t-elf	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/t-elf	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,4 @@
 +# Build the libraries for both hard and soft floating point
 +
-+MULTILIB_OPTIONS = msoft-float m64/m32 mno-atomic
-+MULTILIB_DIRNAMES = soft-float 64 32 no-atomic
-diff -urN empty/gcc/config/riscv/t-linux64 gcc-5.2.0/gcc/config/riscv/t-linux64
---- gcc-5.2.0/gcc/config/riscv/t-linux64	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/gcc/config/riscv/t-linux64	2015-07-17 22:36:52.319705931 +0200
++MULTILIB_OPTIONS = m64/m32 msoft-float mno-atomic
++MULTILIB_DIRNAMES = 64 32 soft-float no-atomic
+diff -urN empty/gcc/config/riscv/t-linux64 gcc-5.3.0/gcc/config/riscv/t-linux64
+--- empty/gcc/config/riscv/t-linux64	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/gcc/config/riscv/t-linux64	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,5 @@
 +# Build the libraries for both hard and soft floating point
 +
 +MULTILIB_OPTIONS = m64/m32 msoft-float mno-atomic
 +MULTILIB_DIRNAMES = 64 32 soft-float no-atomic
-+MULTILIB_OSDIRNAMES = ../lib ../lib32
-diff -urN empty/libgcc/config/riscv/crti.S gcc-5.2.0/libgcc/config/riscv/crti.S
---- gcc-5.2.0/libgcc/config/riscv/crti.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/crti.S	2015-07-17 22:36:52.319705931 +0200
++MULTILIB_OSDIRNAMES = ../lib ../lib32 soft-float no-atomic
+diff -urN empty/libgcc/config/riscv/crti.S gcc-5.3.0/libgcc/config/riscv/crti.S
+--- empty/libgcc/config/riscv/crti.S	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/crti.S	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1 @@
 +/* crti.S is empty because .init_array/.fini_array are used exclusively. */
-diff -urN empty/libgcc/config/riscv/crtn.S gcc-5.2.0/libgcc/config/riscv/crtn.S
---- gcc-5.2.0/libgcc/config/riscv/crtn.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/crtn.S	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/libgcc/config/riscv/crtn.S gcc-5.3.0/libgcc/config/riscv/crtn.S
+--- empty/libgcc/config/riscv/crtn.S	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/crtn.S	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1 @@
 +/* crtn.S is empty because .init_array/.fini_array are used exclusively. */
-diff -urN empty/libgcc/config/riscv/div.S gcc-5.2.0/libgcc/config/riscv/div.S
---- gcc-5.2.0/libgcc/config/riscv/div.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/div.S	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/libgcc/config/riscv/div.S gcc-5.3.0/libgcc/config/riscv/div.S
+--- empty/libgcc/config/riscv/div.S	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/div.S	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,121 @@
 +  .text
 +  .align 2
@@ -11246,9 +9575,9 @@ diff -urN empty/libgcc/config/riscv/div.S gcc-5.2.0/libgcc/config/riscv/div.S
 +  bne   a0, t0, __divdi3
 +  ret
 +#endif
-diff -urN empty/libgcc/config/riscv/mul.S gcc-5.2.0/libgcc/config/riscv/mul.S
---- gcc-5.2.0/libgcc/config/riscv/mul.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/mul.S	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/libgcc/config/riscv/muldi3.S gcc-5.3.0/libgcc/config/riscv/muldi3.S
+--- empty/libgcc/config/riscv/muldi3.S	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/muldi3.S	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,21 @@
 +  .text
 +  .align 2
@@ -11263,17 +9592,77 @@ diff -urN empty/libgcc/config/riscv/mul.S gcc-5.2.0/libgcc/config/riscv/mul.S
 +  mv     a2, a0
 +  li     a0, 0
 +.L1:
-+  slli   a3, a1, _RISCV_SZPTR-1
-+  bgez   a3, .L2
++  andi   a3, a1, 1
++  beqz   a3, .L2
 +  add    a0, a0, a2
 +.L2:
 +  srli   a1, a1, 1
 +  slli   a2, a2, 1
 +  bnez   a1, .L1
 +  ret
-diff -urN empty/libgcc/config/riscv/riscv-fp.c gcc-5.2.0/libgcc/config/riscv/riscv-fp.c
---- gcc-5.2.0/libgcc/config/riscv/riscv-fp.c	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/riscv-fp.c	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/libgcc/config/riscv/multi3.S gcc-5.3.0/libgcc/config/riscv/multi3.S
+--- empty/libgcc/config/riscv/multi3.S	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/multi3.S	2016-04-02 14:07:12.472438058 +0800
+@@ -0,0 +1,56 @@
++  .text
++  .align 2
++
++#ifndef __riscv64
++/* Our RV64 64-bit routines are equivalent to our RV32 32-bit routines.  */
++# define __multi3 __muldi3
++#endif
++
++  .globl __multi3
++__multi3:
++
++#ifndef __riscv64
++/* Our RV64 64-bit routines are equivalent to our RV32 32-bit routines.  */
++# define __muldi3 __mulsi3
++#endif
++
++/* We rely on the fact that __muldi3 doesn't clobber the t-registers.  */
++
++  mv  t0, ra
++  mv  t5, a0
++  mv  a0, a1
++  mv  t6, a3
++  mv  a1, t5
++  mv  a4, a2
++  li  a5, 0
++  li  t2, 0
++  li  t4, 0
++.L1:
++  add  a6, t2, a1
++  andi t3, a4, 1
++  slli a7, a5, 1
++  slti t1, a1, 0
++  srli a4, a4, 1
++  add  a5, t4, a5
++  beqz t3, .L2
++  sltu t3, a6, t2
++  mv   t2, a6
++  add  t4, t3, a5
++.L2:
++  slli a1, a1, 1
++  or   a5, t1, a7
++  bnez a4, .L1
++  beqz a0, .L3
++  mv   a1, a2
++  call __muldi3
++  add  t4, t4, a0
++.L3:
++  beqz t6, .L4
++  mv   a1, t6
++  mv   a0, t5
++  call  __muldi3
++  add  t4, t4, a0
++.L4:
++  mv  a0, t2
++  mv  a1, t4
++  jr  t0
+diff -urN empty/libgcc/config/riscv/riscv-fp.c gcc-5.3.0/libgcc/config/riscv/riscv-fp.c
+--- empty/libgcc/config/riscv/riscv-fp.c	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/riscv-fp.c	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,178 @@
 +/* Functions needed for soft-float on riscv-linux.  Based on
 +   rs6000/ppc64-fp.c with TF types removed.
@@ -11453,9 +9842,9 @@ diff -urN empty/libgcc/config/riscv/riscv-fp.c gcc-5.2.0/libgcc/config/riscv/ris
 +}
 +
 +#endif
-diff -urN empty/libgcc/config/riscv/save-restore.S gcc-5.2.0/libgcc/config/riscv/save-restore.S
---- gcc-5.2.0/libgcc/config/riscv/save-restore.S	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/save-restore.S	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/libgcc/config/riscv/save-restore.S gcc-5.3.0/libgcc/config/riscv/save-restore.S
+--- empty/libgcc/config/riscv/save-restore.S	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/save-restore.S	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,220 @@
 +  .text
 +
@@ -11677,40 +10066,49 @@ diff -urN empty/libgcc/config/riscv/save-restore.S gcc-5.2.0/libgcc/config/riscv
 +  ret
 +
 +#endif
-diff -urN empty/libgcc/config/riscv/t-dpbit gcc-5.2.0/libgcc/config/riscv/t-dpbit
---- gcc-5.2.0/libgcc/config/riscv/t-dpbit	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/t-dpbit	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/libgcc/config/riscv/t-dpbit gcc-5.3.0/libgcc/config/riscv/t-dpbit
+--- empty/libgcc/config/riscv/t-dpbit	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/t-dpbit	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,4 @@
 +LIB2ADD += dp-bit.c
 +
 +dp-bit.c: $(srcdir)/fp-bit.c
 +	cat $(srcdir)/fp-bit.c > dp-bit.c
-diff -urN empty/libgcc/config/riscv/t-elf gcc-5.2.0/libgcc/config/riscv/t-elf
---- gcc-5.2.0/libgcc/config/riscv/t-elf	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/t-elf	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,4 @@
+diff -urN empty/libgcc/config/riscv/t-elf gcc-5.3.0/libgcc/config/riscv/t-elf
+--- empty/libgcc/config/riscv/t-elf	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/t-elf	2016-04-02 14:07:12.472438058 +0800
+@@ -0,0 +1,5 @@
 +LIB2ADD += $(srcdir)/config/riscv/riscv-fp.c \
 +	   $(srcdir)/config/riscv/save-restore.S \
-+	   $(srcdir)/config/riscv/mul.S \
++	   $(srcdir)/config/riscv/muldi3.S \
++	   $(srcdir)/config/riscv/multi3.S \
 +	   $(srcdir)/config/riscv/div.S
-diff -urN empty/libgcc/config/riscv/t-elf32 gcc-5.2.0/libgcc/config/riscv/t-elf32
---- gcc-5.2.0/libgcc/config/riscv/t-elf32	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/t-elf32	2015-07-17 22:36:52.319705931 +0200
-@@ -0,0 +1,2 @@
+diff -urN empty/libgcc/config/riscv/t-elf32 gcc-5.3.0/libgcc/config/riscv/t-elf32
+--- empty/libgcc/config/riscv/t-elf32	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/t-elf32	2016-04-02 14:07:12.472438058 +0800
+@@ -0,0 +1,4 @@
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _udivsi3 _umodsi3 _mulsi3 _muldi3
++
 +HOST_LIBGCC2_CFLAGS += -m32
 +CRTSTUFF_CFLAGS += -m32
-diff -urN empty/libgcc/config/riscv/t-fpbit gcc-5.2.0/libgcc/config/riscv/t-fpbit
---- gcc-5.2.0/libgcc/config/riscv/t-fpbit	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/t-fpbit	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/libgcc/config/riscv/t-elf64 gcc-5.3.0/libgcc/config/riscv/t-elf64
+--- empty/libgcc/config/riscv/t-elf64	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/t-elf64	2016-04-02 14:07:12.472438058 +0800
+@@ -0,0 +1,2 @@
++LIB2FUNCS_EXCLUDE += _divdi3 _moddi3 _udivdi3 _umoddi3 _muldi3 _multi3 \
++		     _divsi3 _modsi3 _udivsi3 _umodsi3 \
+diff -urN empty/libgcc/config/riscv/t-fpbit gcc-5.3.0/libgcc/config/riscv/t-fpbit
+--- empty/libgcc/config/riscv/t-fpbit	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/t-fpbit	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,5 @@
 +LIB2ADD += fp-bit.c
 +
 +fp-bit.c: $(srcdir)/fp-bit.c
 +	echo '#define FLOAT' > fp-bit.c
 +	cat $(srcdir)/fp-bit.c >> fp-bit.c
-diff -urN empty/libgcc/config/riscv/t-tpbit gcc-5.2.0/libgcc/config/riscv/t-tpbit
---- gcc-5.2.0/libgcc/config/riscv/t-tpbit	1970-01-01 01:00:00.000000000 +0100
-+++ gcc-5.2.0/libgcc/config/riscv/t-tpbit	2015-07-17 22:36:52.319705931 +0200
+diff -urN empty/libgcc/config/riscv/t-tpbit gcc-5.3.0/libgcc/config/riscv/t-tpbit
+--- empty/libgcc/config/riscv/t-tpbit	1970-01-01 08:00:00.000000000 +0800
++++ gcc-5.3.0/libgcc/config/riscv/t-tpbit	2016-04-02 14:07:12.472438058 +0800
 @@ -0,0 +1,10 @@
 +LIB2ADD += tp-bit.c
 +
diff --git a/util/crossgcc/sum/binutils-2.25.tar.bz2.cksum b/util/crossgcc/sum/binutils-2.25.tar.bz2.cksum
deleted file mode 100644
index 1f339d4084..0000000000
--- a/util/crossgcc/sum/binutils-2.25.tar.bz2.cksum
+++ /dev/null
@@ -1 +0,0 @@
-b46cc90ebaba7ffcf6c6d996d60738881b14e50d  tarballs/binutils-2.25.tar.bz2
diff --git a/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum b/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum
new file mode 100644
index 0000000000..ac0a3c3f50
--- /dev/null
+++ b/util/crossgcc/sum/binutils-2.26.tar.bz2.cksum
@@ -0,0 +1 @@
+a637508cffeb2323b14bc8dd65378819768ad4ff  tarballs/binutils-2.26.tar.bz2
diff --git a/util/crossgcc/sum/cfe-3.7.1.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.7.1.src.tar.xz.cksum
deleted file mode 100644
index 57b4bf553f..0000000000
--- a/util/crossgcc/sum/cfe-3.7.1.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-15475a2c1e750a13755812785a4796cf4d9fa4c2  tarballs/cfe-3.7.1.src.tar.xz
diff --git a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum
new file mode 100644
index 0000000000..7ba8c8c272
--- /dev/null
+++ b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum
@@ -0,0 +1 @@
+2230ef962f2df3c13ec93f5b04b0e3cdff94b2ce  tarballs/cfe-3.8.0.src.tar.xz
diff --git a/util/crossgcc/sum/clang-tools-extra-3.7.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.7.1.src.tar.xz.cksum
deleted file mode 100644
index 49eea303b6..0000000000
--- a/util/crossgcc/sum/clang-tools-extra-3.7.1.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-af7b0208d00be365849a923b16b8e6d0fca2a2fc  tarballs/clang-tools-extra-3.7.1.src.tar.xz
diff --git a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum
new file mode 100644
index 0000000000..e9d8d7207d
--- /dev/null
+++ b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum
@@ -0,0 +1 @@
+a99d8b6fc5e593c4671424b327779318a1856acf  tarballs/clang-tools-extra-3.8.0.src.tar.xz
diff --git a/util/crossgcc/sum/compiler-rt-3.7.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.7.1.src.tar.xz.cksum
deleted file mode 100644
index fd007e9d45..0000000000
--- a/util/crossgcc/sum/compiler-rt-3.7.1.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-8ad98fcc0bc801ba448c9bc43942fd3f545a6923  tarballs/compiler-rt-3.7.1.src.tar.xz
diff --git a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum
new file mode 100644
index 0000000000..081705d8f5
--- /dev/null
+++ b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum
@@ -0,0 +1 @@
+480ea09e369dac6de1f3759b27fa19417b26b69e  tarballs/compiler-rt-3.8.0.src.tar.xz
diff --git a/util/crossgcc/sum/gcc-5.2.0.tar.bz2.cksum b/util/crossgcc/sum/gcc-5.2.0.tar.bz2.cksum
deleted file mode 100644
index 2bc4f22a81..0000000000
--- a/util/crossgcc/sum/gcc-5.2.0.tar.bz2.cksum
+++ /dev/null
@@ -1 +0,0 @@
-fe3f5390949d47054b613edc36c557eb1d51c18e  tarballs/gcc-5.2.0.tar.bz2
diff --git a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum
new file mode 100644
index 0000000000..bb05e39f2c
--- /dev/null
+++ b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum
@@ -0,0 +1 @@
+0612270b103941da08376df4d0ef4e5662a2e9eb  tarballs/gcc-5.3.0.tar.bz2
diff --git a/util/crossgcc/sum/llvm-3.7.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.7.1.src.tar.xz.cksum
deleted file mode 100644
index b63e7070de..0000000000
--- a/util/crossgcc/sum/llvm-3.7.1.src.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-5dbdcafac105273dcbff94c68837a66c6dd78cef  tarballs/llvm-3.7.1.src.tar.xz
diff --git a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum
new file mode 100644
index 0000000000..2f0af53db6
--- /dev/null
+++ b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum
@@ -0,0 +1 @@
+723ac918979255706434a05f5af34b71c49c9971  tarballs/llvm-3.8.0.src.tar.xz
diff --git a/util/crossgcc/sum/mpfr-3.1.3.tar.bz2.cksum b/util/crossgcc/sum/mpfr-3.1.3.tar.bz2.cksum
deleted file mode 100644
index 0be644cb02..0000000000
--- a/util/crossgcc/sum/mpfr-3.1.3.tar.bz2.cksum
+++ /dev/null
@@ -1 +0,0 @@
-3e46c5ce43701f2f36f9d01f407efe081700da80  tarballs/mpfr-3.1.3.tar.bz2
author	Iru Cai <mytbk920423@gmail.com>	2016-04-02 10:50:59 +0800
committer	Stefan Reinauer <stefan.reinauer@coreboot.org>	2016-05-04 20:21:11 +0200
commit	ae8e3a0bbb1d028e9d18572304ec93e1495976f5 (patch)
tree	ae98bf3fb77548fdb16eb0f7d40c2a5cc4fdbf04 /util/crossgcc
parent	2da008afa622e5469a34cd9d9712d498e84e4ea8 (diff)