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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-12-16 21:55:17 +0100 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-21 02:37:13 +0000 |
| commit | 45a6ae35ef9c605ff3ce47f98b8cfe53cccbdf7d (patch) | |
| tree | 164e7c1a66a046ba497dd7f5df42b27cbee0e15d /util/crossgcc | |
| parent | 08d8dd3bd3c08ae99b40ea5ee14c3c54a6546590 (diff) | |
soc/intel/xeon_sp/skx: Properly set up MTRR's
Don't depend on the MTRR setup left over from FSP-M ExitTempRam.
Change-Id: I299123b3cd3c37b4345102c20fda77bf261892a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'util/crossgcc')
0 files changed, 0 insertions, 0 deletions