diff options
| author | Iru Cai <mytbk920423@gmail.com> | 2016-10-29 23:37:42 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-05 18:35:18 +0100 |
| commit | 03353de80b2c0604e778d81e9010af787a183ab3 (patch) | |
| tree | 4621200302fe71537d6f1a07dd98c439bf783fd0 /util/crossgcc/patches/binutils-2.28_mips-gold.patch | |
| parent | 0da186c3ffb1d9aa7433a5d0d5263aba7a25ad60 (diff) | |
buildgcc: Update GCC, Binutils, GMP, MPFR, GDB, IASL and LLVM
- GCC gets updated from 5.2.0 to 6.3.0:
gcc-6.3.0_riscv.patch is a diff between 5fcb8c4 and 173684b in
riscv-gcc, and it needs gcc-6.3.0_memmodel.patch.
- Binutils goes from 2.26.1 to 2.28:
There is a build error for MIPS gold so I add patch for it.
- GMP gets a bump from 6.1.0 to 6.1.2
- MPFR is updated from 3.1.4 to 3.1.5
- GDB is upgraded from 6.1.1 to 6.1.2
- IASL is changed from 20160831 to 20161222
- LLVM is changed from 3.8.0 to 3.9.1
Change-Id: I20fea838d798c430d8c4d2cc6b07614d967c60c5
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17189
Tested-by: build bot (Jenkins)
Diffstat (limited to 'util/crossgcc/patches/binutils-2.28_mips-gold.patch')
| -rw-r--r-- | util/crossgcc/patches/binutils-2.28_mips-gold.patch | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/util/crossgcc/patches/binutils-2.28_mips-gold.patch b/util/crossgcc/patches/binutils-2.28_mips-gold.patch new file mode 100644 index 0000000000..d9a40210ff --- /dev/null +++ b/util/crossgcc/patches/binutils-2.28_mips-gold.patch @@ -0,0 +1,11 @@ +diff -urN binutils-2.27.orig/gold/configure.tgt binutils-2.27/gold/configure.tgt +--- binutils-2.27.orig/gold/configure.tgt 2016-08-03 15:36:53.000000000 +0800 ++++ binutils-2.27/gold/configure.tgt 2016-10-29 19:28:56.140587026 +0800 +@@ -157,6 +157,7 @@ + targ_obj=mips + targ_machine=EM_MIPS_RS3_LE + targ_size=32 ++ targ_extra_size=64 + targ_big_endian=false + targ_extra_big_endian=true + ;; |