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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-19 22:22:32 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-12-22 20:34:27 +0000 |
| commit | 8ba96b91dc1559c5a88bad5b4384885d3b384f11 (patch) | |
| tree | 029e28c6f65fe0550cc0e21a55e1fae57a11397f /util/crossgcc/.gitignore | |
| parent | e653942453f6537606417cefc1d16d8962166b10 (diff) | |
soc/intel/apl/graphics: add missing left-shift
According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.
Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'util/crossgcc/.gitignore')
0 files changed, 0 insertions, 0 deletions