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author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-01-31 11:28:06 -0800 |
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committer | Martin Roth <martinroth@google.com> | 2016-03-21 19:47:06 +0100 |
commit | e9a6d1a813f61b505f9463160c27992419cb9056 (patch) | |
tree | 4fc0fa1caec06fdab3a09d8ac763a7ac8f62fd56 /util/chromeos/extract_blobs.sh | |
parent | d75ed0bfd9238b210fdca136784cd699696421c7 (diff) |
Documentation: x86 shadow ROM disable
Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.
TEST=None
Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'util/chromeos/extract_blobs.sh')
0 files changed, 0 insertions, 0 deletions