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author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-05-10 14:25:24 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-24 11:25:24 +0000 |
commit | f5a48989b4d005158917b9890340f416dad506f1 (patch) | |
tree | 2a16b37f5d2f087e819caeea7fcf5e0176837f93 /util/cbfstool/cbfs_image.h | |
parent | a6d337badf0dbc6e56c9debc3062ce7f85ce863b (diff) |
soc/intel/elkhartlake: Make PCIe root port max payload size configurable
The data payload size of PCIe root ports can be set to either 128
(default) or 256 bytes. A bigger payload size can improve PCIe data
throughput on the given port. FSP-S provides a parameter to configure
this value.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'util/cbfstool/cbfs_image.h')
0 files changed, 0 insertions, 0 deletions