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authorPatrick Rudolph <patrick.rudolph@9elements.com>2024-04-03 17:46:29 +0200
committerLean Sheng Tan <sheng.tan@9elements.com>2024-04-14 20:50:22 +0000
commit9cd1bf2c17932e5985c5156dfa5fea76c25da725 (patch)
treee9ddd41610d1d074ab07d370a87aac6bdae661d0 /util/bincfg/bincfg.lex.c_shipped
parente2271dc0de7e3ad299ade88d214e377a91ab0bc3 (diff)
soc/intel/xeon_sp/spr: Drop microcode constraints
For current generation SPR/EMR you need to add at least 3 different microcodes having about 2MiB of size in total. This doesn't work with the hardcoded offset and size in Kconfig. Since it's loaded through FIT there's no need to pass it to FSP-T. Drop the hardcoded locations and place it somewhere in CBFS. Test: Booted on ibm/sbp1 with microcode confirmed loaded in bootblock on BSP. All the APs also have the correct microcode version loaded. TEST= Build and boot on intel/archercity CRB 'cat /proc/cpuinfo | grep microcode' result doesn't change before and after this patch. Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81635 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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