diff options
| author | Yilin Yang <kerker@google.com> | 2020-09-16 14:20:52 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-09-18 08:00:22 +0000 |
| commit | f944e619dd2739d268fc7eaea85d8acdf91bbfb8 (patch) | |
| tree | b858eabdad86c0373eb701dad8a6de279e5f0d0f /util/README.md | |
| parent | 541f2f74a37db36a8e35800950fd02adb0443d88 (diff) | |
util/mtkheader: Port gen-bl-img.py to python3
BUG=chromium:1023662
TEST=1. Use python2 script
2. Run `emerge-asurada coreboot` twice, so we get bootblock.bin.1
and bootblock.bin.2
3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
and bootblock.bin.2.hex
4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
difference. (at least, the time info changes)
5. Migrate to python3
6. Similar steps, we get bootblock.bin.py3.hex
7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
is similar.
Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I788e7c9b09257142728a0f76df8c2ccc72bf6b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'util/README.md')
| -rw-r--r-- | util/README.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/README.md b/util/README.md index 8b05f6f729..5ed4e758a3 100644 --- a/util/README.md +++ b/util/README.md @@ -65,7 +65,7 @@ embedded controller and insert them to the firmware image. `C` partial deblobbing of Intel ME/TXE firmware images `Python` * __mma__ - Memory Margin Analysis automation tests `Bash` * __msrtool__ - Dumps chipset-specific MSR registers. `C` -* __mtkheader__ - Generate MediaTek bootload header. `Python2` +* __mtkheader__ - Generate MediaTek bootload header. `Python3` * __nvidia__ - nvidia blob parsers * __nvramtool__ - Reads and writes coreboot parameters and displaying information from the coreboot table in CMOS/NVRAM. `C` |