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authorMichał Żygowski <michal.zygowski@3mdeb.com>2022-04-07 15:09:19 +0200
committerMichał Żygowski <michal.zygowski@3mdeb.com>2022-04-11 08:48:15 +0000
commitdccfb8a2158287be48522f9f70fd3e83b84c671f (patch)
treeeab3b873b48ae8661535b27b8c58e1ca6dfc3832 /tests
parentf3cc03b137cbceb144a78e709ae66fa1ac314b91 (diff)
soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for PCH-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'tests')
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