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authorKane Chen <kane.chen@intel.corp-partner.google.com>2024-04-12 21:16:15 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-05-07 12:50:37 +0000
commit8c927c4dbf94a140a460b935f87fb1002532c6f7 (patch)
tree7fbf7b5dbca683b31ecb78bb6dbc873b7082e28c /tests/stubs
parent8bcd8210ea64bdbb35485d361e645f2c9cfcf763 (diff)
soc/intel/mtl: Fixed TBT PCIe devtree remapping
The TBT PCIe devicetree settings are not remapped properly when TBT PCIe port 0 is disabled. This code refer SHA:58bc5d937 to remap the PCIe devtree settings properly in case of TBT PCIe port0 is disabled, TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg" showed up in coreboot log Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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