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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-09-30 17:44:08 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-11 15:15:41 +0000 |
| commit | 3df6f4192835d1a15c2d08a74de9b1ce05528b65 (patch) | |
| tree | 830db2f34f93661ca503aa3004a2e4035f3bce59 /tests/commonlib | |
| parent | 0c5885cd94ad8135c0187e5038c0690eb3550047 (diff) | |
soc/amd/cezanne/include/southbridge: add some more PM register defines
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'tests/commonlib')
0 files changed, 0 insertions, 0 deletions