diff options
| author | Jan Samek <jan.samek@siemens.com> | 2023-06-15 10:25:05 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-03 12:49:33 +0000 |
| commit | fc8ad3739b1ff3242cd4d572fa1259d2e04cf1fa (patch) | |
| tree | 899793731ecafe30e3ed08414592edf5c79d3aa1 /src | |
| parent | fef762f613ed06c9b0342cc6a0314542694304a0 (diff) | |
mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0
It's been decided not to use any of the USB 3.0 ports on this board.
This patch disables the remaining USB 3.0 port 0, after the port 1
has already been disabled in commit d0627c7595fe
("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1").
BUG=none
TEST=None of the USB 3.0 ports functional anymore after boot,
the USB 2.0 ports continue working.
Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb index 16f4375e63..9a0142c3dd 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb @@ -20,7 +20,7 @@ chip soc/intel/elkhartlake }" # USB related UPDs - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # X125/X135 + register "usb2_ports[0]" = "USB2_PORT_EMPTY" # UNUSED register "usb2_ports[1]" = "USB2_PORT_EMPTY" # UNUSED register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # X145/X155 register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # X145/X155 @@ -31,7 +31,7 @@ chip soc/intel/elkhartlake register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_EMPTY" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # UNUSED register "usb3_ports[1]" = "USB3_PORT_EMPTY" # UNUSED register "usb3_ports[2]" = "USB3_PORT_EMPTY" # UNUSED register "usb3_ports[3]" = "USB3_PORT_EMPTY" # UNUSED |