diff options
| author | Tim Van Patten <timvp@google.com> | 2023-03-31 17:31:10 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-06 18:00:42 +0000 |
| commit | f5ae1dd1be35daf3012e5773e7ce05f95ffa4da6 (patch) | |
| tree | 0b40a1111e7d72b2446d6df60e9a2c895330a300 /src | |
| parent | b9caac74a320a58ff0a60b33ec541f667082fd27 (diff) | |
amd/mendocino/root_complex: Restrict DPTC to 15W boards
Restrict DPTC to 15W boards, since we only have 15W values defined in
the devicetree. This will revert the 6W boards back to their default
values, rather than (incorrectly) configuring them with 15W values.
BUG=b:253301653
TEST=Verify DPTC values are set for 15W boards
TEST=Verify DPTC values are set not set for 6W boards
Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74127
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/mendocino/root_complex.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 6217246802..53a245b609 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -12,11 +12,13 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <fsp/amd_misc_data.h> #include <fsp/util.h> #include <soc/iomap.h> #include <stdint.h> #include "chip.h" +#define TDP_15W 15 #define DPTC_TOTAL_UPDATE_PARAMS 13 struct dptc_input { @@ -367,7 +369,18 @@ static void acipgen_dptci(void) static void root_complex_fill_ssdt(const struct device *device) { + uint32_t tdp = 0; + acpi_fill_root_complex_tom(device); + + if (get_amd_smu_reported_tdp(&tdp) != CB_SUCCESS) { + /* Unknown TDP, so return rather than setting invalid values. */ + return; + } + /* TODO(b/249359574): Add support for 6W DPTC values. */ + if (tdp != TDP_15W) + return; + if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) acipgen_dptci(); } |