diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2019-12-30 18:18:02 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-01 16:09:39 +0000 |
| commit | f54ae3875fa0dc183e14acaa579a095f59559400 (patch) | |
| tree | d897413077cb9f25a6dd6d1ca538d47407a6aeae /src | |
| parent | 7c09c6a9609b678518b500d5c8bf44d8fdc18853 (diff) | |
nb/intel/sandybridge: add and use ME stolen memory and lock bit defines
Change-Id: If4663498b10a5eedcc1aa51088b984ecc49ef23e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/finalize.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 2 |
3 files changed, 5 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 60e7a749ba..e07c6c2d5a 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -24,7 +24,7 @@ void intel_sandybridge_finalize_smm(void) pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); - pci_or_config32(PCI_DEV_SNB, MESEG_MASK, 1 << 10); + pci_or_config32(PCI_DEV_SNB, MESEG_MASK, MELCK); pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5b388de44f..4e42c7126b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -608,8 +608,8 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - reg = reg | (1 << 10); // set lockbit on ME mem - reg = reg | (1 << 11); // set ME memory enable + reg = reg | ME_STLEN_EN; // set ME memory enable + reg = reg | MELCK; // set lockbit on ME mem printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg); } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 4bb7003fa3..6dcb3ceb04 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -83,6 +83,8 @@ enum platform_type { #define MESEG_BASE 0x70 #define MESEG_MASK 0x78 +#define MELCK (1 << 10) /* ME Range Lock */ +#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ #define PAM0 0x80 #define PAM1 0x81 |