diff options
| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2024-03-27 14:47:08 +0900 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-04-01 04:48:27 +0000 |
| commit | f3b2c6e5dda795f9e06abf366d4d874c19c5bd27 (patch) | |
| tree | ab1720e8155abb4b91050ffbd4fb1a69f470ba20 /src | |
| parent | 4f085915fb37b718299b22c220d39c92348c2b33 (diff) | |
mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
Update GPIO configuration according to the schematic changes. The
locations of speaker and DMIC are swapped.
- Speaker: I2S2 -> I2S1
- DMIC: GPP_S2/GPP_S3 -> GPP_R4/GPP_R5
BUG=b:318584606
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81444
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/xol/gpio.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 13fd10dac1..168d9821d0 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -151,13 +151,23 @@ static const struct pad_config gpio_overrides[] = { /* H23 : SRCCLKREQ5# ==> PU 100K 3.3V */ PAD_CFG_GPI(GPP_H23, NONE, DEEP), + /* R4 : HDA_RST# ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), /* R7 : I2S2_RXD ==> NC */ PAD_NC(GPP_R7, NONE), - /* S0 : SNDW0_CLK ==> NC */ - PAD_NC(GPP_S0, NONE), - /* S1 : SNDW0_DATA ==> NC */ - PAD_NC(GPP_S1, NONE), + /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), /* S4 : SNDW2_CLK ==> NC */ PAD_NC(GPP_S4, NONE), /* S5 : SNDW2_DATA ==> NC */ |