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authorAngel Pons <th3fanbus@gmail.com>2020-10-13 14:25:57 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-10-23 18:14:21 +0000
commitec05de6f54d89d4cfa86aea56cabbf52238f36e5 (patch)
tree527f88703d18149f2449f81956887d682345946e /src
parent9ab02cb5fc86297bfcd52d266a07c95b8ee3d6e9 (diff)
soc/intel/broadwell: Define RCBA register LCAP
This register has a name. Use it. Change-Id: I952584c4aa92fc917d2fc0ef174ee12ae3eeee81 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/broadwell/finalize.c4
-rw-r--r--src/soc/intel/broadwell/include/soc/rcba.h2
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index af720740af..4196144369 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -95,8 +95,8 @@ static void broadwell_finalize(void *unused)
/* Lock */
RCBA32_OR(0x3a6c, 0x00000001);
- /* Read+Write the following register */
- RCBA32(0x21a4) = RCBA32(0x21a4);
+ /* Read+Write this R/WO register */
+ RCBA32(LCAP) = RCBA32(LCAP);
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h
index 3bacb9d5b6..0c63eb276c 100644
--- a/src/soc/intel/broadwell/include/soc/rcba.h
+++ b/src/soc/intel/broadwell/include/soc/rcba.h
@@ -48,6 +48,8 @@
#define PIRQG 6
#define PIRQH 7
+#define LCAP 0x21a4
+
/* IO Buffer Programming */
#define IOBPIRI 0x2330
#define IOBPD 0x2334