vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3361_03

The headers added are generated as per FSP v3361.03

In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.

BUG=b:247855492
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: I267a0aefca18492bcbcfbf7acbe271887f0a39cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>

2 files changed, 261 insertions, 240 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h
index 3117f275fd..55aa5eaa4a 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h
@@ -1141,7 +1141,11 @@ typedef struct {
 
 /** Offset 0x02B0 - Reserved
 **/
-  UINT8                       Reserved19[97];
+  UINT8                       Reserved19;
+
+/** Offset 0x02B1 - Reserved
+**/
+  UINT8                       Reserved20[96];
 
 /** Offset 0x0311 - Enable Gt CLOS
   0(Default)=Disable, 1=Enable
@@ -1311,51 +1315,51 @@ typedef struct {
 
 /** Offset 0x037B - Reserved
 **/
-  UINT8                       Reserved20[8];
+  UINT8                       Reserved21[8];
 
 /** Offset 0x0383 - Reserved
 **/
-  UINT8                       Reserved21[8];
+  UINT8                       Reserved22[8];
 
 /** Offset 0x038B - Reserved
 **/
-  UINT8                       Reserved22;
+  UINT8                       Reserved23;
 
 /** Offset 0x038C - Reserved
 **/
-  UINT8                       Reserved23;
+  UINT8                       Reserved24;
 
 /** Offset 0x038D - Reserved
 **/
-  UINT8                       Reserved24;
+  UINT8                       Reserved25;
 
 /** Offset 0x038E - Reserved
 **/
-  UINT8                       Reserved25[8];
+  UINT8                       Reserved26[8];
 
 /** Offset 0x0396 - Reserved
 **/
-  UINT8                       Reserved26;
+  UINT8                       Reserved27;
 
 /** Offset 0x0397 - Reserved
 **/
-  UINT8                       Reserved27;
+  UINT8                       Reserved28;
 
 /** Offset 0x0398 - Reserved
 **/
-  UINT8                       Reserved28[8];
+  UINT8                       Reserved29[8];
 
 /** Offset 0x03A0 - Reserved
 **/
-  UINT8                       Reserved29[8];
+  UINT8                       Reserved30[8];
 
 /** Offset 0x03A8 - Reserved
 **/
-  UINT8                       Reserved30;
+  UINT8                       Reserved31;
 
 /** Offset 0x03A9 - Reserved
 **/
-  UINT8                       Reserved31[8];
+  UINT8                       Reserved32[8];
 
 /** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo
   Set ASPM Control configuration
@@ -1512,7 +1516,7 @@ typedef struct {
 
 /** Offset 0x03CD - Reserved
 **/
-  UINT8                       Reserved32;
+  UINT8                       Reserved33;
 
 /** Offset 0x03CE - Ring Downbin
   Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
@@ -1535,7 +1539,7 @@ typedef struct {
 
 /** Offset 0x03D1 - Reserved
 **/
-  UINT8                       Reserved33;
+  UINT8                       Reserved34;
 
 /** Offset 0x03D2 - Ring voltage override
   The ring voltage override which is applied to the entire range of cpu ring frequencies.
@@ -1581,47 +1585,47 @@ typedef struct {
 
 /** Offset 0x03DC - Reserved
 **/
-  UINT8                       Reserved34;
+  UINT8                       Reserved35;
 
 /** Offset 0x03DD - Reserved
 **/
-  UINT8                       Reserved35;
+  UINT8                       Reserved36;
 
 /** Offset 0x03DE - Reserved
 **/
-  UINT16                      Reserved36;
+  UINT16                      Reserved37;
 
 /** Offset 0x03E0 - Reserved
 **/
-  UINT16                      Reserved37;
+  UINT16                      Reserved38;
 
 /** Offset 0x03E2 - Reserved
 **/
-  UINT16                      Reserved38;
+  UINT16                      Reserved39;
 
 /** Offset 0x03E4 - Reserved
 **/
-  UINT16                      Reserved39[4];
+  UINT16                      Reserved40[4];
 
 /** Offset 0x03EC - Reserved
 **/
-  UINT8                       Reserved40[4];
+  UINT8                       Reserved41[4];
 
 /** Offset 0x03F0 - Reserved
 **/
-  UINT8                       Reserved41;
+  UINT8                       Reserved42;
 
 /** Offset 0x03F1 - Reserved
 **/
-  UINT8                       Reserved42;
+  UINT8                       Reserved43;
 
 /** Offset 0x03F2 - Reserved
 **/
-  UINT8                       Reserved43;
+  UINT8                       Reserved44;
 
 /** Offset 0x03F3 - Reserved
 **/
-  UINT8                       Reserved44;
+  UINT8                       Reserved45;
 
 /** Offset 0x03F4 - Core VF Point Offset Mode
   Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
@@ -1633,7 +1637,7 @@ typedef struct {
 
 /** Offset 0x03F5 - Reserved
 **/
-  UINT8                       Reserved45[1];
+  UINT8                       Reserved46[1];
 
 /** Offset 0x03F6 - Core VF Point Offset
   Array used to specifies the Core Voltage Offset applied to the each selected VF
@@ -1660,15 +1664,15 @@ typedef struct {
 
 /** Offset 0x0433 - Reserved
 **/
-  UINT8                       Reserved46;
+  UINT8                       Reserved47;
 
 /** Offset 0x0434 - Reserved
 **/
-  UINT16                      Reserved47[8];
+  UINT16                      Reserved48[8];
 
 /** Offset 0x0444 - Reserved
 **/
-  UINT8                       Reserved48[8];
+  UINT8                       Reserved49[8];
 
 /** Offset 0x044C - Per Core Max Ratio override
   Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
@@ -1684,11 +1688,11 @@ typedef struct {
 
 /** Offset 0x0455 - Reserved
 **/
-  UINT8                       Reserved49[4];
+  UINT8                       Reserved50[4];
 
 /** Offset 0x0459 - Reserved
 **/
-  UINT8                       Reserved50;
+  UINT8                       Reserved51;
 
 /** Offset 0x045A - Pvd Ratio Threshold
   Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default.
@@ -1710,23 +1714,23 @@ typedef struct {
 
 /** Offset 0x045D - Reserved
 **/
-  UINT8                       Reserved51;
+  UINT8                       Reserved52;
 
 /** Offset 0x045E - Reserved
 **/
-  UINT16                      Reserved52[15];
+  UINT16                      Reserved53[15];
 
 /** Offset 0x047C - Reserved
 **/
-  UINT8                       Reserved53[15];
+  UINT8                       Reserved54[15];
 
 /** Offset 0x048B - Reserved
 **/
-  UINT8                       Reserved54[15];
+  UINT8                       Reserved55[15];
 
 /** Offset 0x049A - Reserved
 **/
-  UINT8                       Reserved55;
+  UINT8                       Reserved56;
 
 /** Offset 0x049B - BCLK Frequency Source
   Clock source of BCLK OC frequency, <b>1:CPU BCLK</b>, 2:PCH BCLK, 3:External CLK
@@ -1743,7 +1747,7 @@ typedef struct {
 
 /** Offset 0x049D - Reserved
 **/
-  UINT8                       Reserved56[3];
+  UINT8                       Reserved57[3];
 
 /** Offset 0x04A0 - CPU BCLK OC Frequency
   CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0
@@ -1753,91 +1757,91 @@ typedef struct {
 
 /** Offset 0x04A4 - Reserved
 **/
-  UINT32                      Reserved57;
+  UINT32                      Reserved58;
 
 /** Offset 0x04A8 - Reserved
 **/
-  UINT32                      Reserved58;
+  UINT32                      Reserved59;
 
 /** Offset 0x04AC - Reserved
 **/
-  UINT8                       Reserved59;
+  UINT8                       Reserved60;
 
 /** Offset 0x04AD - Reserved
 **/
-  UINT8                       Reserved60;
+  UINT8                       Reserved61;
 
 /** Offset 0x04AE - Reserved
 **/
-  UINT8                       Reserved61;
+  UINT8                       Reserved62;
 
 /** Offset 0x04AF - Reserved
 **/
-  UINT8                       Reserved62;
+  UINT8                       Reserved63;
 
 /** Offset 0x04B0 - Reserved
 **/
-  UINT16                      Reserved63;
+  UINT16                      Reserved64;
 
 /** Offset 0x04B2 - Reserved
 **/
-  UINT8                       Reserved64;
+  UINT8                       Reserved65;
 
 /** Offset 0x04B3 - Reserved
 **/
-  UINT8                       Reserved65;
+  UINT8                       Reserved66;
 
 /** Offset 0x04B4 - Reserved
 **/
-  UINT16                      Reserved66;
+  UINT16                      Reserved67;
 
 /** Offset 0x04B6 - Reserved
 **/
-  UINT8                       Reserved67;
+  UINT8                       Reserved68;
 
 /** Offset 0x04B7 - Reserved
 **/
-  UINT8                       Reserved68;
+  UINT8                       Reserved69;
 
 /** Offset 0x04B8 - Reserved
 **/
-  UINT8                       Reserved69;
+  UINT8                       Reserved70;
 
 /** Offset 0x04B9 - Reserved
 **/
-  UINT8                       Reserved70;
+  UINT8                       Reserved71;
 
 /** Offset 0x04BA - Reserved
 **/
-  UINT8                       Reserved71;
+  UINT8                       Reserved72;
 
 /** Offset 0x04BB - Reserved
 **/
-  UINT8                       Reserved72;
+  UINT8                       Reserved73;
 
 /** Offset 0x04BC - Reserved
 **/
-  UINT8                       Reserved73;
+  UINT8                       Reserved74;
 
 /** Offset 0x04BD - Reserved
 **/
-  UINT8                       Reserved74[3];
+  UINT8                       Reserved75[3];
 
 /** Offset 0x04C0 - Reserved
 **/
-  UINT32                      Reserved75;
+  UINT32                      Reserved76;
 
 /** Offset 0x04C4 - Reserved
 **/
-  UINT8                       Reserved76;
+  UINT8                       Reserved77;
 
 /** Offset 0x04C5 - Reserved
 **/
-  UINT8                       Reserved77;
+  UINT8                       Reserved78;
 
 /** Offset 0x04C6 - Reserved
 **/
-  UINT8                       Reserved78[6];
+  UINT8                       Reserved79[6];
 
 /** Offset 0x04CC - BiosGuard
   Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@@ -1857,7 +1861,7 @@ typedef struct {
 
 /** Offset 0x04CF - Reserved
 **/
-  UINT8                       Reserved79;
+  UINT8                       Reserved80;
 
 /** Offset 0x04D0 - PrmrrSize
   Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -1921,7 +1925,7 @@ typedef struct {
 
 /** Offset 0x0509 - Reserved
 **/
-  UINT8                       Reserved80[32];
+  UINT8                       Reserved81[32];
 
 /** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle
   Enable PCH PCIe Gen 3 Set CTLE Value.
@@ -2108,7 +2112,7 @@ typedef struct {
 
 /** Offset 0x0745 - Reserved
 **/
-  UINT8                       Reserved81;
+  UINT8                       Reserved82;
 
 /** Offset 0x0746 - SMBUS Base Address
   SMBUS Base Address (IO space).
@@ -2129,7 +2133,7 @@ typedef struct {
 
 /** Offset 0x075B - Reserved
 **/
-  UINT8                       Reserved82[14];
+  UINT8                       Reserved83[14];
 
 /** Offset 0x0769 - ClkReq-to-ClkSrc mapping
   Number of ClkReq signal assigned to ClkSrc
@@ -2138,19 +2142,19 @@ typedef struct {
 
 /** Offset 0x077B - Reserved
 **/
-  UINT8                       Reserved83[14];
+  UINT8                       Reserved84[14];
 
 /** Offset 0x0789 - Reserved
 **/
-  UINT8                       Reserved84[3];
+  UINT8                       Reserved85[3];
 
 /** Offset 0x078C - Reserved
 **/
-  UINT32                      Reserved85[18];
+  UINT32                      Reserved86[18];
 
 /** Offset 0x07D4 - Reserved
 **/
-  UINT32                      Reserved86;
+  UINT32                      Reserved87;
 
 /** Offset 0x07D8 - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -2212,7 +2216,7 @@ typedef struct {
 
 /** Offset 0x07F5 - Reserved
 **/
-  UINT8                       Reserved87[3];
+  UINT8                       Reserved88[3];
 
 /** Offset 0x07F8 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -2274,7 +2278,7 @@ typedef struct {
 
 /** Offset 0x0811 - Reserved
 **/
-  UINT8                       Reserved88[3];
+  UINT8                       Reserved89[3];
 
 /** Offset 0x0814 - Serial Io Uart Debug BaudRate
   Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
@@ -2302,7 +2306,7 @@ typedef struct {
 
 /** Offset 0x081B - Reserved
 **/
-  UINT8                       Reserved89;
+  UINT8                       Reserved90;
 
 /** Offset 0x081C - Serial Io Uart Debug Mmio Base
   Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
@@ -2622,7 +2626,7 @@ typedef struct {
 
 /** Offset 0x0854 - Reserved
 **/
-  UINT8                       Reserved90;
+  UINT8                       Reserved91;
 
 /** Offset 0x0855 - Extern Therm Status
   Enables/Disable Extern Therm Status
@@ -2662,7 +2666,7 @@ typedef struct {
 
 /** Offset 0x085B - Reserved
 **/
-  UINT8                       Reserved91;
+  UINT8                       Reserved92;
 
 /** Offset 0x085C - Exit On Failure (MRC)
   Enables/Disable Exit On Failure (MRC)
@@ -2768,11 +2772,11 @@ typedef struct {
 
 /** Offset 0x086D - Reserved
 **/
-  UINT8                       Reserved92;
+  UINT8                       Reserved93;
 
 /** Offset 0x086E - Reserved
 **/
-  UINT8                       Reserved93;
+  UINT8                       Reserved94;
 
 /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
   Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
@@ -2831,7 +2835,7 @@ typedef struct {
 
 /** Offset 0x087E - Reserved
 **/
-  UINT8                       Reserved94;
+  UINT8                       Reserved95;
 
 /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0
   Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
@@ -3041,11 +3045,11 @@ typedef struct {
 
 /** Offset 0x08A8 - Reserved
 **/
-  UINT8                       Reserved95;
+  UINT8                       Reserved96;
 
 /** Offset 0x08A9 - Reserved
 **/
-  UINT8                       Reserved96;
+  UINT8                       Reserved97;
 
 /** Offset 0x08AA - Rapl Power Floor Ch0
   Power budget ,range[255;0],(0= 5.3W Def)
@@ -3077,7 +3081,7 @@ typedef struct {
 
 /** Offset 0x08AF - Reserved
 **/
-  UINT8                       Reserved97;
+  UINT8                       Reserved98;
 
 /** Offset 0x08B0 - User Manual Threshold
   Disabled: Predefined threshold will be used.\n
@@ -3151,7 +3155,7 @@ typedef struct {
 
 /** Offset 0x08BB - Reserved
 **/
-  UINT8                       Reserved98;
+  UINT8                       Reserved99;
 
 /** Offset 0x08BC - Post Code Output Port
   This option configures Post Code Output Port
@@ -3178,7 +3182,7 @@ typedef struct {
 
 /** Offset 0x08C1 - Reserved
 **/
-  UINT8                       Reserved99[3];
+  UINT8                       Reserved100[3];
 
 /** Offset 0x08C4 - BCLK RFI Frequency
   Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
@@ -3228,15 +3232,15 @@ typedef struct {
 
 /** Offset 0x08DB - Reserved
 **/
-  UINT8                       Reserved100;
+  UINT8                       Reserved101;
 
 /** Offset 0x08DC - Reserved
 **/
-  UINT8                       Reserved101;
+  UINT8                       Reserved102;
 
 /** Offset 0x08DD - Reserved
 **/
-  UINT8                       Reserved102;
+  UINT8                       Reserved103;
 
 /** Offset 0x08DE - REFRESH_PANIC_WM
   DEPRECATED
@@ -3262,39 +3266,39 @@ typedef struct {
 
 /** Offset 0x08E2 - Reserved
 **/
-  UINT8                       Reserved103;
+  UINT8                       Reserved104;
 
 /** Offset 0x08E3 - Reserved
 **/
-  UINT8                       Reserved104;
+  UINT8                       Reserved105;
 
 /** Offset 0x08E4 - Reserved
 **/
-  UINT8                       Reserved105;
+  UINT8                       Reserved106;
 
 /** Offset 0x08E5 - Reserved
 **/
-  UINT8                       Reserved106;
+  UINT8                       Reserved107;
 
 /** Offset 0x08E6 - Reserved
 **/
-  UINT8                       Reserved107;
+  UINT8                       Reserved108;
 
 /** Offset 0x08E7 - Reserved
 **/
-  UINT8                       Reserved108;
+  UINT8                       Reserved109;
 
 /** Offset 0x08E8 - Reserved
 **/
-  UINT8                       Reserved109;
+  UINT8                       Reserved110;
 
 /** Offset 0x08E9 - Reserved
 **/
-  UINT8                       Reserved110;
+  UINT8                       Reserved111;
 
 /** Offset 0x08EA - Reserved
 **/
-  UINT8                       Reserved111;
+  UINT8                       Reserved112;
 
 /** Offset 0x08EB - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -3317,7 +3321,7 @@ typedef struct {
 
 /** Offset 0x08EE - Reserved
 **/
-  UINT8                       Reserved112;
+  UINT8                       Reserved113;
 
 /** Offset 0x08EF - Panel Power Enable
   Control for enabling/disabling VDD force bit (Required only for early enabling of
@@ -3334,7 +3338,7 @@ typedef struct {
 
 /** Offset 0x08F1 - Reserved
 **/
-  UINT8                       Reserved113[3];
+  UINT8                       Reserved114[3];
 
 /** Offset 0x08F4 - PMR Size
   Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@@ -3348,27 +3352,31 @@ typedef struct {
 
 /** Offset 0x08F9 - Reserved
 **/
-  UINT8                       Reserved114;
+  UINT8                       Reserved115;
 
 /** Offset 0x08FA - Reserved
 **/
-  UINT16                      Reserved115;
+  UINT16                      Reserved116;
 
 /** Offset 0x08FC - Reserved
 **/
-  UINT8                       Reserved116;
+  UINT8                       Reserved117;
 
 /** Offset 0x08FD - Reserved
 **/
-  UINT8                       Reserved117;
+  UINT8                       Reserved118;
 
 /** Offset 0x08FE - Reserved
 **/
-  UINT8                       Reserved118[89];
+  UINT8                       Reserved119;
+
+/** Offset 0x08FF - Reserved
+**/
+  UINT8                       Reserved120[88];
 
 /** Offset 0x0957 - Reserved
 **/
-  UINT8                       Reserved119;
+  UINT8                       Reserved121;
 
 /** Offset 0x0958 - TotalFlashSize
   Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
@@ -3384,7 +3392,7 @@ typedef struct {
 
 /** Offset 0x095C - Reserved
 **/
-  UINT8                       Reserved120[12];
+  UINT8                       Reserved122[12];
 
 /** Offset 0x0968 - Smbus dynamic power gating
   Disable or Enable Smbus dynamic power gating.
@@ -3450,7 +3458,7 @@ typedef struct {
 
 /** Offset 0x0972 - Reserved
 **/
-  UINT8                       Reserved121[2];
+  UINT8                       Reserved123[2];
 
 /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1
   Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
@@ -3487,7 +3495,7 @@ typedef struct {
 
 /** Offset 0x0A97 - Reserved
 **/
-  UINT8                       Reserved122;
+  UINT8                       Reserved124;
 
 /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT
   Select RX pin muxing for SerialIo UART used for debug
@@ -3513,183 +3521,183 @@ typedef struct {
 
 /** Offset 0x0AA8 - Reserved
 **/
-  UINT8                       Reserved123;
+  UINT8                       Reserved125;
 
 /** Offset 0x0AA9 - Reserved
 **/
-  UINT8                       Reserved124;
+  UINT8                       Reserved126;
 
 /** Offset 0x0AAA - Reserved
 **/
-  UINT16                      Reserved125;
+  UINT16                      Reserved127;
 
 /** Offset 0x0AAC - Reserved
 **/
-  UINT8                       Reserved126[4];
+  UINT8                       Reserved128[4];
 
 /** Offset 0x0AB0 - Reserved
 **/
-  UINT8                       Reserved127;
+  UINT8                       Reserved129;
 
 /** Offset 0x0AB1 - Reserved
 **/
-  UINT8                       Reserved128;
+  UINT8                       Reserved130;
 
 /** Offset 0x0AB2 - Reserved
 **/
-  UINT8                       Reserved129[6];
+  UINT8                       Reserved131[6];
 
 /** Offset 0x0AB8 - Reserved
 **/
-  UINT64                      Reserved130;
+  UINT64                      Reserved132;
 
 /** Offset 0x0AC0 - Reserved
 **/
-  UINT64                      Reserved131;
+  UINT64                      Reserved133;
 
 /** Offset 0x0AC8 - Reserved
 **/
-  UINT32                      Reserved132;
+  UINT32                      Reserved134;
 
 /** Offset 0x0ACC - Reserved
 **/
-  UINT8                       Reserved133[8];
+  UINT8                       Reserved135[8];
 
 /** Offset 0x0AD4 - Reserved
 **/
-  UINT8                       Reserved134;
+  UINT8                       Reserved136;
 
 /** Offset 0x0AD5 - Reserved
 **/
-  UINT8                       Reserved135[3];
+  UINT8                       Reserved137[3];
 
 /** Offset 0x0AD8 - Reserved
 **/
-  UINT32                      Reserved136;
+  UINT32                      Reserved138;
 
 /** Offset 0x0ADC - Reserved
 **/
-  UINT32                      Reserved137;
+  UINT32                      Reserved139;
 
 /** Offset 0x0AE0 - Reserved
 **/
-  UINT16                      Reserved138;
+  UINT16                      Reserved140;
 
 /** Offset 0x0AE2 - Reserved
 **/
-  UINT16                      Reserved139;
+  UINT16                      Reserved141;
 
 /** Offset 0x0AE4 - Reserved
 **/
-  UINT16                      Reserved140;
+  UINT16                      Reserved142;
 
 /** Offset 0x0AE6 - Reserved
 **/
-  UINT8                       Reserved141;
+  UINT8                       Reserved143;
 
 /** Offset 0x0AE7 - Reserved
 **/
-  UINT8                       Reserved142;
+  UINT8                       Reserved144;
 
 /** Offset 0x0AE8 - Reserved
 **/
-  UINT8                       Reserved143;
+  UINT8                       Reserved145;
 
 /** Offset 0x0AE9 - Reserved
 **/
-  UINT8                       Reserved144;
+  UINT8                       Reserved146;
 
 /** Offset 0x0AEA - Reserved
 **/
-  UINT8                       Reserved145;
+  UINT8                       Reserved147;
 
 /** Offset 0x0AEB - Reserved
 **/
-  UINT8                       Reserved146[5];
+  UINT8                       Reserved148[5];
 
 /** Offset 0x0AF0 - Reserved
 **/
-  UINT64                      Reserved147;
+  UINT64                      Reserved149;
 
 /** Offset 0x0AF8 - Reserved
 **/
-  UINT64                      Reserved148;
+  UINT64                      Reserved150;
 
 /** Offset 0x0B00 - Reserved
 **/
-  UINT32                      Reserved149;
+  UINT32                      Reserved151;
 
 /** Offset 0x0B04 - Reserved
 **/
-  UINT16                      Reserved150;
+  UINT16                      Reserved152;
 
 /** Offset 0x0B06 - Reserved
 **/
-  UINT8                       Reserved151;
+  UINT8                       Reserved153;
 
 /** Offset 0x0B07 - Reserved
 **/
-  UINT8                       Reserved152;
+  UINT8                       Reserved154;
 
 /** Offset 0x0B08 - Reserved
 **/
-  UINT8                       Reserved153;
+  UINT8                       Reserved155;
 
 /** Offset 0x0B09 - Reserved
 **/
-  UINT8                       Reserved154;
+  UINT8                       Reserved156;
 
 /** Offset 0x0B0A - Reserved
 **/
-  UINT8                       Reserved155;
+  UINT8                       Reserved157;
 
 /** Offset 0x0B0B - Reserved
 **/
-  UINT8                       Reserved156;
+  UINT8                       Reserved158;
 
 /** Offset 0x0B0C - Reserved
 **/
-  UINT8                       Reserved157;
+  UINT8                       Reserved159;
 
 /** Offset 0x0B0D - Reserved
 **/
-  UINT8                       Reserved158;
+  UINT8                       Reserved160;
 
 /** Offset 0x0B0E - Reserved
 **/
-  UINT16                      Reserved159;
+  UINT16                      Reserved161;
 
 /** Offset 0x0B10 - Reserved
 **/
-  UINT16                      Reserved160;
+  UINT16                      Reserved162;
 
 /** Offset 0x0B12 - Reserved
 **/
-  UINT16                      Reserved161;
+  UINT16                      Reserved163;
 
 /** Offset 0x0B14 - Reserved
 **/
-  UINT16                      Reserved162;
+  UINT16                      Reserved164;
 
 /** Offset 0x0B16 - Reserved
 **/
-  UINT8                       Reserved163[8];
+  UINT8                       Reserved165[8];
 
 /** Offset 0x0B1E - Reserved
 **/
-  UINT8                       Reserved164[8];
+  UINT8                       Reserved166[8];
 
 /** Offset 0x0B26 - Reserved
 **/
-  UINT16                      Reserved165;
+  UINT16                      Reserved167;
 
 /** Offset 0x0B28 - Reserved
 **/
-  UINT8                       Reserved166;
+  UINT8                       Reserved168;
 
 /** Offset 0x0B29 - Reserved
 **/
-  UINT8                       Reserved167;
+  UINT8                       Reserved169;
 
 /** Offset 0x0B2A -  LP5 Bank Mode
   LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0
@@ -3699,19 +3707,23 @@ typedef struct {
 
 /** Offset 0x0B2B - Reserved
 **/
-  UINT8                       Reserved168;
+  UINT8                       Reserved170;
 
 /** Offset 0x0B2C - Reserved
 **/
-  UINT8                       Reserved169;
+  UINT8                       Reserved171;
 
 /** Offset 0x0B2D - Reserved
 **/
-  UINT8                       Reserved170[5];
+  UINT8                       Reserved172;
+
+/** Offset 0x0B2E - Reserved
+**/
+  UINT8                       Reserved173[5];
 
-/** Offset 0x0B32 - Reserved
+/** Offset 0x0B33 - Reserved
 **/
-  UINT8                       Reserved171[6];
+  UINT8                       Reserved174[5];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h
index ceac191fae..a05fa35c07 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h
@@ -1634,13 +1634,15 @@ typedef struct {
 **/
   UINT8                       Reserved45[1];
 
-/** Offset 0x06AC - Reserved
+/** Offset 0x06AC - VR Fast Vmode ICC Limit support
+  PCODE MMIO Mailbox: The non-zero value will only be effective by setting the corresponding
+  EnableFastVmode to 1. 0-510A in 1/4 A units. 400 = 100A
 **/
-  UINT16                      Reserved46[5];
+  UINT16                      IccLimit[5];
 
 /** Offset 0x06B6 - Reserved
 **/
-  UINT8                       Reserved47[2];
+  UINT8                       Reserved46[2];
 
 /** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number
   Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
@@ -1663,11 +1665,11 @@ typedef struct {
 
 /** Offset 0x06BC - Reserved
 **/
-  UINT8                       Reserved48;
+  UINT8                       Reserved47;
 
 /** Offset 0x06BD - Reserved
 **/
-  UINT8                       Reserved49;
+  UINT8                       Reserved48;
 
 /** Offset 0x06BE - Min Voltage for C8
   PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
@@ -1701,7 +1703,7 @@ typedef struct {
 
 /** Offset 0x06C9 - Reserved
 **/
-  UINT8                       Reserved50;
+  UINT8                       Reserved49;
 
 /** Offset 0x06CA - CPU VR Power Delivery Design
   Used to communicate the power delivery design capability of the board. This value
@@ -1710,29 +1712,32 @@ typedef struct {
 **/
   UINT8                       VrPowerDeliveryDesign;
 
-/** Offset 0x06CB - Reserved
+/** Offset 0x06CB - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
+  Enable/Disable VR FastVmode; The value will only be effective by enabling the corresponding
+  CEP.<b>0: Disable</b>; 1: Enable.For all VR by domain
+  0: Disable, 1: Enable
 **/
-  UINT8                       Reserved51[5];
+  UINT8                       EnableFastVmode[5];
 
 /** Offset 0x06D0 - Reserved
 **/
-  UINT32                      Reserved52;
+  UINT32                      Reserved50;
 
 /** Offset 0x06D4 - Reserved
 **/
-  UINT32                      Reserved53;
+  UINT32                      Reserved51;
 
 /** Offset 0x06D8 - Reserved
 **/
-  UINT32                      Reserved54;
+  UINT32                      Reserved52;
 
 /** Offset 0x06DC - Reserved
 **/
-  UINT32                      Reserved55;
+  UINT32                      Reserved53;
 
 /** Offset 0x06E0 - Reserved
 **/
-  UINT8                       Reserved56[11];
+  UINT8                       Reserved54[11];
 
 /** Offset 0x06EB - Enable Power Optimizer
   Enable DMI Power Optimizer on PCH side.
@@ -1926,7 +1931,7 @@ typedef struct {
 
 /** Offset 0x0894 - Reserved
 **/
-  UINT8                       Reserved57;
+  UINT8                       Reserved55;
 
 /** Offset 0x0895 - Touch Host Controller Port 1 Assignment
   Assign THC Port 1
@@ -1936,7 +1941,7 @@ typedef struct {
 
 /** Offset 0x0896 - Reserved
 **/
-  UINT16                      Reserved58;
+  UINT16                      Reserved56;
 
 /** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux
   Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
@@ -1946,7 +1951,7 @@ typedef struct {
 
 /** Offset 0x089C - Reserved
 **/
-  UINT8                       Reserved59;
+  UINT8                       Reserved57;
 
 /** Offset 0x089D - PCIE RP Pcie Speed
   Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
@@ -1978,7 +1983,7 @@ typedef struct {
 
 /** Offset 0x0929 - Reserved
 **/
-  UINT8                       Reserved60[28];
+  UINT8                       Reserved58[28];
 
 /** Offset 0x0945 - PCIE RP Ltr Enable
   Latency Tolerance Reporting Mechanism.
@@ -2036,11 +2041,11 @@ typedef struct {
 
 /** Offset 0x09A1 - Reserved
 **/
-  UINT8                       Reserved61;
+  UINT8                       Reserved59;
 
 /** Offset 0x09A2 - Reserved
 **/
-  UINT16                      Reserved62;
+  UINT16                      Reserved60;
 
 /** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset
   Allows to select the downstream port preset value that will be used during phase
@@ -2329,7 +2334,7 @@ typedef struct {
 
 /** Offset 0x0A45 - Reserved
 **/
-  UINT8                       Reserved63;
+  UINT8                       Reserved61;
 
 /** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value
   Custimized T0Level value.
@@ -2504,7 +2509,7 @@ typedef struct {
 
 /** Offset 0x0A6B - Reserved
 **/
-  UINT8                       Reserved64;
+  UINT8                       Reserved62;
 
 /** Offset 0x0A6C - Thermal Device Temperature
   Decides the temperature.
@@ -2529,11 +2534,11 @@ typedef struct {
 
 /** Offset 0x0A89 - Reserved
 **/
-  UINT8                       Reserved65[2];
+  UINT8                       Reserved63[2];
 
 /** Offset 0x0A8B - Reserved
 **/
-  UINT8                       Reserved66;
+  UINT8                       Reserved64;
 
 /** Offset 0x0A8C - xHCI High Idle Time LTR override
   Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
@@ -2583,19 +2588,19 @@ typedef struct {
 
 /** Offset 0x0A9C - Reserved
 **/
-  UINT8                       Reserved67;
+  UINT8                       Reserved65;
 
 /** Offset 0x0A9D - Reserved
 **/
-  UINT8                       Reserved68;
+  UINT8                       Reserved66;
 
 /** Offset 0x0A9E - Reserved
 **/
-  UINT8                       Reserved69;
+  UINT8                       Reserved67;
 
 /** Offset 0x0A9F - Reserved
 **/
-  UINT8                       Reserved70[1];
+  UINT8                       Reserved68[1];
 
 /** Offset 0x0AA0 - BgpdtHash[4]
   BgpdtHash values
@@ -2609,7 +2614,7 @@ typedef struct {
 
 /** Offset 0x0AC4 - Reserved
 **/
-  UINT8                       Reserved71[4];
+  UINT8                       Reserved69[4];
 
 /** Offset 0x0AC8 - BiosGuardModulePtr
   BiosGuardModulePtr default values
@@ -2642,7 +2647,7 @@ typedef struct {
 
 /** Offset 0x0ADB - Reserved
 **/
-  UINT8                       Reserved72;
+  UINT8                       Reserved70;
 
 /** Offset 0x0ADC - Change Default SVID
   Change the default SVID used in FSP to programming internal devices. This is only
@@ -2742,35 +2747,35 @@ typedef struct {
 
 /** Offset 0x0B00 - Reserved
 **/
-  UINT8                       Reserved73;
+  UINT8                       Reserved71;
 
 /** Offset 0x0B01 - Reserved
 **/
-  UINT8                       Reserved74;
+  UINT8                       Reserved72;
 
 /** Offset 0x0B02 - Reserved
 **/
-  UINT8                       Reserved75;
+  UINT8                       Reserved73;
 
 /** Offset 0x0B03 - Reserved
 **/
-  UINT8                       Reserved76;
+  UINT8                       Reserved74;
 
 /** Offset 0x0B04 - Reserved
 **/
-  UINT8                       Reserved77;
+  UINT8                       Reserved75;
 
 /** Offset 0x0B05 - Reserved
 **/
-  UINT8                       Reserved78;
+  UINT8                       Reserved76;
 
 /** Offset 0x0B06 - Reserved
 **/
-  UINT8                       Reserved79[2];
+  UINT8                       Reserved77[2];
 
 /** Offset 0x0B08 - Reserved
 **/
-  UINT32                      Reserved80;
+  UINT32                      Reserved78;
 
 /** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm
   CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
@@ -2863,7 +2868,7 @@ typedef struct {
 
 /** Offset 0x0BD1 - Reserved
 **/
-  UINT8                       Reserved81[3];
+  UINT8                       Reserved79[3];
 
 /** Offset 0x0BD4 - CPU PCIE device override table pointer
   The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -3140,7 +3145,7 @@ typedef struct {
 
 /** Offset 0x0CA2 - Reserved
 **/
-  UINT8                       Reserved82[2];
+  UINT8                       Reserved80[2];
 
 /** Offset 0x0CA4 - LogoPixelHeight Address
   Address of LogoPixelHeight
@@ -3154,15 +3159,15 @@ typedef struct {
 
 /** Offset 0x0CAC - Reserved
 **/
-  UINT8                       Reserved83;
+  UINT8                       Reserved81;
 
 /** Offset 0x0CAD - Reserved
 **/
-  UINT8                       Reserved84;
+  UINT8                       Reserved82;
 
 /** Offset 0x0CAE - Reserved
 **/
-  UINT8                       Reserved85[3];
+  UINT8                       Reserved83[3];
 
 /** Offset 0x0CB1 - RSR feature
   Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
@@ -3172,7 +3177,7 @@ typedef struct {
 
 /** Offset 0x0CB2 - Reserved
 **/
-  UINT8                       Reserved86[4];
+  UINT8                       Reserved84[4];
 
 /** Offset 0x0CB6 - Enable or Disable HWP
   Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
@@ -3565,7 +3570,7 @@ typedef struct {
 
 /** Offset 0x0D2D - Reserved
 **/
-  UINT8                       Reserved87;
+  UINT8                       Reserved85;
 
 /** Offset 0x0D2E - Platform Power Pmax
   PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
@@ -3605,7 +3610,7 @@ typedef struct {
 
 /** Offset 0x0D3A - Reserved
 **/
-  UINT8                       Reserved88[2];
+  UINT8                       Reserved86[2];
 
 /** Offset 0x0D3C - Package Long duration turbo mode power limit
   Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -3708,7 +3713,7 @@ typedef struct {
 
 /** Offset 0x0D73 - Reserved
 **/
-  UINT8                       Reserved89[4];
+  UINT8                       Reserved87[4];
 
 /** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0
   Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
@@ -3780,7 +3785,7 @@ typedef struct {
 
 /** Offset 0x0D82 - Reserved
 **/
-  UINT8                       Reserved90;
+  UINT8                       Reserved88;
 
 /** Offset 0x0D83 - Dual Tau Boost
   Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0:
@@ -3791,19 +3796,23 @@ typedef struct {
 
 /** Offset 0x0D84 - Reserved
 **/
-  UINT8                       Reserved91;
+  UINT8                       Reserved89;
 
 /** Offset 0x0D85 - Reserved
 **/
-  UINT8                       Reserved92;
+  UINT8                       Reserved90;
 
 /** Offset 0x0D86 - Reserved
 **/
-  UINT8                       Reserved93[14];
+  UINT8                       Reserved91;
+
+/** Offset 0x0D87 - Reserved
+**/
+  UINT8                       Reserved92[13];
 
 /** Offset 0x0D94 - Reserved
 **/
-  UINT8                       Reserved94[16];
+  UINT8                       Reserved93[16];
 
 /** Offset 0x0DA4 - End of Post message
   Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
@@ -3852,7 +3861,7 @@ typedef struct {
 
 /** Offset 0x0DAB - Reserved
 **/
-  UINT8                       Reserved95[1];
+  UINT8                       Reserved94[1];
 
 /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.
@@ -4004,19 +4013,19 @@ typedef struct {
 
 /** Offset 0x0F96 - Reserved
 **/
-  UINT8                       Reserved96[4];
+  UINT8                       Reserved95[4];
 
 /** Offset 0x0F9A - Reserved
 **/
-  UINT8                       Reserved97[4];
+  UINT8                       Reserved96[4];
 
 /** Offset 0x0F9E - Reserved
 **/
-  UINT8                       Reserved98[4];
+  UINT8                       Reserved97[4];
 
 /** Offset 0x0FA2 - Reserved
 **/
-  UINT8                       Reserved99[4];
+  UINT8                       Reserved98[4];
 
 /** Offset 0x0FA6 - FOMS Control Policy
   Choose the Foms Control Policy, <b>Default = 0 </b>
@@ -4038,23 +4047,23 @@ typedef struct {
 
 /** Offset 0x0FAF - Reserved
 **/
-  UINT8                       Reserved100[8];
+  UINT8                       Reserved99[8];
 
 /** Offset 0x0FB7 - Reserved
 **/
-  UINT8                       Reserved101[8];
+  UINT8                       Reserved100[8];
 
 /** Offset 0x0FBF - Reserved
 **/
-  UINT8                       Reserved102[8];
+  UINT8                       Reserved101[8];
 
 /** Offset 0x0FC7 - Reserved
 **/
-  UINT8                       Reserved103[8];
+  UINT8                       Reserved102[8];
 
 /** Offset 0x0FCF - Reserved
 **/
-  UINT8                       Reserved104;
+  UINT8                       Reserved103;
 
 /** Offset 0x0FD0 - FspEventHandler
   <b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
@@ -4069,99 +4078,99 @@ typedef struct {
 
 /** Offset 0x0FD5 - Reserved
 **/
-  UINT8                       Reserved105[4];
+  UINT8                       Reserved104[4];
 
 /** Offset 0x0FD9 - Reserved
 **/
-  UINT8                       Reserved106;
+  UINT8                       Reserved105;
 
 /** Offset 0x0FDA - Reserved
 **/
-  UINT8                       Reserved107;
+  UINT8                       Reserved106;
 
 /** Offset 0x0FDB - Reserved
 **/
-  UINT8                       Reserved108;
+  UINT8                       Reserved107;
 
 /** Offset 0x0FDC - Reserved
 **/
-  UINT32                      Reserved109;
+  UINT32                      Reserved108;
 
 /** Offset 0x0FE0 - Reserved
 **/
-  UINT32                      Reserved110;
+  UINT32                      Reserved109;
 
 /** Offset 0x0FE4 - Reserved
 **/
-  UINT32                      Reserved111[2];
+  UINT32                      Reserved110[2];
 
 /** Offset 0x0FEC - Reserved
 **/
-  UINT32                      Reserved112[2];
+  UINT32                      Reserved111[2];
 
 /** Offset 0x0FF4 - Reserved
 **/
-  UINT32                      Reserved113[2];
+  UINT32                      Reserved112[2];
 
 /** Offset 0x0FFC - Reserved
 **/
-  UINT32                      Reserved114[2];
+  UINT32                      Reserved113[2];
 
 /** Offset 0x1004 - Reserved
 **/
-  UINT32                      Reserved115[2];
+  UINT32                      Reserved114[2];
 
 /** Offset 0x100C - Reserved
 **/
-  UINT32                      Reserved116[2];
+  UINT32                      Reserved115[2];
 
 /** Offset 0x1014 - Reserved
 **/
-  UINT32                      Reserved117[2];
+  UINT32                      Reserved116[2];
 
 /** Offset 0x101C - Reserved
 **/
-  UINT32                      Reserved118[2];
+  UINT32                      Reserved117[2];
 
 /** Offset 0x1024 - Reserved
 **/
-  UINT32                      Reserved119[2];
+  UINT32                      Reserved118[2];
 
 /** Offset 0x102C - Reserved
 **/
-  UINT32                      Reserved120[2];
+  UINT32                      Reserved119[2];
 
 /** Offset 0x1034 - Reserved
 **/
-  UINT32                      Reserved121[2];
+  UINT32                      Reserved120[2];
 
 /** Offset 0x103C - Reserved
 **/
-  UINT32                      Reserved122[2];
+  UINT32                      Reserved121[2];
 
 /** Offset 0x1044 - Reserved
 **/
-  UINT32                      Reserved123[2];
+  UINT32                      Reserved122[2];
 
 /** Offset 0x104C - Reserved
 **/
-  UINT8                       Reserved124[4];
+  UINT8                       Reserved123[4];
 
 /** Offset 0x1050 - Reserved
 **/
-  UINT64                      Reserved125;
+  UINT64                      Reserved124;
 
 /** Offset 0x1058 - Reserved
 **/
-  UINT32                      Reserved126;
+  UINT32                      Reserved125;
 
 /** Offset 0x105C - Reserved
 **/
-  UINT8                       Reserved127[2];
+  UINT8                       Reserved126[2];
 
 /** Offset 0x105E - Reserved
 **/
-  UINT8                       Reserved128[2];
+  UINT8                       Reserved127[2];
 } FSP_S_CONFIG;
 
 /** Fsp S UPD Configuration
@@ -4182,7 +4191,7 @@ typedef struct {
 
 /** Offset 0x1060
 **/
-  UINT8                       UnusedUpdSpace42[6];
+  UINT8                       UnusedUpdSpace41[6];
 
 /** Offset 0x1066
 **/