cpu/amd/model_10xxx: Refactor model detection to reduce code duplication

Moved mctGetLogicalCPUID() to a separate file and made it available in
both romstage and ramstage.

Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

4 files changed, 114 insertions, 82 deletions

diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c
index 0b3681cbb1..feb8f01f60 100644
--- a/src/cpu/amd/model_10xxx/powernow_acpi.c
+++ b/src/cpu/amd/model_10xxx/powernow_acpi.c
@@ -31,6 +31,8 @@
 #include <cpu/amd/amdfam10_sysconf.h>
 #include <arch/cpu.h>
 #include <northbridge/amd/amdht/AsPsDefs.h>
+#include <northbridge/amd/amdmct/mct/mct.h>
+#include <northbridge/amd/amdmct/amddefs.h>
 
 static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power,
 				u32 *pstate_latency, u32 *pstate_control,
@@ -114,8 +116,6 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
 
 	uint32_t dtemp;
-	uint32_t cpuid_fms;
-	uint8_t model;
 	uint8_t node_count;
 
 	/*
@@ -124,13 +124,10 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	 * cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x4 QuintupleCore ; 0x5 HexCore
 	 */
 	printk(BIOS_INFO, "Pstates algorithm ...\n");
-	/* Get CPU model */
-	cpuid_fms = cpuid_eax(0x80000001);
-	model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4);
 	/* Get number of cores */
 	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8);
 	cmp_cap = (dtemp & 0x3000) >> 12;
-	if ((model == 0x8) || (model == 0x9))	/* revision D */
+	if (mctGetLogicalCPUID(0) & AMD_FAM10_REV_D)	/* revision D */
 		cmp_cap |= (dtemp & 0x8000) >> 13;
 	/* Get number of nodes */
 	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60);
diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc
index ef4bef4654..fdbfa1222a 100644
--- a/src/northbridge/amd/amdfam10/Makefile.inc
+++ b/src/northbridge/amd/amdfam10/Makefile.inc
@@ -1,5 +1,7 @@
 ramstage-y += northbridge.c
 ramstage-y += misc_control.c
+romstage-y += amdfam10_util.c
+ramstage-y += amdfam10_util.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 
diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
new file mode 100644
index 0000000000..2726b280be
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+
+#include <arch/cpu.h>
+#include <northbridge/amd/amdmct/mct/mct_d.h>
+#include <northbridge/amd/amdmct/amddefs.h>
+
+#ifndef __PRE_RAM__
+#include <include/device/pci_ops.h>
+#include <include/device/pci_def.h>
+u32 Get_NB32(u32 dev, u32 reg)
+{
+        return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg);
+}
+#endif
+
+u32 mctGetLogicalCPUID(u32 Node)
+{
+	/* Converts the CPUID to a logical ID MASK that is used to check
+	 CPU version support versions */
+	u32 dev;
+	u32 val, valx;
+	u32 family, model, stepping;
+	u32 ret;
+
+	if (Node == 0xFF) { /* current node */
+		val = cpuid_eax(0x80000001);
+	} else {
+		dev = PA_NBMISC(Node);
+		val = Get_NB32(dev, 0xfc);
+	}
+
+	family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff);
+	model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0);
+	stepping = val & 0x0f;
+
+	valx = (family << 12) | (model << 4) | (stepping);
+
+	switch (valx) {
+	case 0x10000:
+		ret = AMD_DR_A0A;
+		break;
+	case 0x10001:
+		ret = AMD_DR_A1B;
+		break;
+	case 0x10002:
+		ret = AMD_DR_A2;
+		break;
+	case 0x10020:
+		ret = AMD_DR_B0;
+		break;
+	case 0x10021:
+		ret = AMD_DR_B1;
+		break;
+	case 0x10022:
+		ret = AMD_DR_B2;
+		break;
+	case 0x10023:
+		ret = AMD_DR_B3;
+		break;
+	case 0x10042:
+		ret = AMD_RB_C2;
+		break;
+	case 0x10043:
+		ret = AMD_RB_C3;
+		break;
+	case 0x10062:
+		ret = AMD_DA_C2;
+		break;
+	case 0x10063:
+		ret = AMD_DA_C3;
+		break;
+	case 0x10080:
+		ret = AMD_HY_D0;
+		break;
+	case 0x10081:
+	case 0x10091:
+		ret = AMD_HY_D1;
+		break;
+	case 0x100a0:
+		ret = AMD_PH_E0;
+		break;
+	default:
+		/* FIXME: mabe we should die() here. */
+		printk(BIOS_ERR, "FIXME! CPU Version unknown or not supported! \n");
+		ret = 0;
+	}
+
+	return ret;
+}
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 6398506049..02dc956306 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -187,82 +187,6 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
 
 }
 
-
-u32 mctGetLogicalCPUID(u32 Node)
-{
-	/* FIXME: Move this to a more generic place. Maybe to the CPU code */
-	/* Converts the CPUID to a logical ID MASK that is used to check
-	 CPU version support versions */
-	u32 dev;
-	u32 val, valx;
-	u32 family, model, stepping;
-	u32 ret;
-
-	if (Node == 0xFF) { /* current node */
-		val = cpuid_eax(0x80000001);
-	} else {
-		dev = PA_NBMISC(Node);
-		val = Get_NB32(dev, 0xfc);
-	}
-
-	family = ((val >> 8) & 0x0f) + ((val >> 20) & 0xff);
-	model = ((val >> 4) & 0x0f) | ((val >> (16-4)) & 0xf0);
-	stepping = val & 0x0f;
-
-	valx = (family << 12) | (model << 4) | (stepping);
-
-	switch (valx) {
-	case 0x10000:
-		ret = AMD_DR_A0A;
-		break;
-	case 0x10001:
-		ret = AMD_DR_A1B;
-		break;
-	case 0x10002:
-		ret = AMD_DR_A2;
-		break;
-	case 0x10020:
-		ret = AMD_DR_B0;
-		break;
-	case 0x10021:
-		ret = AMD_DR_B1;
-		break;
-	case 0x10022:
-		ret = AMD_DR_B2;
-		break;
-	case 0x10023:
-		ret = AMD_DR_B3;
-		break;
-	case 0x10042:
-		ret = AMD_RB_C2;
-		break;
-	case 0x10043:
-		ret = AMD_RB_C3;
-		break;
-	case 0x10062:
-		ret = AMD_DA_C2;
-		break;
-	case 0x10063:
-		ret = AMD_DA_C3;
-		break;
-	case 0x10080:
-		ret = AMD_HY_D0;
-		break;
-	case 0x10081:
-		ret = AMD_HY_D1;
-		break;
-	case 0x100a0:
-		ret = AMD_PH_E0;
-		break;
-	default:
-		/* FIXME: mabe we should die() here. */
-		printk(BIOS_ERR, "FIXME! CPU Version unknown or not supported! \n");
-		ret = 0;
-	}
-
-	return ret;
-}
-
 static u8 mctGetProcessorPackageType(void) {
 	/* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */
      u32 BrandId = cpuid_ebx(0x80000001);