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authorFelix Held <felix-coreboot@felixheld.de>2021-12-15 20:52:10 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-12-20 17:38:54 +0000
commitea6ee07f43d7f33117e2e9a1ff7d55b6d47cef9f (patch)
tree16dc49b7bd15c027d2dce732dba6cf86f61899e2 /src
parent2d020e1cc393a048b6794c034497bd60808036bb (diff)
soc/amd/stoneyridge/fch: add GNVS-related TODOs
The AOAC device states shouldn't be stored in GNVS, but be read from the AOAC registers during runtime. Same for the EHCI controller's BAR0. The location and size of the XHCI firmware can either be statically determined at build-time or have coreboot generate ACPI objects that contain the needed addresses. Since I can't easily test changes that require booting to a desktop on Stoneyridge at the moment, only add TODOs for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I3691b05606b9430cb60923780a6131993a9887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/fch.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c
index 16802eff4c..3037165a5d 100644
--- a/src/soc/amd/stoneyridge/fch.c
+++ b/src/soc/amd/stoneyridge/fch.c
@@ -165,12 +165,14 @@ static void set_sb_gnvs(struct global_nvs *gnvs)
gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE;
gnvs->fw03 = fwsize << 16;
+ /* TODO: This might break if the OS decides to re-allocate the PCI BARs. */
gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0)
& ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
}
void fch_final(void *chip_info)
{
+ /* TODO: The AOAC states and EHCI/XHCI addresses should be moved out of GNVS */
struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs) {
set_sb_aoac(&gnvs->aoac);