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authorAaron Durbin <adurbin@chromium.org>2016-09-16 11:15:49 -0500
committerAaron Durbin <adurbin@chromium.org>2016-09-19 17:01:23 +0200
commitdfe614ff9fea97b712e10f4977f2343a1f070d3e (patch)
treedb355bc28a591a235d975c408ec540731ce9db8d /src
parentbe5492aec0a02e416cf12a7ad7517900540d9991 (diff)
soc/intel/apollolake: cache boot media post romstage
When the boot media is memory mapped mark it as cacheable after romstage. Otherwise the boot media is uncacheable and all loads from it take longer. Loading FSP-S alone in ramstage went down to 17.5ms from 54ms. BUG=chrome-os-partner:56656 Change-Id: I6703334ba8fe98aca26ba1c995d6d3abb0ddef33 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16613 Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/romstage.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index ebd6287e4a..b9733defa3 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -130,6 +130,11 @@ asmlinkage void car_stage_entry(void)
assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
+ /* Cache the memory-mapped boot media. */
+ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
+ postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
+
run_postcar_phase(&pcf);
}