diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2014-11-11 13:39:18 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:08:12 +0200 |
| commit | dfd441d1a511ec48ac9de61000203dda5f52dcfe (patch) | |
| tree | 76918a44bf176eaa9dce80f9dbc71b0be53eae41 /src | |
| parent | 8549797b3047add2f1700d9f288cebaf7b85f5b8 (diff) | |
urara: add config of SPI bus and correct selection of winbond flash
Urara uses SPFI interface 1 and Winbond SPI NOR flash.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the fix of the Winbond driver (next patch) the bootblock
successfully probes the Windbond device on the FPGA board.
Console log below:
coreboot-4.0 bootblock Tue Nov 11 07:05:48 PST 2014 starting...
SF: Detected W25Q16 with page size 1000, total 200000
Change-Id: Ia848eac5b4a94bf95297c928b5447463c90d89eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38386715c52526edbe9ad356945849e21799fd94
Original-Change-Id: Ic27b60adc26bf244e7a15b5257e94df4b9d88249
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229030
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9809
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/urara/Kconfig | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index bee188a389..e065422fb2 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ID_SUPPORT select BOOTBLOCK_CONSOLE select MAINBOARD_HAS_CHROMEOS - select CONFIG_SPI_FLASH_WINBOND + select SPI_FLASH_WINBOND select CPU_IMGTEC_PISTACHIO select COMMON_CBFS_SPI_WRAPPER select MAINBOARD_HAS_BOOTBLOCK_INIT @@ -58,4 +58,8 @@ config CONSOLE_SERIAL_UART_ADDRESS depends on DRIVERS_UART default 0xB8101500 +config BOOT_MEDIA_SPI_BUS + int + default 1 + endif |