diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-11-13 20:25:33 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-05 14:38:11 +0000 |
| commit | def3c5ccabdc1945a7c10a3882e69b556e0150bd (patch) | |
| tree | 04717c2ce768d72efeac873b07b6af2fcb76918c /src | |
| parent | a3311b9f0f891c6f7740967273d58be4c7f86ded (diff) | |
soc/intel/tigerlake: Fix setting `HyperThreading`
The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.
Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 3 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 6e15d50486..c34892a39a 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -432,9 +432,6 @@ struct soc_intel_tigerlake_config { */ uint8_t cpu_ratio_override; - /* HyperThreadingDisable : Yes (1) / No (0) */ - uint8_t HyperThreadingDisable; - /* * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. * Default 0. Setting this to 1 disables the DMI Power Optimizer. diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 399cb87fe1..d4e694e4e0 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -125,9 +125,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2); m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3); - /* Hyper Threading */ - m_cfg->HyperThreading = !config->HyperThreadingDisable; - /* Disable Lock PCU Thermal Management registers */ m_cfg->LockPTMregs = 0; /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ |