diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2021-02-01 16:28:15 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-03 08:53:10 +0000 |
| commit | dec2c7840320069de8cae98f7606d73d2b5b0309 (patch) | |
| tree | 120c5e7d4fc4202538f29f1ac3baf866f83cde83 /src | |
| parent | 6d7a6d291d6dd04c2fc5ca0dba2b3ccb032c9ff4 (diff) | |
drivers/aspeed: Fix some issues
* Use probe_resource instead of find_resource. This prevents
a call to die and instead returns NULL.
* Handle the case where BAR2 isn't present
* Don't hardcode legacy VGA when BAR2 is present. This fixes
graphic initialisation when the Aspeed isn't the primary GPU
and thus doesn't decode VGA cycles.
This makes the coreboot code more similar to the Linux kernel code.
Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/aspeed/common/ast_main.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 89194ad0be..30d11313cb 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -393,7 +393,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ast->dev = dev; /* PCI BAR 1 */ - res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1); + res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_1); if (!res) { dev_err(dev->pdev, "BAR1 resource not found.\n"); ret = -EIO; @@ -407,19 +407,16 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) /* PCI BAR 2 */ ast->io_space_uses_mmap = false; - res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2); - if (!res) { + res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_2); + if (!res) dev_err(dev->pdev, "BAR2 resource not found.\n"); - ret = -EIO; - goto out_free; - } /* * If we don't have IO space at all, use MMIO now and * assume the chip has MMIO enabled by default (rev 0x20 * and higher). */ - if (!(res->flags & IORESOURCE_IO)) { + if (!res || !(res->flags & IORESOURCE_IO)) { DRM_INFO("platform has no IO space, trying MMIO\n"); ast->ioregs = ast->regs + AST_IO_MM_OFFSET; ast->io_space_uses_mmap = true; @@ -432,8 +429,6 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags) ret = -EIO; goto out_free; } - /* Adjust the I/O space location to match expectations (the code expects offset 0x0 to be I/O location 0x380) */ - ast->ioregs = (void *)AST_IO_MM_OFFSET; } ast_detect_chip(dev, &need_post); |