diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-13 13:42:07 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-19 23:03:38 +0000 |
| commit | dca3cb572bb2f506b8ec57bb7e6017b0b5e8acf2 (patch) | |
| tree | 2a067b11bf57dbc87109024db4c0b2215d23077d /src | |
| parent | 7f1363d9b4672c79b2538dcf9757cbb036aaf3e3 (diff) | |
nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM
Reference code never enables SRT for Sandy Bridge, and only enables it
for Ivy Bridge when the memory frequency is at most 1066 MHz.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I50527f311340584cf8290de2114ec2694cca3a83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4d478a06ab..453222e59d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -759,13 +759,14 @@ static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) { u16 pasr, cwl, mr2reg; odtmap odt; - int srt; + int srt = 0; pasr = 0; cwl = ctrl->CWL - 5; odt = get_ODT(ctrl, channel); - srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; + if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) + srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; mr2reg = 0; mr2reg = (mr2reg & ~0x07) | pasr; |