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authorDavid Hendricks <dhendrix@chromium.org>2013-03-26 21:39:03 -0700
committerDavid Hendricks <dhendrix@chromium.org>2013-03-28 22:52:20 +0100
commitdbc11e2f766ab520fe2ccb61fdfed69b89e9d623 (patch)
tree47f657dbf63692b5defd254de8884b685a1e0f6b /src
parent19f3092b5297b2f6e128a97698176ed1173be909 (diff)
armv7: clean+invalidate all cache levels when disabling MMU
This iterates thru all cache levels and cleans + invalidates all data and unified caches before disabling dcache and MMU. Change-Id: I8a671b4c90d7b88b8d0a95947bfa17f912cebaa2 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2930 Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/arch/armv7/lib/cache.c33
1 files changed, 30 insertions, 3 deletions
diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index de772a12b5..7bb337dd41 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -209,13 +209,40 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
dcache_op_mva(addr, len, OP_DCCIMVAC);
}
-
void dcache_mmu_disable(void)
{
- uint32_t sctlr;
+ uint32_t sctlr, clidr;
+ int level;
+
+ clidr = read_clidr();
+ for (level = 0; level < 7; level++) {
+ unsigned int ctype = (clidr >> (level * 3)) & 0x7;
+ uint32_t csselr;
+
+ switch(ctype) {
+ case 0x0:
+ /* no cache */
+ break;
+ case 0x2:
+ case 0x4:
+ /* dcache only or unified cache */
+ csselr = level << 1;
+ write_csselr(csselr);
+ dcache_clean_invalidate_all();
+ break;
+ case 0x3:
+ /* separate icache and dcache */
+ csselr = level << 1;
+ write_csselr(csselr);
+ dcache_clean_invalidate_all();
+ break;
+ default:
+ /* reserved */
+ break;
+ }
+ }
sctlr = read_sctlr();
- dcache_clean_invalidate_all();
sctlr &= ~(SCTLR_C | SCTLR_M);
write_sctlr(sctlr);
}