summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorRaul E Rangel <rrangel@chromium.org>2021-11-10 13:14:32 -0700
committerShelley Chen <shchen@google.com>2023-05-08 17:43:51 +0000
commitd6e0a90aa0bd574b28b6c9b4b46289bf46a208db (patch)
tree213b05143f785c1181ca364f7381fca4f8002b12 /src
parenta23ec079670c6bbff32f1d75891998d7652873e0 (diff)
soc/amd/cezanne/romstage: Preload fspm.bin
FSP-M is normally memmapped and then decompressed. The SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. It is interesting that FSP-M takes an additional 8ms to execute. I suspect since we call it 50ms earlier it's having to wait for one of its dependencies. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time | 970 - loading FSP-M | 0.316 | 0.997 Δ( 0.68, 0.05%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.026 | 13.874 Δ( 13.85, 0.96%) | | 18 - finished LZ4 decompress (ignore for x86) | 64.361 | 0.337 Δ(-64.02, -4.43%) | | 2 - before RAM initialization | 0.534 | 0.529 Δ( -0.01, -0.00%) | | 950 - calling FspMemoryInit | 1.455 | 1.132 Δ( -0.32, -0.02%) | | 951 - returning from FspMemoryInit | 207.695 | 216.537 Δ( 8.84, 0.61%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I850b1576501753a355e7b23745e04802a0560387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/cezanne/fsp_s_params.c6
-rw-r--r--src/soc/amd/cezanne/romstage.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index 60f3942802..a7ef95876f 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -18,10 +18,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
fsp_assign_vbios_upds(scfg);
/*
- * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB
- * before FSP-S was loaded, we would introduce contention onto the SPI bus and
- * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs
- * no SPI operations, we can read the APOB while FSP-S executes.
+ * At this point FSP-S has been loaded into RAM. Since FSP-S takes a while to execute
+ * and performs no SPI operations, we can read the APOB while FSP-S executes.
*/
start_apob_cache_read();
/*
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 2bf5e230c9..c6bba7b81e 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -18,6 +18,8 @@ void __noreturn romstage_main(void)
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
+ preload_fspm();
+
fsp_memory_init(acpi_is_wakeup_s3());
/* Fixup settings FSP-M should not be changing */