xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs

Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

2 files changed, 0 insertions, 1315 deletions

diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
deleted file mode 100644
index 44098b1290..0000000000
--- a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
+++ /dev/null
@@ -1,1017 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SKXSP_TP_GPIO_H_
-#define _SKXSP_TP_GPIO_H_
-
-#include <gpio_fsp.h>
-#include <soc/gpio_soc_defs.h>
-
-/*
- *  OCP TiogaPass Gpio Pad Configuration
- */
-static const UPD_GPIO_INIT_CONFIG tp_gpio_table[] = {
-	{GPIO_SKL_H_GPP_A0, {
-		GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
-	{GPIO_SKL_H_GPP_A1, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_1_LAD_0_ESPI_IO_0
-	{GPIO_SKL_H_GPP_A2, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_2_LAD_1_ESPI_IO_1
-	{GPIO_SKL_H_GPP_A3, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_3_LAD_2_ESPI_IO_2
-	{GPIO_SKL_H_GPP_A4, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_4_LAD_3_ESPI_IO_3
-	{GPIO_SKL_H_GPP_A5, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
-	{GPIO_SKL_H_GPP_A6, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
-	{GPIO_SKL_H_GPP_A7, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
-	{GPIO_SKL_H_GPP_A8, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_8_FM_LPC_CLKRUN_N
-	{GPIO_SKL_H_GPP_A9, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
-	{GPIO_SKL_H_GPP_A10, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_10_CLKOUT_LPC1
-	{GPIO_SKL_H_GPP_A11, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_11_FM_LPC_PME_N
-	{GPIO_SKL_H_GPP_A12, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
-	{GPIO_SKL_H_GPP_A13, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
-	{GPIO_SKL_H_GPP_A14, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_14_ESPI_RESET_N
-	{GPIO_SKL_H_GPP_A15, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_15_SUSACK_N
-	{GPIO_SKL_H_GPP_A16, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_16_CLKOUT_LPC2
-	{GPIO_SKL_H_GPP_A17, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_17
-	{GPIO_SKL_H_GPP_A18, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_18
-	//		{GPIO_SKL_H_GPP_A19, {} }, //GPP_A_19, controlled by ME
-	{GPIO_SKL_H_GPP_A20, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} },//GPP_A_20
-	{GPIO_SKL_H_GPP_A21, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_21
-	{GPIO_SKL_H_GPP_A22, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_22
-	{GPIO_SKL_H_GPP_A23, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_A_23
-
-	{GPIO_SKL_H_GPP_B0,  {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_0_CORE_VID_0
-	{GPIO_SKL_H_GPP_B1,  {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_1_CORE_VID_1
-	{GPIO_SKL_H_GPP_B2,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_2_VRALERT_N
-	{GPIO_SKL_H_GPP_B3,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_3_CPU_GP2
-	{GPIO_SKL_H_GPP_B4,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_4_CPU_GP3
-	{GPIO_SKL_H_GPP_B5,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_5_SRCCLKREQ0_N
-	{GPIO_SKL_H_GPP_B6,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_6_SRCCLKREQ1_N
-	{GPIO_SKL_H_GPP_B7,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_7_SRCCLKREQ2_N
-	{GPIO_SKL_H_GPP_B8,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_8_SRCCLKREQ3_N
-	{GPIO_SKL_H_GPP_B9,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_9_SRCCLKREQ4_N
-	{GPIO_SKL_H_GPP_B10, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_10_SRCCLKREQ5_N
-	{GPIO_SKL_H_GPP_B11, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_11
-	{GPIO_SKL_H_GPP_B12, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_12_GLB_RST_WARN_N
-	{GPIO_SKL_H_GPP_B13, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_13_RST_PLTRST_N
-	{GPIO_SKL_H_GPP_B14, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
-	{GPIO_SKL_H_GPP_B15, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_15
-	{GPIO_SKL_H_GPP_B16, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_16
-	{GPIO_SKL_H_GPP_B17, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_17
-	{GPIO_SKL_H_GPP_B18, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_18
-	{GPIO_SKL_H_GPP_B19, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_19
-	{GPIO_SKL_H_GPP_B20, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_20
-	{GPIO_SKL_H_GPP_B21, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_21
-	{GPIO_SKL_H_GPP_B22, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_22
-	{GPIO_SKL_H_GPP_B23, {
-		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
-		GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
-
-//		{GPIO_SKL_H_GPP_C0,  {} }, //GPP_C_0_SMBCLK, controlled by ME
-//		{GPIO_SKL_H_GPP_C1,  {} }, //GPP_C_1_SMBDATA, controlled by ME
-	{GPIO_SKL_H_GPP_C2,  {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_2_SMBALERT_N
-//		{GPIO_SKL_H_GPP_C3,  {} }, //GPP_C_3_SML0CLK_IE, controlled by ME
-//		{GPIO_SKL_H_GPP_C4,  {} }, //GPP_C_4_SML0DATA_IE, controlled by ME
-	{GPIO_SKL_H_GPP_C5,  {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_5_SML0ALERT_IE_N
-//		{GPIO_SKL_H_GPP_C6,  {} }, //GPP_C_6_SML1CLK_IE, controlled by ME
-//		{GPIO_SKL_H_GPP_C7,  {} }, //GPP_C_7_SML1DATA_IE, controlled by ME
-	{GPIO_SKL_H_GPP_C8,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_8
-	{GPIO_SKL_H_GPP_C9,  {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_9
-	{GPIO_SKL_H_GPP_C10, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_10
-	{GPIO_SKL_H_GPP_C11, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,	GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_11
-	{GPIO_SKL_H_GPP_C12, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_12
-	{GPIO_SKL_H_GPP_C13, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_13
-	{GPIO_SKL_H_GPP_C14, {
-		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
-		GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_14
-	{GPIO_SKL_H_GPP_C15, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_15
-	{GPIO_SKL_H_GPP_C16, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_16
-	{GPIO_SKL_H_GPP_C17, {
-		GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_17
-	{GPIO_SKL_H_GPP_C18, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_18
-	{GPIO_SKL_H_GPP_C19, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_19
-//		{GPIO_SKL_H_GPP_C20, {} }, //GPP_C_20, controlled by ME
-	{GPIO_SKL_H_GPP_C21, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_21
-	{GPIO_SKL_H_GPP_C22, {
-		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
-		GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_22
-	{GPIO_SKL_H_GPP_C23, {
-		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
-		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_C_23
-
-	{GPIO_SKL_H_GPP_D0, {
-		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault,
-		GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_0
-	{GPIO_SKL_H_GPP_D1, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_1
-	{GPIO_SKL_H_GPP_D2, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_2
-	{GPIO_SKL_H_GPP_D3, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_3
-	{GPIO_SKL_H_GPP_D4, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_4
-	{GPIO_SKL_H_GPP_D5, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_5
-	{GPIO_SKL_H_GPP_D6, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_6
-	{GPIO_SKL_H_GPP_D7, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_7
-	{GPIO_SKL_H_GPP_D8, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_8
-	{GPIO_SKL_H_GPP_D9, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_9_SSATA_DEVSLP3
-	{GPIO_SKL_H_GPP_D10, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_10_SSATA_DEVSLP4
-	{GPIO_SKL_H_GPP_D11, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_11_SSATA_DEVSLP5
-	{GPIO_SKL_H_GPP_D12, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_12_SSATA_SDATAOUT1
-	{GPIO_SKL_H_GPP_D13, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_13_SML0BLCK_IE
-	{GPIO_SKL_H_GPP_D14, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_14_SML0BDATA_IE
-	{GPIO_SKL_H_GPP_D15, {
-		GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_15_SSATA_SDATAOUT0
-	{GPIO_SKL_H_GPP_D16, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_16_SML0BALERT_IE_N
-	{GPIO_SKL_H_GPP_D17, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_17
-	{GPIO_SKL_H_GPP_D18, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_18
-	{GPIO_SKL_H_GPP_D19, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock
-		} }, //GPP_D_19
-	{GPIO_SKL_H_GPP_D20, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_20_TP_PCH_GPP_D_20
-	{GPIO_SKL_H_GPP_D21, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_21_IE_URAT_RX
-	{GPIO_SKL_H_GPP_D22, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_22_IE_URAT_TX
-	{GPIO_SKL_H_GPP_D23, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_D_23
-
-	{GPIO_SKL_H_GPP_E0, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_0_SATAXPCIE0_SATAGP0
-	{GPIO_SKL_H_GPP_E1, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_1_SATAXPCIE1_SATAGP1
-	{GPIO_SKL_H_GPP_E2, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_2_SATAXPCIE2_SATAGP2
-	{GPIO_SKL_H_GPP_E3, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_3_CPU_GP0
-	{GPIO_SKL_H_GPP_E4, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_4_SATA_DEVSLP0
-	{GPIO_SKL_H_GPP_E5, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_5_SATA_DEVSLP1
-	{GPIO_SKL_H_GPP_E6, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_6_SATA_DEVSLP2
-	{GPIO_SKL_H_GPP_E7, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_7_CPU_GP1
-	{GPIO_SKL_H_GPP_E8, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_8_SATA_LED_N
-	{GPIO_SKL_H_GPP_E9, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_9_USB2_OC0_N
-	{GPIO_SKL_H_GPP_E10, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_10_USB2_OC1_N
-	{GPIO_SKL_H_GPP_E11, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_11_USB2_OC2_N
-	{GPIO_SKL_H_GPP_E12, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_E_12_USB2_OC3_N
-
-	{GPIO_SKL_H_GPP_F0, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_0_SATAXPCIE3_SATAGP3
-	{GPIO_SKL_H_GPP_F1, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_1_SATAXPCIE4_SATAGP4
-	{GPIO_SKL_H_GPP_F2, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_2_SATAXPCIE5_SATAGP5
-	{GPIO_SKL_H_GPP_F3, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_3_SATAXPCIE6_SATAGP6
-	{GPIO_SKL_H_GPP_F4, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_4_SATAXPCIE7_SATAGP7
-	{GPIO_SKL_H_GPP_F5, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_5_SATA_DEVSLP3
-	{GPIO_SKL_H_GPP_F6, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_6_SATA_DEVSLP4
-	{GPIO_SKL_H_GPP_F7, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_7_SATA_DEVSLP5
-	{GPIO_SKL_H_GPP_F8, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_8_SATA_DEVSLP6
-	{GPIO_SKL_H_GPP_F9, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_9_SATA_DEVSLP7
-	{GPIO_SKL_H_GPP_F10, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_10_SATA_SCLOCK
-	{GPIO_SKL_H_GPP_F11, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_11_SATA_SLOAD
-	{GPIO_SKL_H_GPP_F12, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_12_SATA_SDATAOUT1
-	{GPIO_SKL_H_GPP_F13, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_13_SATA_SDATAOUT0
-	{GPIO_SKL_H_GPP_F14, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_14_SSATA_LED_N
-	{GPIO_SKL_H_GPP_F15, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_15_USB2_OC4_N
-	{GPIO_SKL_H_GPP_F16, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_16_USB2_OC5_N
-	{GPIO_SKL_H_GPP_F17, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_17_USB2_OC6_N
-	{GPIO_SKL_H_GPP_F18, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_18_USB2_OC7_N
-	{GPIO_SKL_H_GPP_F19, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_19_LAN_SMBCLK
-	{GPIO_SKL_H_GPP_F20, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_20_LAN_SMBDATA
-	{GPIO_SKL_H_GPP_F21, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_21_LAN_SMBALERT_N
-	{GPIO_SKL_H_GPP_F22, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_22_SSATA_SCLOCK
-	{GPIO_SKL_H_GPP_F23, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_F_23_SSATA_SLOAD
-
-	{GPIO_SKL_H_GPP_G0, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_0_FANTACH0_FANTACH0IE
-	{GPIO_SKL_H_GPP_G1, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_1_FANTACH1_FANTACH1IE
-	{GPIO_SKL_H_GPP_G2, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_2_FANTACH2_FANTACH2IE
-	{GPIO_SKL_H_GPP_G3, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_3_FANTACH3_FANTACH3IE
-	{GPIO_SKL_H_GPP_G4, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_4_FANTACH4_FANTACH4IE
-	{GPIO_SKL_H_GPP_G5, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_5_FANTACH5_FANTACH5IE
-	{GPIO_SKL_H_GPP_G6, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_6_FANTACH6_FANTACH6IE
-	{GPIO_SKL_H_GPP_G7, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_7_FANTACH7_FANTACH7IE
-	{GPIO_SKL_H_GPP_G8, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_8_FANPWM0_FANPWM0IE
-	{GPIO_SKL_H_GPP_G9, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_9_FANPWM1_FANPWM1IE
-	{GPIO_SKL_H_GPP_G10, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_10_FANPWM2_FANPWM2IE
-	{GPIO_SKL_H_GPP_G11, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_11_FANPWM3_FANPWM3IE
-	{GPIO_SKL_H_GPP_G12, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_12
-	{GPIO_SKL_H_GPP_G13, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_13
-	{GPIO_SKL_H_GPP_G14, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_14
-	{GPIO_SKL_H_GPP_G15, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_15
-	{GPIO_SKL_H_GPP_G16, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_16
-	{GPIO_SKL_H_GPP_G17, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_17_ADR_COMPLETE
-	{GPIO_SKL_H_GPP_G18, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_18_FM_NMI_EVENT_N
-	{GPIO_SKL_H_GPP_G19, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_19_FM_SMI_ACTIVE_N
-//		{GPIO_SKL_H_GPP_G20, {} }, //GPP_G_20_SSATA_DEVSLP0, controlled by ME
-	{GPIO_SKL_H_GPP_G21, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_21_SSATA_DEVSLP1
-	{GPIO_SKL_H_GPP_G22, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_22_SSATA_DEVSLP2
-	{GPIO_SKL_H_GPP_G23, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
-
-	{GPIO_SKL_H_GPP_H0, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_0_SRCCLKREQ6_N
-	{GPIO_SKL_H_GPP_H1, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_1_SRCCLKREQ7_N
-	{GPIO_SKL_H_GPP_H2, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_2_SRCCLKREQ8_N
-	{GPIO_SKL_H_GPP_H3, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_3_SRCCLKREQ9_N
-	{GPIO_SKL_H_GPP_H4, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_4_SRCCLKREQ10_N
-//		{GPIO_SKL_H_GPP_H5,  {} }, //GPP_H_5_SRCCLKREQ11_N
-	{GPIO_SKL_H_GPP_H6, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_6_SRCCLKREQ12_N
-	{GPIO_SKL_H_GPP_H7, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_7_SRCCLKREQ13_N
-	{GPIO_SKL_H_GPP_H8, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_8_SRCCLKREQ14_N
-	{GPIO_SKL_H_GPP_H9, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_9_SRCCLKREQ15_N
-//		{GPIO_SKL_H_GPP_H10, {} }, //GPP_H_10_SML2CLK_IE
-//		{GPIO_SKL_H_GPP_H11, {} }, //GPP_H_11_SML2DATA_IE
-	{GPIO_SKL_H_GPP_H12, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_12_SML2ALERT_N_IE
-//		{GPIO_SKL_H_GPP_H13, {} }, //GPP_H_13_SML3CLK_IE
-//		{GPIO_SKL_H_GPP_H14, {} }, //GPP_H_14_SML3DATA_IE
-	{GPIO_SKL_H_GPP_H15, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_15_SML3ALERT_N_IE
-//		{GPIO_SKL_H_GPP_H16, {} }, //GPP_H_16_SML4CLK_IE
-//		{GPIO_SKL_H_GPP_H17, {} }, //GPP_H_17_SML4DATA_IE
-	{GPIO_SKL_H_GPP_H18, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_18_SML4ALERT_N_IE
-	{GPIO_SKL_H_GPP_H19, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
-	{GPIO_SKL_H_GPP_H20, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
-	{GPIO_SKL_H_GPP_H21, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
-	{GPIO_SKL_H_GPP_H22, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
-	{GPIO_SKL_H_GPP_H23, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
-		} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
-
-	{GPIO_SKL_H_GPP_I0, {
-		GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_0_GBE_TDO
-	{GPIO_SKL_H_GPP_I1, {
-		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_1_GBE_TCK
-	{GPIO_SKL_H_GPP_I2, {
-		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_2_GBE_TMS
-	{GPIO_SKL_H_GPP_I3, {
-		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_3_GBE_TDI
-	{GPIO_SKL_H_GPP_I4, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_4_DO_RESET_IN_N
-	{GPIO_SKL_H_GPP_I5, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_5_DO_RESET_OUT_N
-	{GPIO_SKL_H_GPP_I6, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_6_RESET_DONE
-	{GPIO_SKL_H_GPP_I7, {
-		GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_7_JTAG_GBE_TRST_N
-	{GPIO_SKL_H_GPP_I8, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_8_GBE_PCI_DIS
-	{GPIO_SKL_H_GPP_I9, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_9_GBE_LAN_DIS
-	{GPIO_SKL_H_GPP_I10, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_I_10
-
-	{GPIO_SKL_H_GPP_J0, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_0_LAN_LED_P0_0
-	{GPIO_SKL_H_GPP_J1, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_1_LAN_LED_P0_1
-	{GPIO_SKL_H_GPP_J2, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_2_LAN_LED_P1_0
-	{GPIO_SKL_H_GPP_J3, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_3_LAN_LED_P1_1
-	{GPIO_SKL_H_GPP_J4, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_4_LAN_LED_P2_0
-	{GPIO_SKL_H_GPP_J5, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_5_LAN_LED_P2_1
-	{GPIO_SKL_H_GPP_J6, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_6_LAN_LED_P3_0
-	{GPIO_SKL_H_GPP_J7, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_7_LAN_LED_P3_1
-	{GPIO_SKL_H_GPP_J8, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
-	{GPIO_SKL_H_GPP_J9, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
-	{GPIO_SKL_H_GPP_J10, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
-	{GPIO_SKL_H_GPP_J11, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
-	{GPIO_SKL_H_GPP_J12, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
-	{GPIO_SKL_H_GPP_J13, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
-	{GPIO_SKL_H_GPP_J14, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
-	{GPIO_SKL_H_GPP_J15, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
-	{GPIO_SKL_H_GPP_J16, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_16_LAN_SDP_P0_0
-	{GPIO_SKL_H_GPP_J17, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_17_LAN_SDP_P0_1
-	{GPIO_SKL_H_GPP_J18, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_18_LAN_SDP_P1_0
-	{GPIO_SKL_H_GPP_J19, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_19_LAN_SDP_P1_1
-	{GPIO_SKL_H_GPP_J20, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_20_LAN_SDP_P2_0
-	{GPIO_SKL_H_GPP_J21, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_21_LAN_SDP_P2_1
-	{GPIO_SKL_H_GPP_J22, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_22_LAN_SDP_P3_0
-	{GPIO_SKL_H_GPP_J23, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_J_23_LAN_SDP_P3_1
-
-	{GPIO_SKL_H_GPP_K0, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_0_LAN_NCSI_CLK_IN
-	{GPIO_SKL_H_GPP_K1, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_1_LAN_NCSI_TXD0
-	{GPIO_SKL_H_GPP_K2, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_2_LAN_NCSI_TXD1
-	{GPIO_SKL_H_GPP_K3, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_3_LAN_NCSI_TX_EN
-	{GPIO_SKL_H_GPP_K4, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_4_LAN_NCSI_CRS_DV
-	{GPIO_SKL_H_GPP_K5, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_5_LAN_NCSI_RXD0
-	{GPIO_SKL_H_GPP_K6, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_6_LAN_NCSI_RXD1
-	{GPIO_SKL_H_GPP_K7, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_7
-	{GPIO_SKL_H_GPP_K8, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_8_LAN_NCSI_ARB_IN
-	{GPIO_SKL_H_GPP_K9, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_9_LAN_NCSI_ARB_OUT
-	{GPIO_SKL_H_GPP_K10, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_K_10_PE_RST_N
-
-	{GPIO_SKL_H_GPP_L2, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_2_TESTCH0_D0
-	{GPIO_SKL_H_GPP_L3, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_3_TESTCH0_D1
-	{GPIO_SKL_H_GPP_L4, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_4_TESTCH0_D2
-	{GPIO_SKL_H_GPP_L5, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_5_TESTCH0_D3
-	{GPIO_SKL_H_GPP_L6, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_6_TESTCH0_D4
-	{GPIO_SKL_H_GPP_L7, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_7_TESTCH0_D5
-	{GPIO_SKL_H_GPP_L8, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_8_TESTCH0_D6
-	{GPIO_SKL_H_GPP_L9, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_9_TESTCH0_D7
-	{GPIO_SKL_H_GPP_L10, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_10_TESTCH0_CLK
-	{GPIO_SKL_H_GPP_L11, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_11_TESTCH1_D0
-	{GPIO_SKL_H_GPP_L12, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_12_TESTCH1_D1
-	{GPIO_SKL_H_GPP_L13, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_13_TESTCH1_D2
-	{GPIO_SKL_H_GPP_L14, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_14_TESTCH1_D3
-	{GPIO_SKL_H_GPP_L15, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_15_TESTCH1_D4
-	{GPIO_SKL_H_GPP_L16, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_16_TESTCH1_D5
-	{GPIO_SKL_H_GPP_L17, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_17_TESTCH1_D6
-	{GPIO_SKL_H_GPP_L18, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_18_TESTCH1_D7
-	{GPIO_SKL_H_GPP_L19, {
-		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
-		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
-		} }, //GPP_L_19_TESTCH1_CLK
-
-	{GPIO_SKL_H_GPD0,	{} }, //GPD_0, controlled by ME
-	{GPIO_SKL_H_GPD1,	{
-		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_1_ACPRESENT
-	{GPIO_SKL_H_GPD2,	{
-		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_2_GBE_WAKE_N
-	{GPIO_SKL_H_GPD3,	{
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_3_PWRBTNB_N
-	{GPIO_SKL_H_GPD4,	{
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_4_SLP_S3B
-	{GPIO_SKL_H_GPD5,	{
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_5_SLP_S4B
-	{GPIO_SKL_H_GPD6,	{
-		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_6_SLPA_N
-	{GPIO_SKL_H_GPD7,	{
-		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_7
-	{GPIO_SKL_H_GPD8,	{
-		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
-	{GPIO_SKL_H_GPD9,	{
-		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_9
-	{GPIO_SKL_H_GPD10, {
-		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_10_FM_SLPS5_N
-	{GPIO_SKL_H_GPD11, {
-		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
-		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
-		} }, //GPD_11_GBEPHY
-};
-
-#endif /* _SKXSP_TP_GPIO_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h
deleted file mode 100644
index ac230ef78b..0000000000
--- a/src/soc/intel/xeon_sp/skx/include/soc/gpio_soc_defs.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _GPIO_SOC_DEFS_H_
-#define _GPIO_SOC_DEFS_H_
-
-///
-/// Skylake-SP chipset GPIO Groups
-///
-#define GPIO_SKL_H_GROUP_GPP_A  0x0100
-#define GPIO_SKL_H_GROUP_GPP_B  0x0101
-#define GPIO_SKL_H_GROUP_GPP_C  0x0102
-#define GPIO_SKL_H_GROUP_GPP_D  0x0103
-#define GPIO_SKL_H_GROUP_GPP_E  0x0104
-#define GPIO_SKL_H_GROUP_GPP_F  0x0105
-#define GPIO_SKL_H_GROUP_GPP_G  0x0106
-#define GPIO_SKL_H_GROUP_GPP_H  0x0107
-#define GPIO_SKL_H_GROUP_GPP_I  0x0108
-#define GPIO_SKL_H_GROUP_GPP_J  0x0109
-#define GPIO_SKL_H_GROUP_GPP_K  0x010A
-#define GPIO_SKL_H_GROUP_GPP_L  0x010B
-#define GPIO_SKL_H_GROUP_GPD    0x010C
-
-///
-/// SKL H GPIO pins
-///
-#define GPIO_SKL_H_GPP_A0       0x01000000
-#define GPIO_SKL_H_GPP_A1       0x01000001
-#define GPIO_SKL_H_GPP_A2       0x01000002
-#define GPIO_SKL_H_GPP_A3       0x01000003
-#define GPIO_SKL_H_GPP_A4       0x01000004
-#define GPIO_SKL_H_GPP_A5       0x01000005
-#define GPIO_SKL_H_GPP_A6       0x01000006
-#define GPIO_SKL_H_GPP_A7       0x01000007
-#define GPIO_SKL_H_GPP_A8       0x01000008
-#define GPIO_SKL_H_GPP_A9       0x01000009
-#define GPIO_SKL_H_GPP_A10      0x0100000A
-#define GPIO_SKL_H_GPP_A11      0x0100000B
-#define GPIO_SKL_H_GPP_A12      0x0100000C
-#define GPIO_SKL_H_GPP_A13      0x0100000D
-#define GPIO_SKL_H_GPP_A14      0x0100000E
-#define GPIO_SKL_H_GPP_A15      0x0100000F
-#define GPIO_SKL_H_GPP_A16      0x01000010
-#define GPIO_SKL_H_GPP_A17      0x01000011
-#define GPIO_SKL_H_GPP_A18      0x01000012
-#define GPIO_SKL_H_GPP_A19      0x01000013
-#define GPIO_SKL_H_GPP_A20      0x01000014
-#define GPIO_SKL_H_GPP_A21      0x01000015
-#define GPIO_SKL_H_GPP_A22      0x01000016
-#define GPIO_SKL_H_GPP_A23      0x01000017
-#define GPIO_SKL_H_GPP_B0       0x01010000
-#define GPIO_SKL_H_GPP_B1       0x01010001
-#define GPIO_SKL_H_GPP_B2       0x01010002
-#define GPIO_SKL_H_GPP_B3       0x01010003
-#define GPIO_SKL_H_GPP_B4       0x01010004
-#define GPIO_SKL_H_GPP_B5       0x01010005
-#define GPIO_SKL_H_GPP_B6       0x01010006
-#define GPIO_SKL_H_GPP_B7       0x01010007
-#define GPIO_SKL_H_GPP_B8       0x01010008
-#define GPIO_SKL_H_GPP_B9       0x01010009
-#define GPIO_SKL_H_GPP_B10      0x0101000A
-#define GPIO_SKL_H_GPP_B11      0x0101000B
-#define GPIO_SKL_H_GPP_B12      0x0101000C
-#define GPIO_SKL_H_GPP_B13      0x0101000D
-#define GPIO_SKL_H_GPP_B14      0x0101000E
-#define GPIO_SKL_H_GPP_B15      0x0101000F
-#define GPIO_SKL_H_GPP_B16      0x01010010
-#define GPIO_SKL_H_GPP_B17      0x01010011
-#define GPIO_SKL_H_GPP_B18      0x01010012
-#define GPIO_SKL_H_GPP_B19      0x01010013
-#define GPIO_SKL_H_GPP_B20      0x01010014
-#define GPIO_SKL_H_GPP_B21      0x01010015
-#define GPIO_SKL_H_GPP_B22      0x01010016
-#define GPIO_SKL_H_GPP_B23      0x01010017
-#define GPIO_SKL_H_GPP_C0       0x01020000
-#define GPIO_SKL_H_GPP_C1       0x01020001
-#define GPIO_SKL_H_GPP_C2       0x01020002
-#define GPIO_SKL_H_GPP_C3       0x01020003
-#define GPIO_SKL_H_GPP_C4       0x01020004
-#define GPIO_SKL_H_GPP_C5       0x01020005
-#define GPIO_SKL_H_GPP_C6       0x01020006
-#define GPIO_SKL_H_GPP_C7       0x01020007
-#define GPIO_SKL_H_GPP_C8       0x01020008
-#define GPIO_SKL_H_GPP_C9       0x01020009
-#define GPIO_SKL_H_GPP_C10      0x0102000A
-#define GPIO_SKL_H_GPP_C11      0x0102000B
-#define GPIO_SKL_H_GPP_C12      0x0102000C
-#define GPIO_SKL_H_GPP_C13      0x0102000D
-#define GPIO_SKL_H_GPP_C14      0x0102000E
-#define GPIO_SKL_H_GPP_C15      0x0102000F
-#define GPIO_SKL_H_GPP_C16      0x01020010
-#define GPIO_SKL_H_GPP_C17      0x01020011
-#define GPIO_SKL_H_GPP_C18      0x01020012
-#define GPIO_SKL_H_GPP_C19      0x01020013
-#define GPIO_SKL_H_GPP_C20      0x01020014
-#define GPIO_SKL_H_GPP_C21      0x01020015
-#define GPIO_SKL_H_GPP_C22      0x01020016
-#define GPIO_SKL_H_GPP_C23      0x01020017
-#define GPIO_SKL_H_GPP_D0       0x01030000
-#define GPIO_SKL_H_GPP_D1       0x01030001
-#define GPIO_SKL_H_GPP_D2       0x01030002
-#define GPIO_SKL_H_GPP_D3       0x01030003
-#define GPIO_SKL_H_GPP_D4       0x01030004
-#define GPIO_SKL_H_GPP_D5       0x01030005
-#define GPIO_SKL_H_GPP_D6       0x01030006
-#define GPIO_SKL_H_GPP_D7       0x01030007
-#define GPIO_SKL_H_GPP_D8       0x01030008
-#define GPIO_SKL_H_GPP_D9       0x01030009
-#define GPIO_SKL_H_GPP_D10      0x0103000A
-#define GPIO_SKL_H_GPP_D11      0x0103000B
-#define GPIO_SKL_H_GPP_D12      0x0103000C
-#define GPIO_SKL_H_GPP_D13      0x0103000D
-#define GPIO_SKL_H_GPP_D14      0x0103000E
-#define GPIO_SKL_H_GPP_D15      0x0103000F
-#define GPIO_SKL_H_GPP_D16      0x01030010
-#define GPIO_SKL_H_GPP_D17      0x01030011
-#define GPIO_SKL_H_GPP_D18      0x01030012
-#define GPIO_SKL_H_GPP_D19      0x01030013
-#define GPIO_SKL_H_GPP_D20      0x01030014
-#define GPIO_SKL_H_GPP_D21      0x01030015
-#define GPIO_SKL_H_GPP_D22      0x01030016
-#define GPIO_SKL_H_GPP_D23      0x01030017
-#define GPIO_SKL_H_GPP_E0       0x01040000
-#define GPIO_SKL_H_GPP_E1       0x01040001
-#define GPIO_SKL_H_GPP_E2       0x01040002
-#define GPIO_SKL_H_GPP_E3       0x01040003
-#define GPIO_SKL_H_GPP_E4       0x01040004
-#define GPIO_SKL_H_GPP_E5       0x01040005
-#define GPIO_SKL_H_GPP_E6       0x01040006
-#define GPIO_SKL_H_GPP_E7       0x01040007
-#define GPIO_SKL_H_GPP_E8       0x01040008
-#define GPIO_SKL_H_GPP_E9       0x01040009
-#define GPIO_SKL_H_GPP_E10      0x0104000A
-#define GPIO_SKL_H_GPP_E11      0x0104000B
-#define GPIO_SKL_H_GPP_E12      0x0104000C
-#define GPIO_SKL_H_GPP_F0       0x01050000
-#define GPIO_SKL_H_GPP_F1       0x01050001
-#define GPIO_SKL_H_GPP_F2       0x01050002
-#define GPIO_SKL_H_GPP_F3       0x01050003
-#define GPIO_SKL_H_GPP_F4       0x01050004
-#define GPIO_SKL_H_GPP_F5       0x01050005
-#define GPIO_SKL_H_GPP_F6       0x01050006
-#define GPIO_SKL_H_GPP_F7       0x01050007
-#define GPIO_SKL_H_GPP_F8       0x01050008
-#define GPIO_SKL_H_GPP_F9       0x01050009
-#define GPIO_SKL_H_GPP_F10      0x0105000A
-#define GPIO_SKL_H_GPP_F11      0x0105000B
-#define GPIO_SKL_H_GPP_F12      0x0105000C
-#define GPIO_SKL_H_GPP_F13      0x0105000D
-#define GPIO_SKL_H_GPP_F14      0x0105000E
-#define GPIO_SKL_H_GPP_F15      0x0105000F
-#define GPIO_SKL_H_GPP_F16      0x01050010
-#define GPIO_SKL_H_GPP_F17      0x01050011
-#define GPIO_SKL_H_GPP_F18      0x01050012
-#define GPIO_SKL_H_GPP_F19      0x01050013
-#define GPIO_SKL_H_GPP_F20      0x01050014
-#define GPIO_SKL_H_GPP_F21      0x01050015
-#define GPIO_SKL_H_GPP_F22      0x01050016
-#define GPIO_SKL_H_GPP_F23      0x01050017
-#define GPIO_SKL_H_GPP_G0       0x01060000
-#define GPIO_SKL_H_GPP_G1       0x01060001
-#define GPIO_SKL_H_GPP_G2       0x01060002
-#define GPIO_SKL_H_GPP_G3       0x01060003
-#define GPIO_SKL_H_GPP_G4       0x01060004
-#define GPIO_SKL_H_GPP_G5       0x01060005
-#define GPIO_SKL_H_GPP_G6       0x01060006
-#define GPIO_SKL_H_GPP_G7       0x01060007
-#define GPIO_SKL_H_GPP_G8       0x01060008
-#define GPIO_SKL_H_GPP_G9       0x01060009
-#define GPIO_SKL_H_GPP_G10      0x0106000A
-#define GPIO_SKL_H_GPP_G11      0x0106000B
-#define GPIO_SKL_H_GPP_G12      0x0106000C
-#define GPIO_SKL_H_GPP_G13      0x0106000D
-#define GPIO_SKL_H_GPP_G14      0x0106000E
-#define GPIO_SKL_H_GPP_G15      0x0106000F
-#define GPIO_SKL_H_GPP_G16      0x01060010
-#define GPIO_SKL_H_GPP_G17      0x01060011
-#define GPIO_SKL_H_GPP_G18      0x01060012
-#define GPIO_SKL_H_GPP_G19      0x01060013
-#define GPIO_SKL_H_GPP_G20      0x01060014
-#define GPIO_SKL_H_GPP_G21      0x01060015
-#define GPIO_SKL_H_GPP_G22      0x01060016
-#define GPIO_SKL_H_GPP_G23      0x01060017
-#define GPIO_SKL_H_GPP_H0       0x01070000
-#define GPIO_SKL_H_GPP_H1       0x01070001
-#define GPIO_SKL_H_GPP_H2       0x01070002
-#define GPIO_SKL_H_GPP_H3       0x01070003
-#define GPIO_SKL_H_GPP_H4       0x01070004
-#define GPIO_SKL_H_GPP_H5       0x01070005
-#define GPIO_SKL_H_GPP_H6       0x01070006
-#define GPIO_SKL_H_GPP_H7       0x01070007
-#define GPIO_SKL_H_GPP_H8       0x01070008
-#define GPIO_SKL_H_GPP_H9       0x01070009
-#define GPIO_SKL_H_GPP_H10      0x0107000A
-#define GPIO_SKL_H_GPP_H11      0x0107000B
-#define GPIO_SKL_H_GPP_H12      0x0107000C
-#define GPIO_SKL_H_GPP_H13      0x0107000D
-#define GPIO_SKL_H_GPP_H14      0x0107000E
-#define GPIO_SKL_H_GPP_H15      0x0107000F
-#define GPIO_SKL_H_GPP_H16      0x01070010
-#define GPIO_SKL_H_GPP_H17      0x01070011
-#define GPIO_SKL_H_GPP_H18      0x01070012
-#define GPIO_SKL_H_GPP_H19      0x01070013
-#define GPIO_SKL_H_GPP_H20      0x01070014
-#define GPIO_SKL_H_GPP_H21      0x01070015
-#define GPIO_SKL_H_GPP_H22      0x01070016
-#define GPIO_SKL_H_GPP_H23      0x01070017
-#define GPIO_SKL_H_GPP_I0       0x01080000
-#define GPIO_SKL_H_GPP_I1       0x01080001
-#define GPIO_SKL_H_GPP_I2       0x01080002
-#define GPIO_SKL_H_GPP_I3       0x01080003
-#define GPIO_SKL_H_GPP_I4       0x01080004
-#define GPIO_SKL_H_GPP_I5       0x01080005
-#define GPIO_SKL_H_GPP_I6       0x01080006
-#define GPIO_SKL_H_GPP_I7       0x01080007
-#define GPIO_SKL_H_GPP_I8       0x01080008
-#define GPIO_SKL_H_GPP_I9       0x01080009
-#define GPIO_SKL_H_GPP_I10      0x0108000A
-
-#define GPIO_SKL_H_GPP_J0       0x01090000
-#define GPIO_SKL_H_GPP_J1       0x01090001
-#define GPIO_SKL_H_GPP_J2       0x01090002
-#define GPIO_SKL_H_GPP_J3       0x01090003
-#define GPIO_SKL_H_GPP_J4       0x01090004
-#define GPIO_SKL_H_GPP_J5       0x01090005
-#define GPIO_SKL_H_GPP_J6       0x01090006
-#define GPIO_SKL_H_GPP_J7       0x01090007
-#define GPIO_SKL_H_GPP_J8       0x01090008
-#define GPIO_SKL_H_GPP_J9       0x01090009
-#define GPIO_SKL_H_GPP_J10      0x0109000A
-#define GPIO_SKL_H_GPP_J11      0x0109000B
-#define GPIO_SKL_H_GPP_J12      0x0109000C
-#define GPIO_SKL_H_GPP_J13      0x0109000D
-#define GPIO_SKL_H_GPP_J14      0x0109000E
-#define GPIO_SKL_H_GPP_J15      0x0109000F
-#define GPIO_SKL_H_GPP_J16      0x01090010
-#define GPIO_SKL_H_GPP_J17      0x01090011
-#define GPIO_SKL_H_GPP_J18      0x01090012
-#define GPIO_SKL_H_GPP_J19      0x01090013
-#define GPIO_SKL_H_GPP_J20      0x01090014
-#define GPIO_SKL_H_GPP_J21      0x01090015
-#define GPIO_SKL_H_GPP_J22      0x01090016
-#define GPIO_SKL_H_GPP_J23      0x01090017
-#define GPIO_SKL_H_GPP_K0       0x010A0000
-#define GPIO_SKL_H_GPP_K1       0x010A0001
-#define GPIO_SKL_H_GPP_K2       0x010A0002
-#define GPIO_SKL_H_GPP_K3       0x010A0003
-#define GPIO_SKL_H_GPP_K4       0x010A0004
-#define GPIO_SKL_H_GPP_K5       0x010A0005
-#define GPIO_SKL_H_GPP_K6       0x010A0006
-#define GPIO_SKL_H_GPP_K7       0x010A0007
-#define GPIO_SKL_H_GPP_K8       0x010A0008
-#define GPIO_SKL_H_GPP_K9       0x010A0009
-#define GPIO_SKL_H_GPP_K10      0x010A000A
-#define GPIO_SKL_H_GPP_L2       0x010B0002
-#define GPIO_SKL_H_GPP_L3       0x010B0003
-#define GPIO_SKL_H_GPP_L4       0x010B0004
-#define GPIO_SKL_H_GPP_L5       0x010B0005
-#define GPIO_SKL_H_GPP_L6       0x010B0006
-#define GPIO_SKL_H_GPP_L7       0x010B0007
-#define GPIO_SKL_H_GPP_L8       0x010B0008
-#define GPIO_SKL_H_GPP_L9       0x010B0009
-#define GPIO_SKL_H_GPP_L10      0x010B000A
-#define GPIO_SKL_H_GPP_L11      0x010B000B
-#define GPIO_SKL_H_GPP_L12      0x010B000C
-#define GPIO_SKL_H_GPP_L13      0x010B000D
-#define GPIO_SKL_H_GPP_L14      0x010B000E
-#define GPIO_SKL_H_GPP_L15      0x010B000F
-#define GPIO_SKL_H_GPP_L16      0x010B0010
-#define GPIO_SKL_H_GPP_L17      0x010B0011
-#define GPIO_SKL_H_GPP_L18      0x010B0012
-#define GPIO_SKL_H_GPP_L19      0x010B0013
-#define GPIO_SKL_H_GPD0         0x010C0000
-#define GPIO_SKL_H_GPD1         0x010C0001
-#define GPIO_SKL_H_GPD2         0x010C0002
-#define GPIO_SKL_H_GPD3         0x010C0003
-#define GPIO_SKL_H_GPD4         0x010C0004
-#define GPIO_SKL_H_GPD5         0x010C0005
-#define GPIO_SKL_H_GPD6         0x010C0006
-#define GPIO_SKL_H_GPD7         0x010C0007
-#define GPIO_SKL_H_GPD8         0x010C0008
-#define GPIO_SKL_H_GPD9         0x010C0009
-#define GPIO_SKL_H_GPD10        0x010C000A
-#define GPIO_SKL_H_GPD11        0x010C000B
-
-#endif