diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-10 00:23:58 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-29 10:15:24 +0000 |
| commit | d0bc92df73d7653ed8b6c76baf3a39c7f8f37173 (patch) | |
| tree | 9d4eaa1787fb8a016c841a661bec9f0171314190 /src | |
| parent | ae38035d3a6c8892bf734bac19ddf052365e9b4c (diff) | |
intel/fsp1_1: Declare fsp_load() as static
The function has only one local call-site.
Change-Id: I623953796e6cd3a8e5b4f72293d953b61f14a5a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49999
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 6 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/ramstage.c | 8 |
2 files changed, 1 insertions, 13 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index 0a6295edc5..f925088e00 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -6,12 +6,6 @@ #include <fsp/util.h> #include <stdint.h> -/* - * Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately - * from calling silicon init. It might be required in cases where stage cache is - * no longer available by the point SoC calls into silicon init. - */ -void fsp_load(void); /* Perform Intel silicon init. */ void intel_silicon_init(void); void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index eb226dbb65..5fff60ac1a 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -173,15 +173,11 @@ static int fsp_find_and_relocate(struct prog *fsp) return 0; } -void fsp_load(void) +static void fsp_load(void) { - static int load_done; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); int is_s3_wakeup = acpi_is_wakeup_s3(); - if (load_done) - return; - if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsp); @@ -192,8 +188,6 @@ void fsp_load(void) /* FSP_INFO_HEADER is set as the program entry. */ fsp_update_fih(prog_entry(&fsp)); - - load_done = 1; } void intel_silicon_init(void) |