soc/intel/baytrail,braswell: Drop TOLM from GNVS

It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.

Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50121
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 30 insertions, 12 deletions

diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index d379bebd81..5433fdc4c5 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -60,9 +60,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
-
-	/* Top of Low Memory (start of resource allocation) */
-	gnvs->tolm = nc_read_top_of_low_memory();
 }
 
 int acpi_sci_irq(void)
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index 3d2b3dcdd9..cffb2241f0 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -40,7 +40,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* Base addresses */
 	Offset (0x30),
 	,	 32,	/* 0x30 - CBMEM TOC */
-	TOLM,	 32,	/* 0x34 - Top of Low Memory */
+	,	 32,	/* 0x34 - Top of Low Memory */
 	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
 }
 
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 75f248677b..ab273448ca 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -30,6 +30,8 @@ Scope(\)
 	}
 }
 
+External (\TOLM, IntObj)
+
 Name(_HID,EISAID("PNP0A08"))	/* PCIe */
 Name(_CID,EISAID("PNP0A03"))	/* PCI */
 
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index d221009db1..310ce4d552 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -1,15 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <acpi/acpi.h>
 #include <stdint.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /*
  * Host Memory Map:
@@ -123,9 +124,18 @@ static void nc_read_resources(struct device *dev)
 		chromeos_reserve_ram_oops(dev, index++);
 }
 
+static void nc_generate_ssdt(const struct device *dev)
+{
+	generate_cpu_entries(dev);
+
+	acpigen_write_scope("\\");
+	acpigen_write_name_dword("TOLM", nc_read_top_of_low_memory());
+	acpigen_pop_len();
+}
+
 static struct device_operations nc_ops = {
 	.read_resources   = nc_read_resources,
-	.acpi_fill_ssdt   = generate_cpu_entries,
+	.acpi_fill_ssdt   = nc_generate_ssdt,
 	.ops_pci          = &soc_pci_ops,
 };
 
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 70fd9930d9..dbb883503f 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -64,9 +64,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* Top of Low Memory (start of resource allocation) */
-	gnvs->tolm = nc_read_top_of_low_memory();
-
 	/* Fill in the Wi-Fi Region ID */
 	if (CONFIG(HAVE_REGULATORY_DOMAIN))
 		gnvs->cid1 = wifi_regulatory_domain();
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 22af61bc82..9a436710aa 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -42,7 +42,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* Base addresses */
 	Offset (0x30),
 	,	 32,	/* 0x30 - CBMEM TOC */
-	TOLM,	 32,	/* 0x34 - Top of Low Memory */
+	,	 32,	/* 0x34 - Top of Low Memory */
 	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
 }
 
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index 8fa95ef337..64bff1227f 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -30,6 +30,8 @@ Scope(\)
 	}
 }
 
+External (\TOLM, IntObj)
+
 Name(_HID,EISAID("PNP0A08"))	/* PCIe */
 Name(_CID,EISAID("PNP0A03"))	/* PCI */
 
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 0b47e2f0c3..0ef58b2470 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <cbmem.h>
 #include <cpu/x86/smm.h>
 #include <device/device.h>
@@ -149,9 +150,18 @@ static void nc_read_resources(struct device *dev)
 		chromeos_reserve_ram_oops(dev, index++);
 }
 
+static void nc_generate_ssdt(const struct device *dev)
+{
+	generate_cpu_entries(dev);
+
+	acpigen_write_scope("\\");
+	acpigen_write_name_dword("TOLM", nc_read_top_of_low_memory());
+	acpigen_pop_len();
+}
+
 static struct device_operations nc_ops = {
-	.acpi_fill_ssdt	= generate_cpu_entries,
 	.read_resources	= nc_read_resources,
+	.acpi_fill_ssdt	= nc_generate_ssdt,
 	.ops_pci	= &soc_pci_ops,
 };