diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-05-03 12:32:17 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-16 13:23:31 +0000 |
| commit | cf0236972d06ff02880619beb7a891a0d3011184 (patch) | |
| tree | 53b0a76a12a1eb73fccc9798c9e9708247e63c1b /src | |
| parent | 6438084eab6cfe3047fe64966e2b473aa96529de (diff) | |
mb/siemens/mc_ehl2: Set PCH TSN link speed to 1 Gbps in devicetree
TSN runs in SGMII mode on this mainboard. This requires setting the link
speed to 1 Gbps.
Change-Id: I9f1da971b4de5671d6d38be6dbc50edbbe20d157
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 72e4b0f2da..f74b504e0d 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -101,7 +101,7 @@ chip soc/intel/elkhartlake }" # TSN GBE related UPDs - register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" + register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps" register "PchTsnGbeSgmiiEnable" = "1" register "PseTsnGbeSgmiiEnable[0]" = "1" register "PseTsnGbeSgmiiEnable[1]" = "1" |