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authorFelix Held <felix-coreboot@felixheld.de>2022-02-07 15:27:27 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-08 17:09:18 +0000
commitceefc74f01bcfe070477107d0677acf6b9d9c372 (patch)
tree98acbdc66b0b2992f1054d3925b2f389d23d1e1e /src
parent45ba318b2a7348a24f2f073cc0258018d31a9b47 (diff)
soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO
Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to configure the PCI MMCONF base address. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/sabrina/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 43c96c0c5d..239a0e800f 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -59,7 +59,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct
- select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct
+ select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct