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authorRonak Kanabar <ronak.kanabar@intel.com>2021-05-12 18:44:30 +0530
committerDavid Hendricks <david.hendricks@gmail.com>2021-05-16 22:17:26 +0000
commitc4813ea2604600476fa3c95557135b3225f404aa (patch)
tree4f13dec38bea020a08663399669c34135c023860 /src
parent3704c65f08aa56e252cee9bf0b90d9173b20204c (diff)
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00
The headers added are generated as per FSP v2162_00. Previous FSP version was v2117_00. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Remove DisableDimmMc*Ch* Upds in FspmUpd.h - Add DisableMc*Ch* Upds in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid compilation failure other change related to UPDs name change will be part of next patch in relation chain. BUG=b:187189546 BRANCH=None TEST=Build and boot ADLRVP using all the patch in relation chain. Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/alderlake/meminit.c16
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h1006
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h1160
3 files changed, 1092 insertions, 1090 deletions
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 33f26da87f..2c46b07ec5 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -133,14 +133,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
[7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, },
};
uint8_t *disable_dimm_upds[MRC_CHANNELS] = {
- &mem_cfg->DisableDimmMc0Ch0,
- &mem_cfg->DisableDimmMc0Ch1,
- &mem_cfg->DisableDimmMc0Ch2,
- &mem_cfg->DisableDimmMc0Ch3,
- &mem_cfg->DisableDimmMc1Ch0,
- &mem_cfg->DisableDimmMc1Ch1,
- &mem_cfg->DisableDimmMc1Ch2,
- &mem_cfg->DisableDimmMc1Ch3,
+ &mem_cfg->DisableMc0Ch0,
+ &mem_cfg->DisableMc0Ch1,
+ &mem_cfg->DisableMc0Ch2,
+ &mem_cfg->DisableMc0Ch3,
+ &mem_cfg->DisableMc1Ch0,
+ &mem_cfg->DisableMc1Ch1,
+ &mem_cfg->DisableMc1Ch2,
+ &mem_cfg->DisableMc1Ch3,
};
size_t ch, dimm;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
index f6bba7d929..2c04f90781 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
@@ -324,7 +324,7 @@ typedef struct {
UINT8 DciDbcMode;
/** Offset 0x0193 - Enable DCI ModPHY Power Gate
- Enable ModPHY Power Gate when DCI is enabled
+ DEPRECATED
$EN_DIS
**/
UINT8 DciModphyPg;
@@ -485,52 +485,52 @@ typedef struct {
UINT8 RMT;
/** Offset 0x01D8 - Controller 0 Channel 0 DIMM Control
- Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+ Enable / Disable DIMMs on Controller 0 Channel 0
+ $EN_DIS
**/
- UINT8 DisableDimmMc0Ch0;
+ UINT8 DisableMc0Ch0;
/** Offset 0x01D9 - Controller 0 Channel 1 DIMM Control
- Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+ Enable / Disable DIMMs on Controller 0 Channel 1
+ $EN_DIS
**/
- UINT8 DisableDimmMc0Ch1;
+ UINT8 DisableMc0Ch1;
/** Offset 0x01DA - Controller 0 Channel 2 DIMM Control
- Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+ Enable / Disable DIMMs on Controller 0 Channel 2
+ $EN_DIS
**/
- UINT8 DisableDimmMc0Ch2;
+ UINT8 DisableMc0Ch2;
/** Offset 0x01DB - Controller 0 Channel 3 DIMM Control
- Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+ Enable / Disable DIMMs on Controller 0 Channel 3
+ $EN_DIS
**/
- UINT8 DisableDimmMc0Ch3;
+ UINT8 DisableMc0Ch3;
/** Offset 0x01DC - Controller 1 Channel 0 DIMM Control
- Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+ Enable / Disable DIMMs on Controller 1 Channel 0
+ $EN_DIS
**/
- UINT8 DisableDimmMc1Ch0;
+ UINT8 DisableMc1Ch0;
/** Offset 0x01DD - Controller 1 Channel 1 DIMM Control
- Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+ Enable / Disable DIMMs on Controller 1 Channel 1
+ $EN_DIS
**/
- UINT8 DisableDimmMc1Ch1;
+ UINT8 DisableMc1Ch1;
/** Offset 0x01DE - Controller 1 Channel 2 DIMM Control
- Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+ Enable / Disable DIMMs on Controller 1 Channel 2
+ $EN_DIS
**/
- UINT8 DisableDimmMc1Ch2;
+ UINT8 DisableMc1Ch2;
/** Offset 0x01DF - Controller 1 Channel 3 DIMM Control
- Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+ Enable / Disable DIMMs on Controller 1 Channel 3
+ $EN_DIS
**/
- UINT8 DisableDimmMc1Ch3;
+ UINT8 DisableMc1Ch3;
/** Offset 0x01E0 - Scrambler Support
This option enables data scrambling in memory.
@@ -557,9 +557,7 @@ typedef struct {
/** Offset 0x01E4 - Memory Voltage
DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
- chips) in millivolts. <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
- 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
- Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+ chips) in millivolts from 0 - default to 1435mv.
**/
UINT16 VddVoltage;
@@ -1055,29 +1053,29 @@ typedef struct {
/** Offset 0x02A2 - Reserved
**/
- UINT8 Reserved11[110];
+ UINT8 Reserved11[111];
-/** Offset 0x0310 - Enable Gt CLOS
+/** Offset 0x0311 - Enable Gt CLOS
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 GtClosEnable;
-/** Offset 0x0311 - DMI Max Link Speed
+/** Offset 0x0312 - DMI Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
**/
UINT8 DmiMaxLinkSpeed;
-/** Offset 0x0312 - DMI Equalization Phase 2
+/** Offset 0x0313 - DMI Equalization Phase 2
DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
AUTO - Use the current default method
0:Disable phase2, 1:Enable phase2, 2:Auto
**/
UINT8 DmiGen3EqPh2Enable;
-/** Offset 0x0313 - DMI Gen3 Equalization Phase3
+/** Offset 0x0314 - DMI Gen3 Equalization Phase3
DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
@@ -1087,67 +1085,67 @@ typedef struct {
**/
UINT8 DmiGen3EqPh3Method;
-/** Offset 0x0314 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+/** Offset 0x0315 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 DmiGen3ProgramStaticEq;
-/** Offset 0x0315 - DeEmphasis control for DMI
+/** Offset 0x0316 - DeEmphasis control for DMI
DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
0: -6dB, 1: -3.5dB
**/
UINT8 DmiDeEmphasis;
-/** Offset 0x0316 - DMI Gen3 Root port preset values per lane
+/** Offset 0x0317 - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
**/
UINT8 DmiGen3RootPortPreset[8];
-/** Offset 0x031E - DMI Gen3 End port preset values per lane
+/** Offset 0x031F - DMI Gen3 End port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
**/
UINT8 DmiGen3EndPointPreset[8];
-/** Offset 0x0326 - DMI Gen3 End port Hint values per lane
+/** Offset 0x0327 - DMI Gen3 End port Hint values per lane
Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
**/
UINT8 DmiGen3EndPointHint[8];
-/** Offset 0x032E - DMI Gen3 RxCTLEp per-Bundle control
+/** Offset 0x032F - DMI Gen3 RxCTLEp per-Bundle control
Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
**/
UINT8 DmiGen3RxCtlePeaking[4];
-/** Offset 0x0332 - DMI ASPM Configuration:{Combo
+/** Offset 0x0333 - DMI ASPM Configuration:{Combo
Set ASPM Configuration
0:Disabled, 1:L0s, 2:L1, 3:L1L0s
**/
UINT8 DmiAspm;
-/** Offset 0x0333 - Enable/Disable DMI GEN3 Hardware Eq
+/** Offset 0x0334 - Enable/Disable DMI GEN3 Hardware Eq
Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0)(Default): Disable Hardware Eq,
Enabled(0x1): Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 DmiHweq;
-/** Offset 0x0334 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass
+/** Offset 0x0335 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass
CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1):
Enable Phase 23 Bypass
$EN_DIS
**/
UINT8 Gen3EqPhase23Bypass;
-/** Offset 0x0335 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass
+/** Offset 0x0336 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass
CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1):
Enable Phase 3 Bypass
$EN_DIS
**/
UINT8 Gen3EqPhase3Bypass;
-/** Offset 0x0336 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable
+/** Offset 0x0337 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable
Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default):
Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter
Coefficient Override
@@ -1155,7 +1153,7 @@ typedef struct {
**/
UINT8 Gen3LtcoEnable;
-/** Offset 0x0337 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
+/** Offset 0x0338 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote
Transmitter Coefficient/Preset Override
@@ -1163,94 +1161,94 @@ typedef struct {
**/
UINT8 Gen3RtcoRtpoEnable;
-/** Offset 0x0338 - DMI Gen3 Transmitter Pre-Cursor Coefficient
+/** Offset 0x0339 - DMI Gen3 Transmitter Pre-Cursor Coefficient
Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10,
2 is default for each lane
**/
UINT8 DmiGen3Ltcpre[8];
-/** Offset 0x0340 - DMI Gen3 Transmitter Post-Cursor Coefficient
+/** Offset 0x0341 - DMI Gen3 Transmitter Post-Cursor Coefficient
Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default
for each lane
**/
UINT8 DmiGen3Ltcpo[8];
-/** Offset 0x0348 - PCIE Hw Eq Gen3 CoeffList Cm
+/** Offset 0x0349 - PCIE Hw Eq Gen3 CoeffList Cm
CPU_PCIE_EQ_PARAM. Coefficient C-1.
**/
UINT8 CpuDmiHwEqGen3CoeffListCm[8];
-/** Offset 0x0350 - PCIE Hw Eq Gen3 CoeffList Cp
+/** Offset 0x0351 - PCIE Hw Eq Gen3 CoeffList Cp
CPU_PCIE_EQ_PARAM. Coefficient C+1.
**/
UINT8 CpuDmiHwEqGen3CoeffListCp[8];
-/** Offset 0x0358 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
+/** Offset 0x0359 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable,
Manual(0x1): Enable DmiGen3DsPresetEnable
$EN_DIS
**/
UINT8 DmiGen3DsPresetEnable;
-/** Offset 0x0359 - DMI Gen3 Root port preset Rx values per lane
+/** Offset 0x035A - DMI Gen3 Root port preset Rx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
for each lane
**/
UINT8 DmiGen3DsPortRxPreset[8];
-/** Offset 0x0361 - DMI Gen3 Root port preset Tx values per lane
+/** Offset 0x0362 - DMI Gen3 Root port preset Tx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
for each lane
**/
UINT8 DmiGen3DsPortTxPreset[8];
-/** Offset 0x0369 - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable
+/** Offset 0x036A - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable
Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable,
Manual(0x1): Enable DmiGen3UsPresetEnable
$EN_DIS
**/
UINT8 DmiGen3UsPresetEnable;
-/** Offset 0x036A - DMI Gen3 Root port preset Rx values per lane
+/** Offset 0x036B - DMI Gen3 Root port preset Rx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
for each lane
**/
UINT8 DmiGen3UsPortRxPreset[8];
-/** Offset 0x0372 - DMI Gen3 Root port preset Tx values per lane
+/** Offset 0x0373 - DMI Gen3 Root port preset Tx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
for each lane
**/
UINT8 DmiGen3UsPortTxPreset[8];
-/** Offset 0x037A - Reserved
+/** Offset 0x037B - Reserved
**/
UINT8 Reserved12[54];
-/** Offset 0x03B0 - DMI ASPM Control Configuration:{Combo
+/** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo
Set ASPM Control configuration
0:Disabled, 1:L0s, 2:L1, 3:L1L0s
**/
UINT8 DmiAspmCtrl;
-/** Offset 0x03B1 - DMI ASPM L1 exit Latency
+/** Offset 0x03B2 - DMI ASPM L1 exit Latency
Range: 0-7, 4 is default L1 exit Latency
**/
UINT8 DmiAspmL1ExitLatency;
-/** Offset 0x03B2 - BIST on Reset
+/** Offset 0x03B3 - BIST on Reset
Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 BistOnReset;
-/** Offset 0x03B3 - Skip Stop PBET Timer Enable/Disable
+/** Offset 0x03B4 - Skip Stop PBET Timer Enable/Disable
Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 SkipStopPbet;
-/** Offset 0x03B4 - C6DRAM power gating feature
+/** Offset 0x03B5 - C6DRAM power gating feature
This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
@@ -1258,61 +1256,61 @@ typedef struct {
**/
UINT8 EnableC6Dram;
-/** Offset 0x03B5 - Over clocking support
+/** Offset 0x03B6 - Over clocking support
Over clocking support; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 OcSupport;
-/** Offset 0x03B6 - Over clocking Lock
+/** Offset 0x03B7 - Over clocking Lock
Over clocking Lock Enable/Disable; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 OcLock;
-/** Offset 0x03B7 - Maximum Core Turbo Ratio Override
+/** Offset 0x03B8 - Maximum Core Turbo Ratio Override
Maximum core turbo ratio override allows to increase CPU core frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
**/
UINT8 CoreMaxOcRatio;
-/** Offset 0x03B8 - Core voltage mode
+/** Offset 0x03B9 - Core voltage mode
Core voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 CoreVoltageMode;
-/** Offset 0x03B9 - Maximum clr turbo ratio override
+/** Offset 0x03BA - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
**/
UINT8 RingMaxOcRatio;
-/** Offset 0x03BA - Hyper Threading Enable/Disable
+/** Offset 0x03BB - Hyper Threading Enable/Disable
Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 HyperThreading;
-/** Offset 0x03BB - Enable or Disable CPU Ratio Override
+/** Offset 0x03BC - Enable or Disable CPU Ratio Override
Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CpuRatioOverride;
-/** Offset 0x03BC - CPU ratio value
+/** Offset 0x03BD - CPU ratio value
CPU ratio value. Valid Range 0 to 63
**/
UINT8 CpuRatio;
-/** Offset 0x03BD - Boot frequency
+/** Offset 0x03BE - Boot frequency
Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.
1: Maximum non-turbo performance. <b>2: Turbo performance </b>
0:0, 1:1, 2:2
**/
UINT8 BootFrequency;
-/** Offset 0x03BE - Number of active big cores
+/** Offset 0x03BF - Number of active big cores
Number of active big cores(Depends on Number of big cores). Default 0xFF means to
active all system supported big cores. <b>0xFF: Active all big cores</b>; 0: Disable
all big cores; 1: 1; 2: 2; 3: 3;
@@ -1320,49 +1318,45 @@ typedef struct {
**/
UINT8 ActiveCoreCount;
-/** Offset 0x03BF - Processor Early Power On Configuration FCLK setting
+/** Offset 0x03C0 - Processor Early Power On Configuration FCLK setting
<b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
2: 400 MHz. - 3: Reserved
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
**/
UINT8 FClkFrequency;
-/** Offset 0x03C0 - Set JTAG power in C10 and deeper power states
+/** Offset 0x03C1 - Set JTAG power in C10 and deeper power states
False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
and deeper power states for debug purpose. <b>0: False</b>; 1: True.
0: False, 1: True
**/
UINT8 JtagC10PowerGateDisable;
-/** Offset 0x03C1 - Enable or Disable VMX
+/** Offset 0x03C2 - Enable or Disable VMX
Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 VmxEnable;
-/** Offset 0x03C2 - AVX2 Ratio Offset
+/** Offset 0x03C3 - AVX2 Ratio Offset
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx2RatioOffset;
-/** Offset 0x03C3 - AVX3 Ratio Offset
+/** Offset 0x03C4 - AVX3 Ratio Offset
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx3RatioOffset;
-/** Offset 0x03C4 - BCLK Adaptive Voltage Enable
+/** Offset 0x03C5 - BCLK Adaptive Voltage Enable
When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
Disable;<b> 1: Enable
$EN_DIS
**/
UINT8 BclkAdaptiveVoltage;
-/** Offset 0x03C5 - Reserved
-**/
- UINT8 Reserved13;
-
/** Offset 0x03C6 - core voltage override
The core voltage override which is applied to the entire range of cpu core frequencies.
Valid Range 0 to 2000
@@ -1387,7 +1381,7 @@ typedef struct {
/** Offset 0x03CD - Reserved
**/
- UINT8 Reserved14;
+ UINT8 Reserved13;
/** Offset 0x03CE - Ring Downbin
Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
@@ -1410,7 +1404,7 @@ typedef struct {
/** Offset 0x03D1 - Reserved
**/
- UINT8 Reserved15;
+ UINT8 Reserved14;
/** Offset 0x03D2 - Ring voltage override
The ring voltage override which is applied to the entire range of cpu ring frequencies.
@@ -1454,1251 +1448,1371 @@ typedef struct {
**/
UINT8 DebugInterfaceLockEnable;
-/** Offset 0x03DC - BiosGuard
+/** Offset 0x03DC - Reserved
+**/
+ UINT8 Reserved15[24];
+
+/** Offset 0x03F4 - Core VF Point Offset Mode
+ Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
+ In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
+ setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
+ 0:Legacy, 1:Selection
+**/
+ UINT8 CoreVfPointOffsetMode;
+
+/** Offset 0x03F5 - Reserved
+**/
+ UINT8 Reserved16;
+
+/** Offset 0x03F6 - Core VF Point Offset
+ Array used to specifies the Core Voltage Offset applied to the each selected VF
+ Point. This voltage is specified in millivolts.
+**/
+ UINT16 CoreVfPointOffset[15];
+
+/** Offset 0x0414 - Core VF Point Offset Prefix
+ Sets the CoreVfPointOffset value as positive or negative for corresponding core
+ VF Point; <b>0: Positive </b>; 1: Negative.
+ 0:Positive, 1:Negative
+**/
+ UINT8 CoreVfPointOffsetPrefix[15];
+
+/** Offset 0x0423 - Core VF Point Ratio
+ Array for the each selected Core VF Point to display the ration.
+**/
+ UINT8 CoreVfPointRatio[15];
+
+/** Offset 0x0432 - Core VF Point Count
+ Number of supported Core Voltage & Frequency Point Offset
+**/
+ UINT8 CoreVfPointCount;
+
+/** Offset 0x0433 - Reserved
+**/
+ UINT8 Reserved17[25];
+
+/** Offset 0x044C - Per Core Max Ratio override
+ Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
+ favored core ratio to each Core. <b>0: Disable</b>, 1: enable
+ $EN_DIS
+**/
+ UINT8 PerCoreRatioOverride;
+
+/** Offset 0x044D - Per Core Current Max Ratio
+ Array for the Per Core Max Ratio
+**/
+ UINT8 PerCoreRatio[8];
+
+/** Offset 0x0455 - Reserved
+**/
+ UINT8 Reserved18[5];
+
+/** Offset 0x045A - Pvd Ratio Threshold
+ Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default.
+**/
+ UINT8 PvdRatioThreshold;
+
+/** Offset 0x045B - Support Unlimited ICCMAX
+ Support Unlimited ICCMAX more than maximum value 255.75A; <b>0: Disabled</b>; 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 UnlimitedIccMax;
+
+/** Offset 0x045C - Enable CPU CrashLog GPRs dump
+ Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
+ disable Smm GPRs dump
+ 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
+**/
+ UINT8 CrashLogGprs;
+
+/** Offset 0x045D - Reserved
+**/
+ UINT8 Reserved19[62];
+
+/** Offset 0x049B - BCLK Frequency Source
+ Clock source of BCLK OC frequency, <b>1:CPU BCLK</b>, 2:PCH BCLK, 3:External CLK
+ 1:CPU BCLK, 2:PCH BCLK, 3:External CLK
+**/
+ UINT8 BclkSource;
+
+/** Offset 0x049C - GPIO Override
+ Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
+ before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
+ configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
+**/
+ UINT8 GpioOverride;
+
+/** Offset 0x049D - Reserved
+**/
+ UINT8 Reserved20[3];
+
+/** Offset 0x04A0 - CPU BCLK OC Frequency
+ CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0
+ - Auto</b>. Range is 8000-50000 (10KHz).
+**/
+ UINT32 CpuBclkOcFrequency;
+
+/** Offset 0x04A4 - Reserved
+**/
+ UINT8 Reserved21[40];
+
+/** Offset 0x04CC - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
**/
UINT8 BiosGuard;
-/** Offset 0x03DD
+/** Offset 0x04CD
**/
UINT8 BiosGuardToolsInterface;
-/** Offset 0x03DE - Txt
+/** Offset 0x04CE - Txt
Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
$EN_DIS
**/
UINT8 Txt;
-/** Offset 0x03DF - Reserved
+/** Offset 0x04CF - Reserved
**/
- UINT8 Reserved16;
+ UINT8 Reserved22;
-/** Offset 0x03E0 - PrmrrSize
+/** Offset 0x04D0 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
**/
UINT32 PrmrrSize;
-/** Offset 0x03E4 - SinitMemorySize
+/** Offset 0x04D4 - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
-/** Offset 0x03E8 - TxtDprMemoryBase
+/** Offset 0x04D8 - TxtDprMemoryBase
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
**/
UINT64 TxtDprMemoryBase;
-/** Offset 0x03F0 - TxtHeapMemorySize
+/** Offset 0x04E0 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
**/
UINT32 TxtHeapMemorySize;
-/** Offset 0x03F4 - TxtDprMemorySize
+/** Offset 0x04E4 - TxtDprMemorySize
Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
**/
UINT32 TxtDprMemorySize;
-/** Offset 0x03F8 - BiosAcmBase
+/** Offset 0x04E8 - BiosAcmBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT32 BiosAcmBase;
-/** Offset 0x03FC - BiosAcmSize
+/** Offset 0x04EC - BiosAcmSize
Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
**/
UINT32 BiosAcmSize;
-/** Offset 0x0400 - ApStartupBase
+/** Offset 0x04F0 - ApStartupBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT32 ApStartupBase;
-/** Offset 0x0404 - TgaSize
+/** Offset 0x04F4 - TgaSize
Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
**/
UINT32 TgaSize;
-/** Offset 0x0408 - TxtLcpPdBase
+/** Offset 0x04F8 - TxtLcpPdBase
Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
**/
UINT64 TxtLcpPdBase;
-/** Offset 0x0410 - TxtLcpPdSize
+/** Offset 0x0500 - TxtLcpPdSize
Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
**/
UINT64 TxtLcpPdSize;
-/** Offset 0x0418 - IsTPMPresence
+/** Offset 0x0508 - IsTPMPresence
IsTPMPresence default values
**/
UINT8 IsTPMPresence;
-/** Offset 0x0419 - Reserved
+/** Offset 0x0509 - Reserved
**/
- UINT8 Reserved17[53];
+ UINT8 Reserved23[32];
-/** Offset 0x044E - Enable PCH HSIO PCIE Rx Set Ctle
+/** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value.
**/
UINT8 PchPcieHsioRxSetCtleEnable[28];
-/** Offset 0x046A - PCH HSIO PCIE Rx Set Ctle Value
+/** Offset 0x0545 - PCH HSIO PCIE Rx Set Ctle Value
PCH PCIe Gen 3 Set CTLE Value.
**/
UINT8 PchPcieHsioRxSetCtle[28];
-/** Offset 0x0486 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+/** Offset 0x0561 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28];
-/** Offset 0x04A2 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x057D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen1DownscaleAmp[28];
-/** Offset 0x04BE - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+/** Offset 0x0599 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28];
-/** Offset 0x04DA - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x05B5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen2DownscaleAmp[28];
-/** Offset 0x04F6 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+/** Offset 0x05D1 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28];
-/** Offset 0x0512 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x05ED - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen3DownscaleAmp[28];
-/** Offset 0x052E - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0609 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen1DeEmphEnable[28];
-/** Offset 0x054A - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+/** Offset 0x0625 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen1DeEmph[28];
-/** Offset 0x0566 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+/** Offset 0x0641 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28];
-/** Offset 0x0582 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+/** Offset 0x065D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen2DeEmph3p5[28];
-/** Offset 0x059E - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+/** Offset 0x0679 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28];
-/** Offset 0x05BA - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+/** Offset 0x0695 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen2DeEmph6p0[28];
-/** Offset 0x05D6 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x06B1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
-/** Offset 0x05DE - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x06B9 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen1EqBoostMag[8];
-/** Offset 0x05E6 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x06C1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
-/** Offset 0x05EE - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x06C9 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen2EqBoostMag[8];
-/** Offset 0x05F6 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x06D1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
-/** Offset 0x05FE - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x06D9 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen3EqBoostMag[8];
-/** Offset 0x0606 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x06E1 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
-/** Offset 0x060E - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x06E9 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen1DownscaleAmp[8];
-/** Offset 0x0616 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x06F1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
-/** Offset 0x061E - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x06F9 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen2DownscaleAmp[8];
-/** Offset 0x0626 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x0701 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
-/** Offset 0x062E - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0709 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen3DownscaleAmp[8];
-/** Offset 0x0636 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0711 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen1DeEmphEnable[8];
-/** Offset 0x063E - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0719 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen1DeEmph[8];
-/** Offset 0x0646 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0721 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen2DeEmphEnable[8];
-/** Offset 0x064E - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0729 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen2DeEmph[8];
-/** Offset 0x0656 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0731 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen3DeEmphEnable[8];
-/** Offset 0x065E - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0739 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen3DeEmph[8];
-/** Offset 0x0666 - PCH LPC Enhanced Port 80 Decoding
+/** Offset 0x0741 - PCH LPC Enhanced Port 80 Decoding
Original LPC only decodes one byte of port 80h.
$EN_DIS
**/
UINT8 PchLpcEnhancePort8xhDecoding;
-/** Offset 0x0667 - PCH Port80 Route
+/** Offset 0x0742 - PCH Port80 Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
0:LPC, 1:PCI
**/
UINT8 PchPort80Route;
-/** Offset 0x0668 - Enable SMBus ARP support
+/** Offset 0x0743 - Enable SMBus ARP support
Enable SMBus ARP support.
$EN_DIS
**/
UINT8 SmbusArpEnable;
-/** Offset 0x0669 - Number of RsvdSmbusAddressTable.
+/** Offset 0x0744 - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
**/
UINT8 PchNumRsvdSmbusAddresses;
-/** Offset 0x066A - SMBUS Base Address
+/** Offset 0x0745 - Reserved
+**/
+ UINT8 Reserved24;
+
+/** Offset 0x0746 - SMBUS Base Address
SMBUS Base Address (IO space).
**/
UINT16 PchSmbusIoBase;
-/** Offset 0x066C - Enable SMBus Alert Pin
+/** Offset 0x0748 - Enable SMBus Alert Pin
Enable SMBus Alert Pin.
$EN_DIS
**/
UINT8 PchSmbAlertEnable;
-/** Offset 0x066D - Usage type for ClkSrc
+/** Offset 0x0749 - Usage type for ClkSrc
0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
(free running), 0xFF: not used
**/
UINT8 PcieClkSrcUsage[18];
-/** Offset 0x067F - Reserved
+/** Offset 0x075B - Reserved
**/
- UINT8 Reserved18[14];
+ UINT8 Reserved25[14];
-/** Offset 0x068D - ClkReq-to-ClkSrc mapping
+/** Offset 0x0769 - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 PcieClkSrcClkReq[18];
-/** Offset 0x069F - Reserved
+/** Offset 0x077B - Reserved
**/
- UINT8 Reserved19[93];
+ UINT8 Reserved26[93];
-/** Offset 0x06FC - Enable PCIE RP Mask
+/** Offset 0x07D8 - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
for port1, bit1 for port2, and so on.
**/
UINT32 PcieRpEnableMask;
-/** Offset 0x0700 - VC Type
+/** Offset 0x07DC - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1.
0: VC0, 1: VC1
**/
UINT8 PchHdaVcType;
-/** Offset 0x0701 - Universal Audio Architecture compliance for DSP enabled system
+/** Offset 0x07DD - Universal Audio Architecture compliance for DSP enabled system
0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
driver or SST driver supported).
$EN_DIS
**/
UINT8 PchHdaDspUaaCompliance;
-/** Offset 0x0702 - Enable HD Audio Link
+/** Offset 0x07DE - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkHdaEnable;
-/** Offset 0x0703 - Enable HDA SDI lanes
+/** Offset 0x07DF - Enable HDA SDI lanes
Enable/disable HDA SDI lanes.
**/
UINT8 PchHdaSdiEnable[2];
-/** Offset 0x0705 - HDA Power/Clock Gating (PGD/CGD)
+/** Offset 0x07E1 - HDA Power/Clock Gating (PGD/CGD)
Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
FORCE_ENABLE, 2: FORCE_DISABLE.
0: POR, 1: Force Enable, 2: Force Disable
**/
UINT8 PchHdaTestPowerClockGating;
-/** Offset 0x0706 - Enable HD Audio DMIC_N Link
+/** Offset 0x07E2 - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
**/
UINT8 PchHdaAudioLinkDmicEnable[2];
-/** Offset 0x0708 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+/** Offset 0x07E4 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
**/
UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-/** Offset 0x0710 - DMIC<N> ClkB Pin Muxing
+/** Offset 0x07EC - DMIC<N> ClkB Pin Muxing
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
**/
UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-/** Offset 0x0718 - Enable HD Audio DSP
+/** Offset 0x07F4 - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
-/** Offset 0x0719 - Reserved
+/** Offset 0x07F5 - Reserved
**/
- UINT8 Reserved20[3];
+ UINT8 Reserved27[3];
-/** Offset 0x071C - DMIC<N> Data Pin Muxing
+/** Offset 0x07F8 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
**/
UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-/** Offset 0x0724 - Enable HD Audio SSP0 Link
+/** Offset 0x0800 - Enable HD Audio SSP0 Link
Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
**/
UINT8 PchHdaAudioLinkSspEnable[6];
-/** Offset 0x072A - Enable HD Audio SoundWire#N Link
+/** Offset 0x0806 - Enable HD Audio SoundWire#N Link
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
**/
UINT8 PchHdaAudioLinkSndwEnable[4];
-/** Offset 0x072E - iDisp-Link Frequency
+/** Offset 0x080A - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
4: 96MHz, 3: 48MHz
**/
UINT8 PchHdaIDispLinkFrequency;
-/** Offset 0x072F - iDisp-Link T-mode
+/** Offset 0x080B - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
0: 2T, 2: 4T, 3: 8T, 4: 16T
**/
UINT8 PchHdaIDispLinkTmode;
-/** Offset 0x0730 - iDisplay Audio Codec disconnection
+/** Offset 0x080C - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS
**/
UINT8 PchHdaIDispCodecDisconnect;
-/** Offset 0x0731 - Debug Interfaces
+/** Offset 0x080D - Reserved
+**/
+ UINT8 Reserved28;
+
+/** Offset 0x080E - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.
**/
UINT8 PcdDebugInterfaceFlags;
-/** Offset 0x0732 - Serial Io Uart Debug Controller Number
+/** Offset 0x080F - Serial Io Uart Debug Controller Number
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
Core interface, it cannot be used for debug purpose.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 SerialIoUartDebugControllerNumber;
-/** Offset 0x0733 - Serial Io Uart Debug Auto Flow
+/** Offset 0x0810 - Serial Io Uart Debug Auto Flow
Enables UART hardware flow control, CTS and RTS lines.
$EN_DIS
**/
UINT8 SerialIoUartDebugAutoFlow;
-/** Offset 0x0734 - Serial Io Uart Debug BaudRate
+/** Offset 0x0811 - Reserved
+**/
+ UINT8 Reserved29[3];
+
+/** Offset 0x0814 - Serial Io Uart Debug BaudRate
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
**/
UINT32 SerialIoUartDebugBaudRate;
-/** Offset 0x0738 - Serial Io Uart Debug Parity
+/** Offset 0x0818 - Serial Io Uart Debug Parity
Set default Parity.
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
UINT8 SerialIoUartDebugParity;
-/** Offset 0x0739 - Serial Io Uart Debug Stop Bits
+/** Offset 0x0819 - Serial Io Uart Debug Stop Bits
Set default stop bits.
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
**/
UINT8 SerialIoUartDebugStopBits;
-/** Offset 0x073A - Serial Io Uart Debug Data Bits
+/** Offset 0x081A - Serial Io Uart Debug Data Bits
Set default word length. 0: Default, 5,6,7,8
5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
**/
UINT8 SerialIoUartDebugDataBits;
-/** Offset 0x073B - Reserved
+/** Offset 0x081B - Reserved
**/
- UINT8 Reserved21;
+ UINT8 Reserved30;
-/** Offset 0x073C - Serial Io Uart Debug Mmio Base
+/** Offset 0x081C - Serial Io Uart Debug Mmio Base
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
= SerialIoUartPci.
**/
UINT32 SerialIoUartDebugMmioBase;
-/** Offset 0x0740 - ISA Serial Base selection
+/** Offset 0x0820 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
0:0x3F8, 1:0x2F8
**/
UINT8 PcdIsaSerialUartBase;
-/** Offset 0x0741 - GT PLL voltage offset
+/** Offset 0x0821 - GT PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 GtPllVoltageOffset;
-/** Offset 0x0742 - Ring PLL voltage offset
+/** Offset 0x0822 - Ring PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 RingPllVoltageOffset;
-/** Offset 0x0743 - System Agent PLL voltage offset
+/** Offset 0x0823 - System Agent PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 SaPllVoltageOffset;
-/** Offset 0x0744 - Memory Controller PLL voltage offset
+/** Offset 0x0824 - Memory Controller PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 McPllVoltageOffset;
-/** Offset 0x0745 - MRC Safe Config
+/** Offset 0x0825 - MRC Safe Config
Enables/Disable MRC Safe Config
$EN_DIS
**/
UINT8 MrcSafeConfig;
-/** Offset 0x0746 - TCSS Thunderbolt PCIE Root Port 0 Enable
+/** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable
Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie0En;
-/** Offset 0x0747 - TCSS Thunderbolt PCIE Root Port 1 Enable
+/** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable
Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie1En;
-/** Offset 0x0748 - TCSS Thunderbolt PCIE Root Port 2 Enable
+/** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable
Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie2En;
-/** Offset 0x0749 - TCSS Thunderbolt PCIE Root Port 3 Enable
+/** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable
Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie3En;
-/** Offset 0x074A - TCSS USB HOST (xHCI) Enable
+/** Offset 0x082A - TCSS USB HOST (xHCI) Enable
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
$EN_DIS
**/
UINT8 TcssXhciEn;
-/** Offset 0x074B - TCSS USB DEVICE (xDCI) Enable
+/** Offset 0x082B - TCSS USB DEVICE (xDCI) Enable
Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
$EN_DIS
**/
UINT8 TcssXdciEn;
-/** Offset 0x074C - TCSS DMA0 Enable
+/** Offset 0x082C - TCSS DMA0 Enable
Set TCSS DMA0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma0En;
-/** Offset 0x074D - TCSS DMA1 Enable
+/** Offset 0x082D - TCSS DMA1 Enable
Set TCSS DMA1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma1En;
-/** Offset 0x074E - PcdSerialDebugBaudRate
+/** Offset 0x082E - PcdSerialDebugBaudRate
Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
3:9600, 4:19200, 6:56700, 7:115200
**/
UINT8 PcdSerialDebugBaudRate;
-/** Offset 0x074F - HobBufferSize
+/** Offset 0x082F - HobBufferSize
Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
total HOB size).
0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
**/
UINT8 HobBufferSize;
-/** Offset 0x0750 - Early Command Training
+/** Offset 0x0830 - Early Command Training
Enables/Disable Early Command Training
$EN_DIS
**/
UINT8 ECT;
-/** Offset 0x0751 - SenseAmp Offset Training
+/** Offset 0x0831 - SenseAmp Offset Training
Enables/Disable SenseAmp Offset Training
$EN_DIS
**/
UINT8 SOT;
-/** Offset 0x0752 - Early ReadMPR Timing Centering 2D
+/** Offset 0x0832 - Early ReadMPR Timing Centering 2D
Enables/Disable Early ReadMPR Timing Centering 2D
$EN_DIS
**/
UINT8 ERDMPRTC2D;
-/** Offset 0x0753 - Read MPR Training
+/** Offset 0x0833 - Read MPR Training
Enables/Disable Read MPR Training
$EN_DIS
**/
UINT8 RDMPRT;
-/** Offset 0x0754 - Receive Enable Training
+/** Offset 0x0834 - Receive Enable Training
Enables/Disable Receive Enable Training
$EN_DIS
**/
UINT8 RCVET;
-/** Offset 0x0755 - Jedec Write Leveling
+/** Offset 0x0835 - Jedec Write Leveling
Enables/Disable Jedec Write Leveling
$EN_DIS
**/
UINT8 JWRL;
-/** Offset 0x0756 - Early Write Time Centering 2D
+/** Offset 0x0836 - Early Write Time Centering 2D
Enables/Disable Early Write Time Centering 2D
$EN_DIS
**/
UINT8 EWRTC2D;
-/** Offset 0x0757 - Early Read Time Centering 2D
+/** Offset 0x0837 - Early Read Time Centering 2D
Enables/Disable Early Read Time Centering 2D
$EN_DIS
**/
UINT8 ERDTC2D;
-/** Offset 0x0758 - Write Timing Centering 1D
+/** Offset 0x0838 - Write Timing Centering 1D
Enables/Disable Write Timing Centering 1D
$EN_DIS
**/
UINT8 WRTC1D;
-/** Offset 0x0759 - Write Voltage Centering 1D
+/** Offset 0x0839 - Write Voltage Centering 1D
Enables/Disable Write Voltage Centering 1D
$EN_DIS
**/
UINT8 WRVC1D;
-/** Offset 0x075A - Read Timing Centering 1D
+/** Offset 0x083A - Read Timing Centering 1D
Enables/Disable Read Timing Centering 1D
$EN_DIS
**/
UINT8 RDTC1D;
-/** Offset 0x075B - Dimm ODT Training
+/** Offset 0x083B - Dimm ODT Training
Enables/Disable Dimm ODT Training
$EN_DIS
**/
UINT8 DIMMODTT;
-/** Offset 0x075C - DIMM RON Training
+/** Offset 0x083C - DIMM RON Training
Enables/Disable DIMM RON Training
$EN_DIS
**/
UINT8 DIMMRONT;
-/** Offset 0x075D - Write Drive Strength/Equalization 2D
+/** Offset 0x083D - Write Drive Strength/Equalization 2D
Enables/Disable Write Drive Strength/Equalization 2D
$EN_DIS
**/
UINT8 WRDSEQT;
-/** Offset 0x075E - Write Slew Rate Training
+/** Offset 0x083E - Write Slew Rate Training
Enables/Disable Write Slew Rate Training
$EN_DIS
**/
UINT8 WRSRT;
-/** Offset 0x075F - Read ODT Training
+/** Offset 0x083F - Read ODT Training
Enables/Disable Read ODT Training
$EN_DIS
**/
UINT8 RDODTT;
-/** Offset 0x0760 - Read Equalization Training
+/** Offset 0x0840 - Read Equalization Training
Enables/Disable Read Equalization Training
$EN_DIS
**/
UINT8 RDEQT;
-/** Offset 0x0761 - Read Amplifier Training
+/** Offset 0x0841 - Read Amplifier Training
Enables/Disable Read Amplifier Training
$EN_DIS
**/
UINT8 RDAPT;
-/** Offset 0x0762 - Write Timing Centering 2D
+/** Offset 0x0842 - Write Timing Centering 2D
Enables/Disable Write Timing Centering 2D
$EN_DIS
**/
UINT8 WRTC2D;
-/** Offset 0x0763 - Read Timing Centering 2D
+/** Offset 0x0843 - Read Timing Centering 2D
Enables/Disable Read Timing Centering 2D
$EN_DIS
**/
UINT8 RDTC2D;
-/** Offset 0x0764 - Write Voltage Centering 2D
+/** Offset 0x0844 - Write Voltage Centering 2D
Enables/Disable Write Voltage Centering 2D
$EN_DIS
**/
UINT8 WRVC2D;
-/** Offset 0x0765 - Read Voltage Centering 2D
+/** Offset 0x0845 - Read Voltage Centering 2D
Enables/Disable Read Voltage Centering 2D
$EN_DIS
**/
UINT8 RDVC2D;
-/** Offset 0x0766 - Command Voltage Centering
+/** Offset 0x0846 - Command Voltage Centering
Enables/Disable Command Voltage Centering
$EN_DIS
**/
UINT8 CMDVC;
-/** Offset 0x0767 - Late Command Training
+/** Offset 0x0847 - Late Command Training
Enables/Disable Late Command Training
$EN_DIS
**/
UINT8 LCT;
-/** Offset 0x0768 - Round Trip Latency Training
+/** Offset 0x0848 - Round Trip Latency Training
Enables/Disable Round Trip Latency Training
$EN_DIS
**/
UINT8 RTL;
-/** Offset 0x0769 - Turn Around Timing Training
+/** Offset 0x0849 - Turn Around Timing Training
Enables/Disable Turn Around Timing Training
$EN_DIS
**/
UINT8 TAT;
-/** Offset 0x076A - Memory Test
+/** Offset 0x084A - Memory Test
Enables/Disable Memory Test
$EN_DIS
**/
UINT8 MEMTST;
-/** Offset 0x076B - DIMM SPD Alias Test
+/** Offset 0x084B - DIMM SPD Alias Test
Enables/Disable DIMM SPD Alias Test
$EN_DIS
**/
UINT8 ALIASCHK;
-/** Offset 0x076C - Receive Enable Centering 1D
+/** Offset 0x084C - Receive Enable Centering 1D
Enables/Disable Receive Enable Centering 1D
$EN_DIS
**/
UINT8 RCVENC1D;
-/** Offset 0x076D - Retrain Margin Check
+/** Offset 0x084D - Retrain Margin Check
Enables/Disable Retrain Margin Check
$EN_DIS
**/
UINT8 RMC;
-/** Offset 0x076E - Write Drive Strength Up/Dn independently
+/** Offset 0x084E - Write Drive Strength Up/Dn independently
Enables/Disable Write Drive Strength Up/Dn independently
$EN_DIS
**/
UINT8 WRDSUDT;
-/** Offset 0x076F - ECC Support
+/** Offset 0x084F - ECC Support
Enables/Disable ECC Support
$EN_DIS
**/
UINT8 EccSupport;
-/** Offset 0x0770 - Memory Remap
+/** Offset 0x0850 - Memory Remap
Enables/Disable Memory Remap
$EN_DIS
**/
UINT8 RemapEnable;
-/** Offset 0x0771 - Rank Interleave support
+/** Offset 0x0851 - Rank Interleave support
Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
the same time.
$EN_DIS
**/
UINT8 RankInterleave;
-/** Offset 0x0772 - Enhanced Interleave support
+/** Offset 0x0852 - Enhanced Interleave support
Enables/Disable Enhanced Interleave support
$EN_DIS
**/
UINT8 EnhancedInterleave;
-/** Offset 0x0773 - Ch Hash Support
+/** Offset 0x0853 - Ch Hash Support
Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
$EN_DIS
**/
UINT8 ChHashEnable;
-/** Offset 0x0774 - Reserved
+/** Offset 0x0854 - Reserved
**/
- UINT8 Reserved22;
+ UINT8 Reserved31;
-/** Offset 0x0775 - Extern Therm Status
+/** Offset 0x0855 - Extern Therm Status
Enables/Disable Extern Therm Status
$EN_DIS
**/
UINT8 EnableExtts;
-/** Offset 0x0776 - DDR PowerDown and idle counter
+/** Offset 0x0856 - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS
**/
UINT8 EnablePwrDn;
-/** Offset 0x0777 - DDR PowerDown and idle counter
+/** Offset 0x0857 - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS
**/
UINT8 EnablePwrDnLpddr;
-/** Offset 0x0778 - SelfRefresh Enable
+/** Offset 0x0858 - SelfRefresh Enable
Enables/Disable SelfRefresh Enable
$EN_DIS
**/
UINT8 SrefCfgEna;
-/** Offset 0x0779 - Throttler CKEMin Defeature
+/** Offset 0x0859 - Throttler CKEMin Defeature
Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
$EN_DIS
**/
UINT8 ThrtCkeMinDefeatLpddr;
-/** Offset 0x077A - Throttler CKEMin Defeature
+/** Offset 0x085A - Throttler CKEMin Defeature
Enables/Disable Throttler CKEMin Defeature
$EN_DIS
**/
UINT8 ThrtCkeMinDefeat;
-/** Offset 0x077B - Reserved
+/** Offset 0x085B - Reserved
**/
- UINT8 Reserved23;
+ UINT8 Reserved32;
-/** Offset 0x077C - Exit On Failure (MRC)
+/** Offset 0x085C - Exit On Failure (MRC)
Enables/Disable Exit On Failure (MRC)
$EN_DIS
**/
UINT8 ExitOnFailure;
-/** Offset 0x077D - New Features 1 - MRC
+/** Offset 0x085D - New Features 1 - MRC
New Feature Enabling 1, <b>0:Disable</b>, 1:Enable
0:Disable, 1:Enable
**/
UINT8 NewFeatureEnable1;
-/** Offset 0x077E - New Features 2 - MRC
+/** Offset 0x085E - New Features 2 - MRC
New Feature Enabling 2, <b>0:Disable</b>, 1:Enable
0:Disable, 1:Enable
**/
UINT8 NewFeatureEnable2;
-/** Offset 0x077F - Duty Cycle Correction Training
+/** Offset 0x085F - Duty Cycle Correction Training
Enable/Disable Duty Cycle Correction Training
$EN_DIS
**/
UINT8 DCC;
-/** Offset 0x0780 - Read Voltage Centering 1D
+/** Offset 0x0860 - Read Voltage Centering 1D
Enable/Disable Read Voltage Centering 1D
$EN_DIS
**/
UINT8 RDVC1D;
-/** Offset 0x0781 - TxDqTCO Comp Training
+/** Offset 0x0861 - TxDqTCO Comp Training
Enable/Disable TxDqTCO Comp Training
$EN_DIS
**/
UINT8 TXTCO;
-/** Offset 0x0782 - ClkTCO Comp Training
+/** Offset 0x0862 - ClkTCO Comp Training
Enable/Disable ClkTCO Comp Training
$EN_DIS
**/
UINT8 CLKTCO;
-/** Offset 0x0783 - CMD Slew Rate Training
+/** Offset 0x0863 - CMD Slew Rate Training
Enable/Disable CMD Slew Rate Training
$EN_DIS
**/
UINT8 CMDSR;
-/** Offset 0x0784 - CMD Drive Strength and Tx Equalization
+/** Offset 0x0864 - CMD Drive Strength and Tx Equalization
Enable/Disable CMD Drive Strength and Tx Equalization
$EN_DIS
**/
UINT8 CMDDSEQ;
-/** Offset 0x0785 - DIMM CA ODT Training
+/** Offset 0x0865 - DIMM CA ODT Training
Enable/Disable DIMM CA ODT Training
$EN_DIS
**/
UINT8 DIMMODTCA;
-/** Offset 0x0786 - TxDqsTCO Comp Training
+/** Offset 0x0866 - TxDqsTCO Comp Training
Enable/Disable TxDqsTCO Comp Training
$EN_DIS
**/
UINT8 TXTCODQS;
-/** Offset 0x0787 - CMD/CTL Drive Strength Up/Dn 2D
+/** Offset 0x0867 - CMD/CTL Drive Strength Up/Dn 2D
Enable/Disable CMD/CTL Drive Strength Up/Dn 2D
$EN_DIS
**/
UINT8 CMDDRUD;
-/** Offset 0x0788 - VccDLL Bypass Training
+/** Offset 0x0868 - VccDLL Bypass Training
Enable/Disable VccDLL Bypass Training
$EN_DIS
**/
UINT8 VCCDLLBP;
-/** Offset 0x0789 - PanicVttDnLp Training
+/** Offset 0x0869 - PanicVttDnLp Training
Enable/Disable PanicVttDnLp Training
$EN_DIS
**/
UINT8 PVTTDNLP;
-/** Offset 0x078A - Read Vref Decap Training*
+/** Offset 0x086A - Read Vref Decap Training*
Enable/Disable Read Vref Decap Training*
$EN_DIS
**/
UINT8 RDVREFDC;
-/** Offset 0x078B - Vddq Training
+/** Offset 0x086B - Vddq Training
Enable/Disable Vddq Training
$EN_DIS
**/
UINT8 VDDQT;
-/** Offset 0x078C - Rank Margin Tool Per Bit
+/** Offset 0x086C - Rank Margin Tool Per Bit
Enable/Disable Rank Margin Tool Per Bit
$EN_DIS
**/
UINT8 RMTBIT;
-/** Offset 0x078D - Reserved
+/** Offset 0x086D - Reserved
**/
- UINT8 Reserved24[2];
+ UINT8 Reserved33[2];
-/** Offset 0x078F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+/** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
$EN_DIS
**/
UINT8 Ddr4DdpSharedClock;
-/** Offset 0x0790 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+/** Offset 0x0870 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
$EN_DIS
**/
UINT8 Ddr4DdpSharedZq;
-/** Offset 0x0791 - Ch Hash Interleaved Bit
+/** Offset 0x0871 - Ch Hash Interleaved Bit
Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
**/
UINT8 ChHashInterleaveBit;
-/** Offset 0x0792 - Ch Hash Mask
+/** Offset 0x0872 - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
BITS [19:6] Default is 0x30CC
**/
UINT16 ChHashMask;
-/** Offset 0x0794 - Base reference clock value
+/** Offset 0x0874 - Base reference clock value
Base reference clock value, in Hertz(Default is 100Hz)
100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
**/
UINT32 BClkFrequency;
-/** Offset 0x0798 - EPG DIMM Idd3N
+/** Offset 0x0878 - EPG DIMM Idd3N
Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
a per DIMM basis. Default is 26
**/
UINT16 Idd3n;
-/** Offset 0x079A - EPG DIMM Idd3P
+/** Offset 0x087A - EPG DIMM Idd3P
Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
on a per DIMM basis. Default is 11
**/
UINT16 Idd3p;
-/** Offset 0x079C - CMD Normalization
+/** Offset 0x087C - CMD Normalization
Enable/Disable CMD Normalization
$EN_DIS
**/
UINT8 CMDNORM;
-/** Offset 0x079D - Early DQ Write Drive Strength and Equalization Training
+/** Offset 0x087D - Early DQ Write Drive Strength and Equalization Training
Enable/Disable Early DQ Write Drive Strength and Equalization Training
$EN_DIS
**/
UINT8 EWRDSEQ;
-/** Offset 0x079E - Reserved
+/** Offset 0x087E - Reserved
**/
- UINT8 Reserved25;
+ UINT8 Reserved34;
-/** Offset 0x079F - Idle Energy Mc0Ch0Dimm0
+/** Offset 0x087F - Idle Energy Mc0Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch0Dimm0;
-/** Offset 0x07A0 - Idle Energy Mc0Ch0Dimm1
+/** Offset 0x0880 - Idle Energy Mc0Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch0Dimm1;
-/** Offset 0x07A1 - Idle Energy Mc0Ch1Dimm0
+/** Offset 0x0881 - Idle Energy Mc0Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch1Dimm0;
-/** Offset 0x07A2 - Idle Energy Mc0Ch1Dimm1
+/** Offset 0x0882 - Idle Energy Mc0Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch1Dimm1;
-/** Offset 0x07A3 - Idle Energy Mc1Ch0Dimm0
+/** Offset 0x0883 - Idle Energy Mc1Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch0Dimm0;
-/** Offset 0x07A4 - Idle Energy Mc1Ch0Dimm1
+/** Offset 0x0884 - Idle Energy Mc1Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch0Dimm1;
-/** Offset 0x07A5 - Idle Energy Mc1Ch1Dimm0
+/** Offset 0x0885 - Idle Energy Mc1Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch1Dimm0;
-/** Offset 0x07A6 - Idle Energy Mc1Ch1Dimm1
+/** Offset 0x0886 - Idle Energy Mc1Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch1Dimm1;
-/** Offset 0x07A7 - PowerDown Energy Mc0Ch0Dimm0
+/** Offset 0x0887 - PowerDown Energy Mc0Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch0Dimm0;
-/** Offset 0x07A8 - PowerDown Energy Mc0Ch0Dimm1
+/** Offset 0x0888 - PowerDown Energy Mc0Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch0Dimm1;
-/** Offset 0x07A9 - PowerDown Energy Mc0Ch1Dimm0
+/** Offset 0x0889 - PowerDown Energy Mc0Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch1Dimm0;
-/** Offset 0x07AA - PowerDown Energy Mc0Ch1Dimm1
+/** Offset 0x088A - PowerDown Energy Mc0Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch1Dimm1;
-/** Offset 0x07AB - PowerDown Energy Mc1Ch0Dimm0
+/** Offset 0x088B - PowerDown Energy Mc1Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch0Dimm0;
-/** Offset 0x07AC - PowerDown Energy Mc1Ch0Dimm1
+/** Offset 0x088C - PowerDown Energy Mc1Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch0Dimm1;
-/** Offset 0x07AD - PowerDown Energy Mc1Ch1Dimm0
+/** Offset 0x088D - PowerDown Energy Mc1Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch1Dimm0;
-/** Offset 0x07AE - PowerDown Energy Mc1Ch1Dimm1
+/** Offset 0x088E - PowerDown Energy Mc1Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch1Dimm1;
-/** Offset 0x07AF - Activate Energy Mc0Ch0Dimm0
+/** Offset 0x088F - Activate Energy Mc0Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch0Dimm0;
-/** Offset 0x07B0 - Activate Energy Mc0Ch0Dimm1
+/** Offset 0x0890 - Activate Energy Mc0Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch0Dimm1;
-/** Offset 0x07B1 - Activate Energy Mc0Ch1Dimm0
+/** Offset 0x0891 - Activate Energy Mc0Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch1Dimm0;
-/** Offset 0x07B2 - Activate Energy Mc0Ch1Dimm1
+/** Offset 0x0892 - Activate Energy Mc0Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch1Dimm1;
-/** Offset 0x07B3 - Activate Energy Mc1Ch0Dimm0
+/** Offset 0x0893 - Activate Energy Mc1Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch0Dimm0;
-/** Offset 0x07B4 - Activate Energy Mc1Ch0Dimm1
+/** Offset 0x0894 - Activate Energy Mc1Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch0Dimm1;
-/** Offset 0x07B5 - Activate Energy Mc1Ch1Dimm0
+/** Offset 0x0895 - Activate Energy Mc1Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch1Dimm0;
-/** Offset 0x07B6 - Activate Energy Mc1Ch1Dimm1
+/** Offset 0x0896 - Activate Energy Mc1Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch1Dimm1;
-/** Offset 0x07B7 - Read Energy Mc0Ch0Dimm0
+/** Offset 0x0897 - Read Energy Mc0Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch0Dimm0;
-/** Offset 0x07B8 - Read Energy Mc0Ch0Dimm1
+/** Offset 0x0898 - Read Energy Mc0Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch0Dimm1;
-/** Offset 0x07B9 - Read Energy Mc0Ch1Dimm0
+/** Offset 0x0899 - Read Energy Mc0Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch1Dimm0;
-/** Offset 0x07BA - Read Energy Mc0Ch1Dimm1
+/** Offset 0x089A - Read Energy Mc0Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch1Dimm1;
-/** Offset 0x07BB - Read Energy Mc1Ch0Dimm0
+/** Offset 0x089B - Read Energy Mc1Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch0Dimm0;
-/** Offset 0x07BC - Read Energy Mc1Ch0Dimm1
+/** Offset 0x089C - Read Energy Mc1Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch0Dimm1;
-/** Offset 0x07BD - Read Energy Mc1Ch1Dimm0
+/** Offset 0x089D - Read Energy Mc1Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch1Dimm0;
-/** Offset 0x07BE - Read Energy Mc1Ch1Dimm1
+/** Offset 0x089E - Read Energy Mc1Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch1Dimm1;
-/** Offset 0x07BF - Write Energy Mc0Ch0Dimm0
+/** Offset 0x089F - Write Energy Mc0Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch0Dimm0;
-/** Offset 0x07C0 - Write Energy Mc0Ch0Dimm1
+/** Offset 0x08A0 - Write Energy Mc0Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch0Dimm1;
-/** Offset 0x07C1 - Write Energy Mc0Ch1Dimm0
+/** Offset 0x08A1 - Write Energy Mc0Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch1Dimm0;
-/** Offset 0x07C2 - Write Energy Mc0Ch1Dimm1
+/** Offset 0x08A2 - Write Energy Mc0Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch1Dimm1;
-/** Offset 0x07C3 - Write Energy Mc1Ch0Dimm0
+/** Offset 0x08A3 - Write Energy Mc1Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch0Dimm0;
-/** Offset 0x07C4 - Write Energy Mc1Ch0Dimm1
+/** Offset 0x08A4 - Write Energy Mc1Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch0Dimm1;
-/** Offset 0x07C5 - Write Energy Mc1Ch1Dimm0
+/** Offset 0x08A5 - Write Energy Mc1Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch1Dimm0;
-/** Offset 0x07C6 - Write Energy Mc1Ch1Dimm1
+/** Offset 0x08A6 - Write Energy Mc1Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch1Dimm1;
-/** Offset 0x07C7 - Throttler CKEMin Timer
+/** Offset 0x08A7 - Throttler CKEMin Timer
Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
Dfault is 0x00
**/
UINT8 ThrtCkeMinTmr;
-/** Offset 0x07C8 - Reserved
+/** Offset 0x08A8 - Reserved
**/
- UINT8 Reserved26[2];
+ UINT8 Reserved35[2];
-/** Offset 0x07CA - Rapl Power Floor Ch0
+/** Offset 0x08AA - Rapl Power Floor Ch0
Power budget ,range[255;0],(0= 5.3W Def)
**/
UINT8 RaplPwrFlCh0;
-/** Offset 0x07CB - Rapl Power Floor Ch1
+/** Offset 0x08AB - Rapl Power Floor Ch1
Power budget ,range[255;0],(0= 5.3W Def)
**/
UINT8 RaplPwrFlCh1;
-/** Offset 0x07CC - Command Rate Support
+/** Offset 0x08AC - Command Rate Support
CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS
**/
UINT8 EnCmdRate;
-/** Offset 0x07CD - REFRESH_2X_MODE
+/** Offset 0x08AD - REFRESH_2X_MODE
0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
**/
UINT8 Refresh2X;
-/** Offset 0x07CE - Energy Performance Gain
+/** Offset 0x08AE - Energy Performance Gain
Enable/disable(default) Energy Performance Gain.
$EN_DIS
**/
UINT8 EpgEnable;
-/** Offset 0x07CF - Reserved
+/** Offset 0x08AF - Reserved
**/
- UINT8 Reserved27;
+ UINT8 Reserved36;
-/** Offset 0x07D0 - User Manual Threshold
+/** Offset 0x08B0 - User Manual Threshold
Disabled: Predefined threshold will be used.\n
Enabled: User Input will be used.
$EN_DIS
**/
UINT8 UserThresholdEnable;
-/** Offset 0x07D1 - User Manual Budget
+/** Offset 0x08B1 - User Manual Budget
Disabled: Configuration of memories will defined the Budget value.\n
Enabled: User Input will be used.
$EN_DIS
**/
UINT8 UserBudgetEnable;
-/** Offset 0x07D2 - Power Down Mode
+/** Offset 0x08B2 - Power Down Mode
This option controls command bus tristating during idle periods
0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
**/
UINT8 PowerDownMode;
-/** Offset 0x07D3 - Pwr Down Idle Timer
+/** Offset 0x08B3 - Pwr Down Idle Timer
The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
AUTO: 64 for ULX/ULT, 128 for DT/Halo
**/
UINT8 PwdwnIdleCounter;
-/** Offset 0x07D4 - Page Close Idle Timeout
+/** Offset 0x08B4 - Page Close Idle Timeout
This option controls Page Close Idle Timeout
0:Enabled, 1:Disabled
**/
UINT8 DisPgCloseIdleTimeout;
-/** Offset 0x07D5 - Bitmask of ranks that have CA bus terminated
+/** Offset 0x08B5 - Bitmask of ranks that have CA bus terminated
Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
Rank0 is terminating and Rank1 is non-terminating</b>
**/
UINT8 CmdRanksTerminated;
-/** Offset 0x07D6 - PcdSerialDebugLevel
+/** Offset 0x08B6 - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -2707,91 +2821,91 @@ typedef struct {
**/
UINT8 PcdSerialDebugLevel;
-/** Offset 0x07D7 - Safe Mode Support
+/** Offset 0x08B7 - Safe Mode Support
This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
$EN_DIS
**/
UINT8 SafeMode;
-/** Offset 0x07D8 - Ask MRC to clear memory content
+/** Offset 0x08B8 - Ask MRC to clear memory content
Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
$EN_DIS
**/
UINT8 CleanMemory;
-/** Offset 0x07D9 - LpDdrDqDqsReTraining
+/** Offset 0x08B9 - LpDdrDqDqsReTraining
Enable/Disable TxDqDqs ReTraining for LP4/5 and DDR5
$EN_DIS
**/
UINT8 LpDdrDqDqsReTraining;
-/** Offset 0x07DA - TCSS USB Port Enable
+/** Offset 0x08BA - TCSS USB Port Enable
Bitmap for per port enabling
**/
UINT8 UsbTcPortEnPreMem;
-/** Offset 0x07DB - Reserved
+/** Offset 0x08BB - Reserved
**/
- UINT8 Reserved28;
+ UINT8 Reserved37;
-/** Offset 0x07DC - Post Code Output Port
+/** Offset 0x08BC - Post Code Output Port
This option configures Post Code Output Port
**/
UINT16 PostCodeOutputPort;
-/** Offset 0x07DE - RMTLoopCount
+/** Offset 0x08BE - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
**/
UINT8 RMTLoopCount;
-/** Offset 0x07DF - Enable/Disable SA CRID
+/** Offset 0x08BF - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID
$EN_DIS
**/
UINT8 CridEnable;
-/** Offset 0x07E0 - WRC Feature
+/** Offset 0x08C0 - WRC Feature
Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports
IO devices allocating onto the ring and into LLC. WRC is fused on by default.
$EN_DIS
**/
UINT8 WrcFeatureEnable;
-/** Offset 0x07E1 - Reserved
+/** Offset 0x08C1 - Reserved
**/
- UINT8 Reserved29[3];
+ UINT8 Reserved38[3];
-/** Offset 0x07E4 - BCLK RFI Frequency
+/** Offset 0x08C4 - BCLK RFI Frequency
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
RFI Tuning</b>. Range is 98Mhz-100Mhz.
**/
UINT32 BclkRfiFreq[4];
-/** Offset 0x07F4 - Size of PCIe IMR.
+/** Offset 0x08D4 - Size of PCIe IMR.
Size of PCIe IMR in megabytes
**/
UINT16 PcieImrSize;
-/** Offset 0x07F6 - Enable PCIe IMR
+/** Offset 0x08D6 - Enable PCIe IMR
0: Disable(AUTO), 1: Enable
$EN_DIS
**/
UINT8 PcieImrEnabled;
-/** Offset 0x07F7 - Enable PCIe IMR
+/** Offset 0x08D7 - Enable PCIe IMR
1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
the Root port location from PCH PCIe or SA PCIe
$EN_DIS
**/
UINT8 PcieImrRpLocation;
-/** Offset 0x07F8 - Root port number for IMR.
+/** Offset 0x08D8 - Root port number for IMR.
Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
**/
UINT8 PcieImrRpSelection;
-/** Offset 0x07F9 - SerialDebugMrcLevel
+/** Offset 0x08D9 - SerialDebugMrcLevel
MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -2800,342 +2914,242 @@ typedef struct {
**/
UINT8 SerialDebugMrcLevel;
-/** Offset 0x07FA - Ddr4OneDpc
+/** Offset 0x08DA - Ddr4OneDpc
DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
or on both (default)
0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
**/
UINT8 Ddr4OneDpc;
-/** Offset 0x07FB - Reserved
+/** Offset 0x08DB - Reserved
**/
- UINT8 Reserved30[3];
+ UINT8 Reserved39[3];
-/** Offset 0x07FE - REFRESH_PANIC_WM
+/** Offset 0x08DE - REFRESH_PANIC_WM
Refresh Panic Watermark, range 1-9, Default is 9
**/
UINT8 RefreshPanicWm;
-/** Offset 0x07FF - REFRESH_HP_WM
+/** Offset 0x08DF - REFRESH_HP_WM
Refresh High Priority Watermark, range 1-8, Default is 8
**/
UINT8 RefreshHpWm;
-/** Offset 0x0800 - Command Pins Mapping
+/** Offset 0x08E0 - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
**/
UINT8 Lp5CccConfig;
-/** Offset 0x0801 - Command Pins Mirrored
+/** Offset 0x08E1 - Command Pins Mirrored
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
**/
UINT8 CmdMirror;
-/** Offset 0x0802 - Reserved
+/** Offset 0x08E2 - Reserved
**/
- UINT8 Reserved31[9];
+ UINT8 Reserved40[9];
-/** Offset 0x080B - Skip external display device scanning
+/** Offset 0x08EB - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x080C - Generate BIOS Data ACPI Table
+/** Offset 0x08EC - Generate BIOS Data ACPI Table
Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
$EN_DIS
**/
UINT8 BdatEnable;
-/** Offset 0x080D - Lock PCU Thermal Management registers
+/** Offset 0x08ED - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
-/** Offset 0x080E - Reserved
+/** Offset 0x08EE - Reserved
**/
- UINT8 Reserved32;
+ UINT8 Reserved41;
-/** Offset 0x080F - Panel Power Enable
+/** Offset 0x08EF - Panel Power Enable
Control for enabling/disabling VDD force bit (Required only for early enabling of
eDP panel). 0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 PanelPowerEnable;
-/** Offset 0x0810 - BdatTestType
+/** Offset 0x08F0 - BdatTestType
Indicates the type of Memory Training data to populate into the BDAT ACPI table.
0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
**/
UINT8 BdatTestType;
-/** Offset 0x0811 - Reserved
+/** Offset 0x08F1 - Reserved
**/
- UINT8 Reserved33[3];
+ UINT8 Reserved42[3];
-/** Offset 0x0814 - PMR Size
+/** Offset 0x08F4 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
**/
UINT32 DmaBufferSize;
-/** Offset 0x0818 - VT-d/IOMMU Boot Policy
+/** Offset 0x08F8 - VT-d/IOMMU Boot Policy
BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
**/
UINT8 PreBootDmaMask;
-/** Offset 0x0819 - Reserved
+/** Offset 0x08F9 - Reserved
**/
- UINT8 Reserved34[95];
+ UINT8 Reserved43[95];
-/** Offset 0x0878 - TotalFlashSize
+/** Offset 0x0958 - TotalFlashSize
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
**/
UINT16 TotalFlashSize;
-/** Offset 0x087A - BiosSize
+/** Offset 0x095A - BiosSize
The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
Range) so that a BIOS Update Script can be stored in the DPR.
**/
UINT16 BiosSize;
-/** Offset 0x087C - Reserved
+/** Offset 0x095C - Reserved
**/
- UINT8 Reserved35[12];
+ UINT8 Reserved44[12];
-/** Offset 0x0888 - Smbus dynamic power gating
+/** Offset 0x0968 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
$EN_DIS
**/
UINT8 SmbusDynamicPowerGating;
-/** Offset 0x0889 - Disable and Lock Watch Dog Register
+/** Offset 0x0969 - Disable and Lock Watch Dog Register
Set 1 to clear WDT status, then disable and lock WDT registers.
$EN_DIS
**/
UINT8 WdtDisableAndLock;
-/** Offset 0x088A - SMBUS SPD Write Disable
+/** Offset 0x096A - SMBUS SPD Write Disable
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
Disable bit. For security recommendations, SPD write disable bit must be set.
$EN_DIS
**/
UINT8 SmbusSpdWriteDisable;
-/** Offset 0x088B - Force ME DID Init Status
+/** Offset 0x096B - Force ME DID Init Status
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
ME DID init stat value
$EN_DIS
**/
UINT8 DidInitStat;
-/** Offset 0x088C - CPU Replaced Polling Disable
+/** Offset 0x096C - CPU Replaced Polling Disable
Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
$EN_DIS
**/
UINT8 DisableCpuReplacedPolling;
-/** Offset 0x088D - Check HECI message before send
+/** Offset 0x096D - Check HECI message before send
Test, 0: disable, 1: enable, Enable/Disable message check.
$EN_DIS
**/
UINT8 DisableMessageCheck;
-/** Offset 0x088E - Skip MBP HOB
+/** Offset 0x096E - Skip MBP HOB
Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
$EN_DIS
**/
UINT8 SkipMbpHob;
-/** Offset 0x088F - HECI2 Interface Communication
+/** Offset 0x096F - HECI2 Interface Communication
Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
$EN_DIS
**/
UINT8 HeciCommunication2;
-/** Offset 0x0890 - Enable KT device
+/** Offset 0x0970 - Enable KT device
Test, 0: disable, 1: enable, Enable or Disable KT device.
$EN_DIS
**/
UINT8 KtDeviceEnable;
-/** Offset 0x0891 - Skip CPU replacement check
+/** Offset 0x0971 - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
$EN_DIS
**/
UINT8 SkipCpuReplacementCheck;
-/** Offset 0x0892 - Reserved
+/** Offset 0x0972 - Reserved
**/
- UINT8 Reserved36[2];
+ UINT8 Reserved45[2];
-/** Offset 0x0894 - Hybrid Graphics GPIO information for PEG 1
+/** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1
Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
**/
UINT32 CpuPcie1Rtd3Gpio[24];
-/** Offset 0x08F4 - Hybrid Graphics GPIO information for PEG 2
+/** Offset 0x09D4 - Hybrid Graphics GPIO information for PEG 2
Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
**/
UINT32 CpuPcie2Rtd3Gpio[24];
-/** Offset 0x0954 - Hybrid Graphics GPIO information for PEG 3
+/** Offset 0x0A34 - Hybrid Graphics GPIO information for PEG 3
Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
**/
UINT32 CpuPcie3Rtd3Gpio[24];
-/** Offset 0x09B4 - Avx2 Voltage Guardband Scaling Factor
+/** Offset 0x0A94 - Avx2 Voltage Guardband Scaling Factor
AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx2VoltageScaleFactor;
-/** Offset 0x09B5 - Avx512 Voltage Guardband Scaling Factor
+/** Offset 0x0A95 - Avx512 Voltage Guardband Scaling Factor
AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200
in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx512VoltageScaleFactor;
-/** Offset 0x09B6 - Serial Io Uart Debug Mode
+/** Offset 0x0A96 - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
-/** Offset 0x09B7 - Reserved
+/** Offset 0x0A97 - Reserved
**/
- UINT8 Reserved37;
+ UINT8 Reserved46;
-/** Offset 0x09B8 - SerialIoUartDebugRxPinMux - FSPT
+/** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT
Select RX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugRxPinMux;
-/** Offset 0x09BC - SerialIoUartDebugTxPinMux - FSPM
+/** Offset 0x0A9C - SerialIoUartDebugTxPinMux - FSPM
Select TX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugTxPinMux;
-/** Offset 0x09C0 - SerialIoUartDebugRtsPinMux - FSPM
+/** Offset 0x0AA0 - SerialIoUartDebugRtsPinMux - FSPM
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
for possible values.
**/
UINT32 SerialIoUartDebugRtsPinMux;
-/** Offset 0x09C4 - SerialIoUartDebugCtsPinMux - FSPM
+/** Offset 0x0AA4 - SerialIoUartDebugCtsPinMux - FSPM
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
for possible values.
**/
UINT32 SerialIoUartDebugCtsPinMux;
-/** Offset 0x09C8 - Reserved
-**/
- UINT8 Reserved38;
-
-/** Offset 0x09C9 - Core VF Point Offset Mode
- Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
- In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
- setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
- 0:Legacy, 1:Selection
-**/
- UINT8 CoreVfPointOffsetMode;
-
-/** Offset 0x09CA - Core VF Point Offset
- Array used to specifies the Core Voltage Offset applied to the each selected VF
- Point. This voltage is specified in millivolts.
-**/
- UINT16 CoreVfPointOffset[15];
-
-/** Offset 0x09E8 - Core VF Point Offset Prefix
- Sets the CoreVfPointOffset value as positive or negative for corresponding core
- VF Point; <b>0: Positive </b>; 1: Negative.
- 0:Positive, 1:Negative
-**/
- UINT8 CoreVfPointOffsetPrefix[15];
-
-/** Offset 0x09F7 - Core VF Point Ratio
- Array for the each selected Core VF Point to display the ration.
-**/
- UINT8 CoreVfPointRatio[15];
-
-/** Offset 0x0A06 - Core VF Point Count
- Number of supported Core Voltage & Frequency Point Offset
-**/
- UINT8 CoreVfPointCount;
-
-/** Offset 0x0A07 - Reserved
-**/
- UINT8 Reserved39[25];
-
-/** Offset 0x0A20 - Per Core Max Ratio override
- Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
- favored core ratio to each Core. <b>0: Disable</b>, 1: enable
- $EN_DIS
-**/
- UINT8 PerCoreRatioOverride;
-
-/** Offset 0x0A21 - Per Core Current Max Ratio
- Array for the Per Core Max Ratio
-**/
- UINT8 PerCoreRatio[8];
-
-/** Offset 0x0A29 - Reserved
-**/
- UINT8 Reserved40[5];
-
-/** Offset 0x0A2E - Pvd Ratio Threshold
- Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default.
-**/
- UINT8 PvdRatioThreshold;
-
-/** Offset 0x0A2F - Support Unlimited ICCMAX
- Support Unlimited ICCMAX more than maximum value 255.75A; <b>0: Disabled</b>; 1: Enabled.
- $EN_DIS
-**/
- UINT8 UnlimitedIccMax;
-
-/** Offset 0x0A30 - Enable CPU CrashLog GPRs dump
- Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
- disable Smm GPRs dump
- 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
-**/
- UINT8 CrashLogGprs;
-
-/** Offset 0x0A31 - Reserved
-**/
- UINT8 Reserved41[62];
-
-/** Offset 0x0A6F - BCLK Frequency Source
- Clock source of BCLK OC frequency, <b>1:CPU BCLK</b>, 2:PCH BCLK, 3:External CLK
- 1:CPU BCLK, 2:PCH BCLK, 3:External CLK
-**/
- UINT8 BclkSource;
-
-/** Offset 0x0A70 - GPIO Override
- Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
- before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
- configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
-**/
- UINT8 GpioOverride;
-
-/** Offset 0x0A71 - Reserved
-**/
- UINT8 Reserved42[3];
-
-/** Offset 0x0A74 - CPU BCLK OC Frequency
- CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0
- - Auto</b>. Range is 8000-50000 (10KHz).
-**/
- UINT32 CpuBclkOcFrequency;
-
-/** Offset 0x0A78 - Reserved
+/** Offset 0x0AA8 - Reserved
**/
- UINT8 Reserved43[16];
+ UINT8 Reserved47[16];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -3154,11 +3168,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0A88
+/** Offset 0x0AB8
**/
- UINT8 UnusedUpdSpace24[6];
+ UINT8 UnusedUpdSpace28[6];
-/** Offset 0x0A8E
+/** Offset 0x0ABE
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
index 4cd435d5bd..efacdc1923 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
@@ -883,187 +883,183 @@ typedef struct {
**/
UINT8 CnviBtAudioOffload;
-/** Offset 0x0438 - Reserved
-**/
- UINT8 Reserved14[4];
-
-/** Offset 0x043C - CNVi RF_RESET pin muxing
+/** Offset 0x0438 - CNVi RF_RESET pin muxing
Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default)
or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
**/
UINT32 CnviRfResetPinMux;
-/** Offset 0x0440 - CNVi CLKREQ pin muxing
+/** Offset 0x043C - CNVi CLKREQ pin muxing
Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default)
or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_*
in GpioPins*.h.
**/
UINT32 CnviClkreqPinMux;
-/** Offset 0x0444 - Enable Host C10 reporting through eSPI
+/** Offset 0x0440 - Enable Host C10 reporting through eSPI
Enable/disable Host C10 reporting to Device via eSPI Virtual Wire.
$EN_DIS
**/
UINT8 PchEspiHostC10ReportEnable;
-/** Offset 0x0445 - PCH USB2 PHY Power Gating enable
+/** Offset 0x0441 - PCH USB2 PHY Power Gating enable
1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
Sus Well PG
$EN_DIS
**/
UINT8 PmcUsb2PhySusPgEnable;
-/** Offset 0x0446 - PCH USB OverCurrent mapping enable
+/** Offset 0x0442 - PCH USB OverCurrent mapping enable
1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
mapping allow for NOA usage of OC pins
$EN_DIS
**/
UINT8 PchUsbOverCurrentEnable;
-/** Offset 0x0447 - Espi Lgmr Memory Range decode
+/** Offset 0x0443 - Espi Lgmr Memory Range decode
This option enables or disables espi lgmr
$EN_DIS
**/
UINT8 PchEspiLgmrEnable;
-/** Offset 0x0448 - External V1P05 Control Ramp Timer value
+/** Offset 0x0444 - External V1P05 Control Ramp Timer value
Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
**/
UINT8 PchFivrExtV1p05RailCtrlRampTmr;
-/** Offset 0x0449 - External VNN Control Ramp Timer value
+/** Offset 0x0445 - External VNN Control Ramp Timer value
Hold off time to be used when changing the vnn_ctrl for external bypass value in us
**/
UINT8 PchFivrExtVnnRailCtrlRampTmr;
-/** Offset 0x044A - Set SATA DEVSLP GPIO Reset Config
+/** Offset 0x0446 - Set SATA DEVSLP GPIO Reset Config
Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
for each port, byte0 for port0, byte1 for port1, and so on.
**/
UINT8 SataPortsDevSlpResetConfig[8];
-/** Offset 0x0452 - PCHHOT# pin
+/** Offset 0x044E - PCHHOT# pin
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchHotEnable;
-/** Offset 0x0453 - SATA LED
+/** Offset 0x044F - SATA LED
SATA LED indicating SATA controller activity. 0: disable, 1: enable
$EN_DIS
**/
UINT8 SataLedEnable;
-/** Offset 0x0454 - VRAlert# Pin
+/** Offset 0x0450 - VRAlert# Pin
When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchPmVrAlert;
-/** Offset 0x0455 - AMT Switch
+/** Offset 0x0451 - AMT Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
$EN_DIS
**/
UINT8 AmtEnabled;
-/** Offset 0x0456 - WatchDog Timer Switch
+/** Offset 0x0452 - WatchDog Timer Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 WatchDogEnabled;
-/** Offset 0x0457 - PET Progress
+/** Offset 0x0453 - PET Progress
Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
PET Events. Setting is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 FwProgress;
-/** Offset 0x0458 - SOL Switch
+/** Offset 0x0454 - SOL Switch
Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
Setting is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 AmtSolEnabled;
-/** Offset 0x0459 - Reserved
+/** Offset 0x0455 - Reserved
**/
- UINT8 Reserved15;
+ UINT8 Reserved14;
-/** Offset 0x045A - OS Timer
+/** Offset 0x0456 - OS Timer
16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
UINT16 WatchDogTimerOs;
-/** Offset 0x045C - BIOS Timer
+/** Offset 0x0458 - BIOS Timer
16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
UINT16 WatchDogTimerBios;
-/** Offset 0x045E - Force MEBX execution
+/** Offset 0x045A - Force MEBX execution
Enable/Disable. 0: Disable, 1: enable, Force MEBX execution.
$EN_DIS
**/
UINT8 ForcMebxSyncUp;
-/** Offset 0x045F - PCH PCIe root port connection type
+/** Offset 0x045B - PCH PCIe root port connection type
0: built-in device, 1:slot
**/
UINT8 PcieRpSlotImplemented[28];
-/** Offset 0x047B - PCIE RP Access Control Services Extended Capability
+/** Offset 0x0477 - PCIE RP Access Control Services Extended Capability
Enable/Disable PCIE RP Access Control Services Extended Capability
**/
UINT8 PcieRpAcsEnabled[28];
-/** Offset 0x0497 - PCIE RP Clock Power Management
+/** Offset 0x0493 - PCIE RP Clock Power Management
Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
can still be controlled by L1 PM substates mechanism
**/
UINT8 PcieRpEnableCpm[28];
-/** Offset 0x04B3 - Reserved
+/** Offset 0x04AF - Reserved
**/
- UINT8 Reserved16;
+ UINT8 Reserved15;
-/** Offset 0x04B4 - PCIE RP Detect Timeout Ms
+/** Offset 0x04B0 - PCIE RP Detect Timeout Ms
The number of milliseconds within 0~65535 in reference code will wait for link to
exit Detect state for enabled ports before assuming there is no device and potentially
disabling the port.
**/
UINT16 PcieRpDetectTimeoutMs[28];
-/** Offset 0x04EC - ModPHY SUS Power Domain Dynamic Gating
+/** Offset 0x04E8 - ModPHY SUS Power Domain Dynamic Gating
Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
PCH-H. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcModPhySusPgEnable;
-/** Offset 0x04ED - V1p05-PHY supply external FET control
+/** Offset 0x04E9 - V1p05-PHY supply external FET control
Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
supply. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcV1p05PhyExtFetControlEn;
-/** Offset 0x04EE - V1p05-IS supply external FET control
+/** Offset 0x04EA - V1p05-IS supply external FET control
Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
supply. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcV1p05IsExtFetControlEn;
-/** Offset 0x04EF - Enable/Disable PavpEnable
+/** Offset 0x04EB - Enable/Disable PavpEnable
Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
$EN_DIS
**/
UINT8 PavpEnable;
-/** Offset 0x04F0 - CdClock Frequency selection
+/** Offset 0x04EC - CdClock Frequency selection
0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
@@ -1071,363 +1067,363 @@ typedef struct {
**/
UINT8 CdClock;
-/** Offset 0x04F1 - Enable/Disable PeiGraphicsPeimInit
+/** Offset 0x04ED - Enable/Disable PeiGraphicsPeimInit
<b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
Disable: FSP will NOT initialize the framebuffer.
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
-/** Offset 0x04F2 - Enable D3 Hot in TCSS
+/** Offset 0x04EE - Enable D3 Hot in TCSS
This policy will enable/disable D3 hot support in IOM
$EN_DIS
**/
UINT8 D3HotEnable;
-/** Offset 0x04F3 - Enable or disable GNA device
+/** Offset 0x04EF - Enable or disable GNA device
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 GnaEnable;
-/** Offset 0x04F4 - TypeC port GPIO setting
+/** Offset 0x04F0 - TypeC port GPIO setting
GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
= AlderLake)
**/
UINT32 IomTypeCPortPadCfg[8];
-/** Offset 0x0514 - CPU USB3 Port Over Current Pin
+/** Offset 0x0510 - CPU USB3 Port Over Current Pin
Describe the specific over current pin number of USBC Port N.
**/
UINT8 CpuUsb3OverCurrentPin[8];
-/** Offset 0x051C - Enable D3 Cold in TCSS
+/** Offset 0x0518 - Enable D3 Cold in TCSS
This policy will enable/disable D3 cold support in IOM
$EN_DIS
**/
UINT8 D3ColdEnable;
-/** Offset 0x051D - Enable/Disable PCIe tunneling for USB4
+/** Offset 0x0519 - Enable/Disable PCIe tunneling for USB4
Enable/Disable PCIe tunneling for USB4, default is enable
$EN_DIS
**/
UINT8 ITbtPcieTunnelingForUsb4;
-/** Offset 0x051E - Enable/Disable SkipFspGop
+/** Offset 0x051A - Enable/Disable SkipFspGop
Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
$EN_DIS
**/
UINT8 SkipFspGop;
-/** Offset 0x051F - TC State in TCSS
+/** Offset 0x051B - TC State in TCSS
This TC C-State Limit in IOM
**/
UINT8 TcCstateLimit;
-/** Offset 0x0520 - Intel Graphics VBT (Video BIOS Table) Size
+/** Offset 0x051C - Intel Graphics VBT (Video BIOS Table) Size
Size of Internal Graphics VBT Image
**/
UINT32 VbtSize;
-/** Offset 0x0524 - Platform LID Status for LFP Displays.
+/** Offset 0x0520 - Platform LID Status for LFP Displays.
LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
0: LidClosed, 1: LidOpen
**/
UINT8 LidStatus;
-/** Offset 0x0525 - Reserved
+/** Offset 0x0521 - Reserved
**/
- UINT8 Reserved17[8];
+ UINT8 Reserved16[8];
-/** Offset 0x052D - Enable VMD controller
+/** Offset 0x0529 - Enable VMD controller
Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
$EN_DIS
**/
UINT8 VmdEnable;
-/** Offset 0x052E - Map port under VMD
+/** Offset 0x052A - Map port under VMD
Map/UnMap port under VMD
$EN_DIS
**/
UINT8 VmdPort[31];
-/** Offset 0x054D - VMD Port Device
+/** Offset 0x0549 - VMD Port Device
VMD Root port device number.
**/
UINT8 VmdPortDev[31];
-/** Offset 0x056C - VMD Port Func
+/** Offset 0x0568 - VMD Port Func
VMD Root port function number.
**/
UINT8 VmdPortFunc[31];
-/** Offset 0x058B - VMD Config Bar size
+/** Offset 0x0587 - VMD Config Bar size
Set The VMD Config Bar Size.
**/
UINT8 VmdCfgBarSize;
-/** Offset 0x058C - VMD Config Bar Attributes
+/** Offset 0x0588 - VMD Config Bar Attributes
0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH
0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
**/
UINT8 VmdCfgBarAttr;
-/** Offset 0x058D - VMD Mem Bar1 size
+/** Offset 0x0589 - VMD Mem Bar1 size
Set The VMD Mem Bar1 Size.
**/
UINT8 VmdMemBarSize1;
-/** Offset 0x058E - VMD Mem Bar1 Attributes
+/** Offset 0x058A - VMD Mem Bar1 Attributes
0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
**/
UINT8 VmdMemBar1Attr;
-/** Offset 0x058F - VMD Mem Bar2 size
+/** Offset 0x058B - VMD Mem Bar2 size
Set The VMD Mem Bar2 Size.
**/
UINT8 VmdMemBarSize2;
-/** Offset 0x0590 - VMD Mem Bar2 Attributes
+/** Offset 0x058C - VMD Mem Bar2 Attributes
0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH
0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
**/
UINT8 VmdMemBar2Attr;
-/** Offset 0x0591 - Reserved
+/** Offset 0x058D - Reserved
**/
- UINT8 Reserved18[3];
+ UINT8 Reserved17[3];
-/** Offset 0x0594 - VMD Variable
+/** Offset 0x0590 - VMD Variable
VMD Variable Pointer.
**/
UINT32 VmdVariablePtr;
-/** Offset 0x0598 - Temporary CfgBar address for VMD
+/** Offset 0x0594 - Temporary CfgBar address for VMD
VMD Variable Pointer.
**/
UINT32 VmdCfgBarBase;
-/** Offset 0x059C - Temporary MemBar1 address for VMD
+/** Offset 0x0598 - Temporary MemBar1 address for VMD
VMD Variable Pointer.
**/
UINT32 VmdMemBar1Base;
-/** Offset 0x05A0 - Temporary MemBar2 address for VMD
+/** Offset 0x059C - Temporary MemBar2 address for VMD
VMD Variable Pointer.
**/
UINT32 VmdMemBar2Base;
-/** Offset 0x05A4 - Reserved
+/** Offset 0x05A0 - Reserved
**/
- UINT8 Reserved19;
+ UINT8 Reserved18;
-/** Offset 0x05A5 - Enable/Disable PMC-PD Solution
+/** Offset 0x05A1 - Enable/Disable PMC-PD Solution
This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
$EN_DIS
**/
UINT8 PmcPdEnable;
-/** Offset 0x05A6 - TCSS Aux Orientation Override Enable
+/** Offset 0x05A2 - TCSS Aux Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssAuxOri;
-/** Offset 0x05A8 - TCSS HSL Orientation Override Enable
+/** Offset 0x05A4 - TCSS HSL Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssHslOri;
-/** Offset 0x05AA - USB override in IOM
+/** Offset 0x05A6 - USB override in IOM
This policy will enable/disable USB Connect override in IOM
$EN_DIS
**/
UINT8 UsbOverride;
-/** Offset 0x05AB - ITBT Root Port Enable
+/** Offset 0x05A7 - ITBT Root Port Enable
ITBT Root Port Enable, 0:Disable, 1:Enable
0:Disable, 1:Enable
**/
UINT8 ITbtPcieRootPortEn[4];
-/** Offset 0x05AF - Reserved
+/** Offset 0x05AB - Reserved
**/
- UINT8 Reserved20;
+ UINT8 Reserved19;
-/** Offset 0x05B0 - ITBTForcePowerOn Timeout value
+/** Offset 0x05AC - ITBTForcePowerOn Timeout value
ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
100 = 100 ms.
**/
UINT16 ITbtForcePowerOnTimeoutInMs;
-/** Offset 0x05B2 - ITbtConnectTopology Timeout value
+/** Offset 0x05AE - ITbtConnectTopology Timeout value
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
is 0-10000. 100 = 100 ms.
**/
UINT16 ITbtConnectTopologyTimeoutInMs;
-/** Offset 0x05B4 - VCCST request for IOM
+/** Offset 0x05B0 - VCCST request for IOM
This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
$EN_DIS
**/
UINT8 VccSt;
-/** Offset 0x05B5 - Reserved
+/** Offset 0x05B1 - Reserved
**/
- UINT8 Reserved21;
+ UINT8 Reserved20;
-/** Offset 0x05B6 - ITBT DMA LTR
+/** Offset 0x05B2 - ITBT DMA LTR
TCSS DMA1, DMA2 LTR value
**/
UINT16 ITbtDmaLtr[2];
-/** Offset 0x05BA - Reserved
+/** Offset 0x05B6 - Reserved
**/
- UINT8 Reserved22;
+ UINT8 Reserved21;
-/** Offset 0x05BB - Enable/Disable PTM
+/** Offset 0x05B7 - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
$EN_DIS
**/
UINT8 PtmEnabled[4];
-/** Offset 0x05BF - PCIE RP Ltr Enable
+/** Offset 0x05BB - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 SaPcieItbtRpLtrEnable[4];
-/** Offset 0x05C3 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x05BF - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4];
-/** Offset 0x05C7 - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x05C3 - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
-/** Offset 0x05CB - Reserved
+/** Offset 0x05C7 - Reserved
**/
- UINT8 Reserved23;
+ UINT8 Reserved22;
-/** Offset 0x05CC - PCIE RP Snoop Latency Override Value
+/** Offset 0x05C8 - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4];
-/** Offset 0x05D4 - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x05D0 - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
-/** Offset 0x05D8 - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x05D4 - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
-/** Offset 0x05DC - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x05D8 - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
-/** Offset 0x05E4 - Force LTR Override
+/** Offset 0x05E0 - Force LTR Override
Force LTR Override.
**/
UINT8 SaPcieItbtRpForceLtrOverride[4];
-/** Offset 0x05E8 - PCIE RP Ltr Config Lock
+/** Offset 0x05E4 - PCIE RP Ltr Config Lock
0: Disable; 1: Enable.
**/
UINT8 SaPcieItbtRpLtrConfigLock[4];
-/** Offset 0x05EC - Advanced Encryption Standard (AES) feature
+/** Offset 0x05E8 - Advanced Encryption Standard (AES) feature
Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
$EN_DIS
**/
UINT8 AesEnable;
-/** Offset 0x05ED - Power State 3 enable/disable
+/** Offset 0x05E9 - Power State 3 enable/disable
PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
For all VR Indexes
**/
UINT8 Psi3Enable[5];
-/** Offset 0x05F2 - Power State 4 enable/disable
+/** Offset 0x05EE - Power State 4 enable/disable
PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
all VR Indexes
**/
UINT8 Psi4Enable[5];
-/** Offset 0x05F7 - Reserved
+/** Offset 0x05F3 - Reserved
**/
- UINT8 Reserved24;
+ UINT8 Reserved23;
-/** Offset 0x05F8 - Imon slope correction
+/** Offset 0x05F4 - Imon slope correction
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
**/
UINT16 ImonSlope[5];
-/** Offset 0x0602 - Imon offset correction
+/** Offset 0x05FE - Imon offset correction
PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
**/
UINT16 ImonOffset[5];
-/** Offset 0x060C - Enable/Disable BIOS configuration of VR
+/** Offset 0x0608 - Enable/Disable BIOS configuration of VR
Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
**/
UINT8 VrConfigEnable[5];
-/** Offset 0x0611 - Thermal Design Current enable/disable
+/** Offset 0x060D - Thermal Design Current enable/disable
PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
Enable.For all VR Indexes
**/
UINT8 TdcEnable[5];
-/** Offset 0x0616 - Reserved
+/** Offset 0x0612 - Reserved
**/
- UINT8 Reserved25[2];
+ UINT8 Reserved24[2];
-/** Offset 0x0618 - Thermal Design Current time window
+/** Offset 0x0614 - Thermal Design Current time window
PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
Range 1ms to 448s
**/
UINT32 TdcTimeWindow[5];
-/** Offset 0x062C - Thermal Design Current Lock
+/** Offset 0x0628 - Thermal Design Current Lock
PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
all VR Indexes
**/
UINT8 TdcLock[5];
-/** Offset 0x0631 - Platform Psys slope correction
+/** Offset 0x062D - Platform Psys slope correction
PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
1/100 increment values. Range is 0-200. 125 = 1.25
**/
UINT8 PsysSlope;
-/** Offset 0x0632 - Platform Psys offset correction
+/** Offset 0x062E - Platform Psys offset correction
PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/1000,
Range 0-63999. For an offset of 25.348, enter 25348.
**/
UINT16 PsysOffset;
-/** Offset 0x0634 - Acoustic Noise Mitigation feature
+/** Offset 0x0630 - Acoustic Noise Mitigation feature
Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
$EN_DIS
**/
UINT8 AcousticNoiseMitigation;
-/** Offset 0x0635 - Disable Fast Slew Rate for Deep Package C States for VR domains
+/** Offset 0x0631 - Disable Fast Slew Rate for Deep Package C States for VR domains
Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
feature enabled. <b>0: False</b>; 1: True
$EN_DIS
**/
UINT8 FastPkgCRampDisable[5];
-/** Offset 0x063A - Slew Rate configuration for Deep Package C States for VR domains
+/** Offset 0x0636 - Slew Rate configuration for Deep Package C States for VR domains
Slew Rate configuration for Deep Package C States for VR domains based on Acoustic
Noise Mitigation feature enabled. ADL supports VCCIA FAST/2/4/8/16, VCCGT FAST/2/4/8
and VCCSA FAST/2 <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
@@ -1435,1017 +1431,1009 @@ typedef struct {
**/
UINT8 SlowSlewRate[5];
-/** Offset 0x063F - Reserved
+/** Offset 0x063B - Reserved
**/
- UINT8 Reserved26;
+ UINT8 Reserved25;
-/** Offset 0x0640 - Thermal Design Current current limit
+/** Offset 0x063C - Thermal Design Current current limit
PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
**/
UINT16 TdcCurrentLimit[5];
-/** Offset 0x064A - AcLoadline
+/** Offset 0x0646 - AcLoadline
PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
**/
UINT16 AcLoadline[5];
-/** Offset 0x0654 - DcLoadline
+/** Offset 0x0650 - DcLoadline
PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
**/
UINT16 DcLoadline[5];
-/** Offset 0x065E - Power State 1 Threshold current
+/** Offset 0x065A - Power State 1 Threshold current
PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
**/
UINT16 Psi1Threshold[5];
-/** Offset 0x0668 - Power State 2 Threshold current
+/** Offset 0x0664 - Power State 2 Threshold current
PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
**/
UINT16 Psi2Threshold[5];
-/** Offset 0x0672 - Power State 3 Threshold current
+/** Offset 0x066E - Power State 3 Threshold current
PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
**/
UINT16 Psi3Threshold[5];
-/** Offset 0x067C - Icc Max limit
+/** Offset 0x0678 - Icc Max limit
PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
**/
UINT16 IccMax[5];
-/** Offset 0x0686 - Enable or Disable TXT
+/** Offset 0x0682 - Enable or Disable TXT
Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 TxtEnable;
-/** Offset 0x0687 - Skip Multi-Processor Initialization
+/** Offset 0x0683 - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
API. </b>0: Initialize; <b>1: Skip
$EN_DIS
**/
UINT8 SkipMpInit;
-/** Offset 0x0688 - FIVR RFI Frequency
+/** Offset 0x0684 - FIVR RFI Frequency
PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
0-1535 (Up to 153.5MHz) for 19MHz clock.
**/
UINT16 FivrRfiFrequency;
-/** Offset 0x068A - FIVR RFI Spread Spectrum
+/** Offset 0x0686 - FIVR RFI Spread Spectrum
Set the Spread Spectrum Range. <b>1.5%</b>; Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%,
6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1%
= 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
**/
UINT8 FivrSpreadSpectrum;
-/** Offset 0x068B - Reserved
+/** Offset 0x0687 - Reserved
**/
- UINT8 Reserved27;
+ UINT8 Reserved26;
-/** Offset 0x068C - CpuBistData
+/** Offset 0x0688 - CpuBistData
Pointer CPU BIST Data
**/
UINT32 CpuBistData;
-/** Offset 0x0690 - CpuMpPpi
+/** Offset 0x068C - CpuMpPpi
<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
If not NULL, FSP will use the boot loader's implementation of multiprocessing.
See section 5.1.4 of the FSP Integration Guide for more details.
**/
UINT32 CpuMpPpi;
-/** Offset 0x0694 - Pre Wake Randomization time
+/** Offset 0x0690 - Pre Wake Randomization time
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake
randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
is enabled. Range 0-255 <b>0</b>.
**/
UINT8 PreWake;
-/** Offset 0x0695 - Ramp Up Randomization time
+/** Offset 0x0691 - Ramp Up Randomization time
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up
randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
is enabled.Range 0-255 <b>0</b>.
**/
UINT8 RampUp;
-/** Offset 0x0696 - Ramp Down Randomization time
+/** Offset 0x0692 - Ramp Down Randomization time
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down
randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation
is enabled.Range 0-255 <b>0</b>.
**/
UINT8 RampDown;
-/** Offset 0x0697 - Reserved
+/** Offset 0x0693 - Reserved
**/
- UINT8 Reserved28;
+ UINT8 Reserved27;
-/** Offset 0x0698 - VR Voltage Limit
+/** Offset 0x0694 - VR Voltage Limit
PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV
**/
UINT16 VrVoltageLimit[5];
-/** Offset 0x06A2 - Reserved
+/** Offset 0x069E - Reserved
**/
- UINT8 Reserved29[12];
+ UINT8 Reserved28[12];
-/** Offset 0x06AE - FIVR RFI Spread Spectrum Enable or disable
+/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable
Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b>
**/
UINT8 FivrSpectrumEnable;
-/** Offset 0x06AF - Reserved
+/** Offset 0x06AB - Reserved
**/
- UINT8 Reserved30[13];
+ UINT8 Reserved29[13];
-/** Offset 0x06BC - PpinSupport to view Protected Processor Inventory Number
+/** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number
Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
flag is set) for PPIN Support
0: Disable, 1: Enable, 2: Auto
**/
UINT8 PpinSupport;
-/** Offset 0x06BD - Enable or Disable Minimum Voltage Override
+/** Offset 0x06B9 - Enable or Disable Minimum Voltage Override
Enable or disable Minimum Voltage overrides ; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 EnableMinVoltageOverride;
-/** Offset 0x06BE - Min Voltage for Runtime
+/** Offset 0x06BA - Min Voltage for Runtime
PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride
= 1. Range 0 to 1999mV. <b> 0: 0mV </b>
**/
UINT16 MinVoltageRuntime;
-/** Offset 0x06C0 - Reserved
+/** Offset 0x06BC - Reserved
**/
- UINT8 Reserved31[2];
+ UINT8 Reserved30[2];
-/** Offset 0x06C2 - Min Voltage for C8
+/** Offset 0x06BE - Min Voltage for C8
PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
1. Range 0 to 1999mV. <b> 0: 0mV </b>
**/
UINT16 MinVoltageC8;
-/** Offset 0x06C4 - Smbios Type4 Max Speed Override
+/** Offset 0x06C0 - Smbios Type4 Max Speed Override
Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
If this value is not zero, it dominates the field.
**/
UINT16 SmbiosType4MaxSpeedOverride;
-/** Offset 0x06C6 - Reserved
+/** Offset 0x06C2 - Reserved
**/
- UINT8 Reserved32[5];
+ UINT8 Reserved31[5];
-/** Offset 0x06CB - AvxDisable
+/** Offset 0x06C7 - AvxDisable
Enable or Disable AVX Support. This only applicable when all small core is disabled.
0: Enable, 1: Disable
**/
UINT8 AvxDisable;
-/** Offset 0x06CC - Avx3Disable
+/** Offset 0x06C8 - Avx3Disable
Enable or Disable AVX3 Support
0: Enable, 1: Disable
**/
UINT8 Avx3Disable;
-/** Offset 0x06CD - Reserved
+/** Offset 0x06C9 - Reserved
**/
- UINT8 Reserved33;
+ UINT8 Reserved32;
-/** Offset 0x06CE - CPU VR Power Delivery Design
+/** Offset 0x06CA - CPU VR Power Delivery Design
Used to communicate the power delivery design capability of the board. This value
is an enum of the available power delivery segments that are defined in the Platform
Design Guide.
**/
UINT8 VrPowerDeliveryDesign;
-/** Offset 0x06CF - Reserved
+/** Offset 0x06CB - Reserved
**/
- UINT8 Reserved34;
+ UINT8 Reserved33[32];
-/** Offset 0x06D0 - Enable Power Optimizer
+/** Offset 0x06EB - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 PchPwrOptEnable;
-/** Offset 0x06D1 - PCH Flash Protection Ranges Write Enble
+/** Offset 0x06EC - PCH Flash Protection Ranges Write Enble
Write or erase is blocked by hardware.
**/
UINT8 PchWriteProtectionEnable[5];
-/** Offset 0x06D6 - PCH Flash Protection Ranges Read Enble
+/** Offset 0x06F1 - PCH Flash Protection Ranges Read Enble
Read is blocked by hardware.
**/
UINT8 PchReadProtectionEnable[5];
-/** Offset 0x06DB - Reserved
-**/
- UINT8 Reserved35;
-
-/** Offset 0x06DC - PCH Protect Range Limit
+/** Offset 0x06F6 - PCH Protect Range Limit
Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
limit comparison.
**/
UINT16 PchProtectedRangeLimit[5];
-/** Offset 0x06E6 - PCH Protect Range Base
+/** Offset 0x0700 - PCH Protect Range Base
Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
UINT16 PchProtectedRangeBase[5];
-/** Offset 0x06F0 - Enable Pme
+/** Offset 0x070A - Enable Pme
Enable Azalia wake-on-ring.
$EN_DIS
**/
UINT8 PchHdaPme;
-/** Offset 0x06F1 - HD Audio Link Frequency
+/** Offset 0x070B - HD Audio Link Frequency
HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
0: 6MHz, 1: 12MHz, 2: 24MHz
**/
UINT8 PchHdaLinkFrequency;
-/** Offset 0x06F2 - Enable PCH ISH SPI Cs0 pins assigned
+/** Offset 0x070C - Enable PCH ISH SPI Cs0 pins assigned
Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiCs0Enable[1];
-/** Offset 0x06F3 - Enable PCH Io Apic Entry 24-119
+/** Offset 0x070D - Enable PCH Io Apic Entry 24-119
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIoApicEntry24_119;
-/** Offset 0x06F4 - PCH Io Apic ID
+/** Offset 0x070E - PCH Io Apic ID
This member determines IOAPIC ID. Default is 0x02.
**/
UINT8 PchIoApicId;
-/** Offset 0x06F5 - Enable PCH ISH SPI pins assigned
+/** Offset 0x070F - Enable PCH ISH SPI pins assigned
Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiEnable[1];
-/** Offset 0x06F6 - Enable PCH ISH UART pins assigned
+/** Offset 0x0710 - Enable PCH ISH UART pins assigned
Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshUartEnable[2];
-/** Offset 0x06F8 - Enable PCH ISH I2C pins assigned
+/** Offset 0x0712 - Enable PCH ISH I2C pins assigned
Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshI2cEnable[3];
-/** Offset 0x06FB - Enable PCH ISH GP pins assigned
+/** Offset 0x0715 - Enable PCH ISH GP pins assigned
Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshGpEnable[8];
-/** Offset 0x0703 - PCH ISH PDT Unlock Msg
+/** Offset 0x071D - PCH ISH PDT Unlock Msg
0: False; 1: True.
$EN_DIS
**/
UINT8 PchIshPdtUnlock;
-/** Offset 0x0704 - Enable PCH Lan LTR capabilty of PCH internal LAN
+/** Offset 0x071E - Enable PCH Lan LTR capabilty of PCH internal LAN
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchLanLtrEnable;
-/** Offset 0x0705 - Enable LOCKDOWN BIOS LOCK
+/** Offset 0x071F - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
protection.
$EN_DIS
**/
UINT8 PchLockDownBiosLock;
-/** Offset 0x0706 - PCH Compatibility Revision ID
+/** Offset 0x0720 - PCH Compatibility Revision ID
This member describes whether or not the CRID feature of PCH should be enabled.
$EN_DIS
**/
UINT8 PchCrid;
-/** Offset 0x0707 - RTC BIOS Interface Lock
+/** Offset 0x0721 - RTC BIOS Interface Lock
Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
$EN_DIS
**/
UINT8 RtcBiosInterfaceLock;
-/** Offset 0x0708 - RTC Cmos Memory Lock
+/** Offset 0x0722 - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
and and lower 128-byte bank of RTC RAM.
$EN_DIS
**/
UINT8 RtcMemoryLock;
-/** Offset 0x0709 - Enable PCIE RP HotPlug
+/** Offset 0x0723 - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
**/
UINT8 PcieRpHotPlug[28];
-/** Offset 0x0725 - Enable PCIE RP Pm Sci
+/** Offset 0x073F - Enable PCIE RP Pm Sci
Indicate whether the root port power manager SCI is enabled.
**/
UINT8 PcieRpPmSci[28];
-/** Offset 0x0741 - Enable PCIE RP Transmitter Half Swing
+/** Offset 0x075B - Enable PCIE RP Transmitter Half Swing
Indicate whether the Transmitter Half Swing is enabled.
**/
UINT8 PcieRpTransmitterHalfSwing[28];
-/** Offset 0x075D - Enable PCIE RP Clk Req Detect
+/** Offset 0x0777 - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
UINT8 PcieRpClkReqDetect[28];
-/** Offset 0x0779 - PCIE RP Advanced Error Report
+/** Offset 0x0793 - PCIE RP Advanced Error Report
Indicate whether the Advanced Error Reporting is enabled.
**/
UINT8 PcieRpAdvancedErrorReporting[28];
-/** Offset 0x0795 - PCIE RP Unsupported Request Report
+/** Offset 0x07AF - PCIE RP Unsupported Request Report
Indicate whether the Unsupported Request Report is enabled.
**/
UINT8 PcieRpUnsupportedRequestReport[28];
-/** Offset 0x07B1 - PCIE RP Fatal Error Report
+/** Offset 0x07CB - PCIE RP Fatal Error Report
Indicate whether the Fatal Error Report is enabled.
**/
UINT8 PcieRpFatalErrorReport[28];
-/** Offset 0x07CD - PCIE RP No Fatal Error Report
+/** Offset 0x07E7 - PCIE RP No Fatal Error Report
Indicate whether the No Fatal Error Report is enabled.
**/
UINT8 PcieRpNoFatalErrorReport[28];
-/** Offset 0x07E9 - PCIE RP Correctable Error Report
+/** Offset 0x0803 - PCIE RP Correctable Error Report
Indicate whether the Correctable Error Report is enabled.
**/
UINT8 PcieRpCorrectableErrorReport[28];
-/** Offset 0x0805 - PCIE RP System Error On Fatal Error
+/** Offset 0x081F - PCIE RP System Error On Fatal Error
Indicate whether the System Error on Fatal Error is enabled.
**/
UINT8 PcieRpSystemErrorOnFatalError[28];
-/** Offset 0x0821 - PCIE RP System Error On Non Fatal Error
+/** Offset 0x083B - PCIE RP System Error On Non Fatal Error
Indicate whether the System Error on Non Fatal Error is enabled.
**/
UINT8 PcieRpSystemErrorOnNonFatalError[28];
-/** Offset 0x083D - PCIE RP System Error On Correctable Error
+/** Offset 0x0857 - PCIE RP System Error On Correctable Error
Indicate whether the System Error on Correctable Error is enabled.
**/
UINT8 PcieRpSystemErrorOnCorrectableError[28];
-/** Offset 0x0859 - PCIE RP Max Payload
+/** Offset 0x0873 - PCIE RP Max Payload
Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
**/
UINT8 PcieRpMaxPayload[28];
-/** Offset 0x0875 - Touch Host Controller Port 0 Assignment
+/** Offset 0x088F - Touch Host Controller Port 0 Assignment
Assign THC Port 0
0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
**/
UINT8 ThcPort0Assignment;
-/** Offset 0x0876 - Reserved
-**/
- UINT8 Reserved36[2];
-
-/** Offset 0x0878 - Touch Host Controller Port 0 Interrupt Pin Mux
+/** Offset 0x0890 - Touch Host Controller Port 0 Interrupt Pin Mux
Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer
to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values.
**/
UINT32 ThcPort0InterruptPinMuxing;
-/** Offset 0x087C - Reserved
+/** Offset 0x0894 - Reserved
**/
- UINT8 Reserved37;
+ UINT8 Reserved34;
-/** Offset 0x087D - Touch Host Controller Port 1 Assignment
+/** Offset 0x0895 - Touch Host Controller Port 1 Assignment
Assign THC Port 1
0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
**/
UINT8 ThcPort1Assignment;
-/** Offset 0x087E - Reserved
+/** Offset 0x0896 - Reserved
**/
- UINT8 Reserved38[2];
+ UINT8 Reserved35[2];
-/** Offset 0x0880 - Touch Host Controller Port 1 Interrupt Pin Mux
+/** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux
Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values.
**/
UINT32 ThcPort1InterruptPinMuxing;
-/** Offset 0x0884 - Reserved
+/** Offset 0x089C - Reserved
**/
- UINT8 Reserved39;
+ UINT8 Reserved36;
-/** Offset 0x0885 - PCIE RP Pcie Speed
+/** Offset 0x089D - PCIE RP Pcie Speed
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
4: Gen4 (see: PCIE_SPEED).
**/
UINT8 PcieRpPcieSpeed[28];
-/** Offset 0x08A1 - PCIE RP Physical Slot Number
+/** Offset 0x08B9 - PCIE RP Physical Slot Number
Indicates the slot number for the root port. Default is the value as root port index.
**/
UINT8 PcieRpPhysicalSlotNumber[28];
-/** Offset 0x08BD - PCIE RP Completion Timeout
+/** Offset 0x08D5 - PCIE RP Completion Timeout
The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
**/
UINT8 PcieRpCompletionTimeout[28];
-/** Offset 0x08D9 - PCIE RP Aspm
+/** Offset 0x08F1 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
PchPcieAspmAutoConfig.
**/
UINT8 PcieRpAspm[28];
-/** Offset 0x08F5 - PCIE RP L1 Substates
+/** Offset 0x090D - PCIE RP L1 Substates
The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
Default is PchPcieL1SubstatesL1_1_2.
**/
UINT8 PcieRpL1Substates[28];
-/** Offset 0x0911 - Reserved
+/** Offset 0x0929 - Reserved
**/
- UINT8 Reserved40[28];
+ UINT8 Reserved37[28];
-/** Offset 0x092D - PCIE RP Ltr Enable
+/** Offset 0x0945 - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 PcieRpLtrEnable[28];
-/** Offset 0x0949 - PCIE RP Ltr Config Lock
+/** Offset 0x0961 - PCIE RP Ltr Config Lock
0: Disable; 1: Enable.
**/
UINT8 PcieRpLtrConfigLock[28];
-/** Offset 0x0965 - PCIe override default settings for EQ
+/** Offset 0x097D - PCIe override default settings for EQ
Choose PCIe EQ method
$EN_DIS
**/
UINT8 PcieEqOverrideDefault;
-/** Offset 0x0966 - PCIe choose EQ method
+/** Offset 0x097E - PCIe choose EQ method
Choose PCIe EQ method
0: HardwareEq, 1: FixedEq
**/
UINT8 PcieEqMethod;
-/** Offset 0x0967 - PCIe choose EQ mode
+/** Offset 0x097F - PCIe choose EQ mode
Choose PCIe EQ mode
0: PresetEq, 1: CoefficientEq
**/
UINT8 PcieEqMode;
-/** Offset 0x0968 - PCIe EQ local transmitter override
+/** Offset 0x0980 - PCIe EQ local transmitter override
Enable/Disable local transmitter override
$EN_DIS
**/
UINT8 PcieEqLocalTransmitterOverrideEnable;
-/** Offset 0x0969 - PCIe number of valid list entries
+/** Offset 0x0981 - PCIe number of valid list entries
Select number of presets or coefficients depending on the mode
**/
UINT8 PcieEqPh3NumberOfPresetsOrCoefficients;
-/** Offset 0x096A - PCIe pre-cursor coefficient list
+/** Offset 0x0982 - PCIe pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieEqPh3PreCursorList[10];
-/** Offset 0x0974 - PCIe post-cursor coefficient list
+/** Offset 0x098C - PCIe post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieEqPh3PostCursorList[10];
-/** Offset 0x097E - PCIe preset list
+/** Offset 0x0996 - PCIe preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieEqPh3PresetList[11];
-/** Offset 0x0989 - Reserved
+/** Offset 0x09A1 - Reserved
**/
- UINT8 Reserved41[3];
+ UINT8 Reserved38[3];
-/** Offset 0x098C - PCIe EQ phase 1 downstream transmitter port preset
+/** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset
Allows to select the downstream port preset value that will be used during phase
1 of equalization
**/
UINT32 PcieEqPh1DownstreamPortTransmitterPreset;
-/** Offset 0x0990 - PCIe EQ phase 1 upstream tranmitter port preset
+/** Offset 0x09A8 - PCIe EQ phase 1 upstream tranmitter port preset
Allows to select the upstream port preset value that will be used during phase 1
of equalization
**/
UINT32 PcieEqPh1UpstreamPortTransmitterPreset;
-/** Offset 0x0994 - PCIe EQ phase 2 local transmitter override preset
+/** Offset 0x09AC - PCIe EQ phase 2 local transmitter override preset
Allows to select the value of the preset used during phase 2 local transmitter override
**/
UINT8 PcieEqPh2LocalTransmitterOverridePreset;
-/** Offset 0x0995 - PCIE Enable Peer Memory Write
+/** Offset 0x09AD - PCIE Enable Peer Memory Write
This member describes whether Peer Memory Writes are enabled on the platform.
$EN_DIS
**/
UINT8 PcieEnablePeerMemoryWrite[28];
-/** Offset 0x09B1 - PCIE Compliance Test Mode
+/** Offset 0x09C9 - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 PcieComplianceTestMode;
-/** Offset 0x09B2 - PCIE Rp Function Swap
+/** Offset 0x09CA - PCIE Rp Function Swap
Allows BIOS to use root port function number swapping when root port of function
0 is disabled.
$EN_DIS
**/
UINT8 PcieRpFunctionSwap;
-/** Offset 0x09B3 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
+/** Offset 0x09CB - Enable/Disable PEG GEN3 Static EQ Phase1 programming
Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets
Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 CpuPcieGen3ProgramStaticEq;
-/** Offset 0x09B4 - Enable/Disable GEN4 Static EQ Phase1 programming
+/** Offset 0x09CC - Enable/Disable GEN4 Static EQ Phase1 programming
Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets
Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 CpuPcieGen4ProgramStaticEq;
-/** Offset 0x09B5 - PCH Pm PME_B0_S5_DIS
+/** Offset 0x09CD - PCH Pm PME_B0_S5_DIS
When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
$EN_DIS
**/
UINT8 PchPmPmeB0S5Dis;
-/** Offset 0x09B6 - PCIE IMR
+/** Offset 0x09CE - PCIE IMR
Enables Isolated Memory Region for PCIe.
$EN_DIS
**/
UINT8 PcieRpImrEnabled;
-/** Offset 0x09B7 - PCIE IMR port number
+/** Offset 0x09CF - PCIE IMR port number
Selects PCIE root port number for IMR feature.
**/
UINT8 PcieRpImrSelection;
-/** Offset 0x09B8 - PCH Pm Wol Enable Override
+/** Offset 0x09D0 - PCH Pm Wol Enable Override
Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
$EN_DIS
**/
UINT8 PchPmWolEnableOverride;
-/** Offset 0x09B9 - PCH Pm Pcie Wake From DeepSx
+/** Offset 0x09D1 - PCH Pm Pcie Wake From DeepSx
Determine if enable PCIe to wake from deep Sx.
$EN_DIS
**/
UINT8 PchPmPcieWakeFromDeepSx;
-/** Offset 0x09BA - PCH Pm WoW lan Enable
+/** Offset 0x09D2 - PCH Pm WoW lan Enable
Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
$EN_DIS
**/
UINT8 PchPmWoWlanEnable;
-/** Offset 0x09BB - PCH Pm WoW lan DeepSx Enable
+/** Offset 0x09D3 - PCH Pm WoW lan DeepSx Enable
Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
PWRM_CFG3 register.
$EN_DIS
**/
UINT8 PchPmWoWlanDeepSxEnable;
-/** Offset 0x09BC - PCH Pm Lan Wake From DeepSx
+/** Offset 0x09D4 - PCH Pm Lan Wake From DeepSx
Determine if enable LAN to wake from deep Sx.
$EN_DIS
**/
UINT8 PchPmLanWakeFromDeepSx;
-/** Offset 0x09BD - PCH Pm Deep Sx Pol
+/** Offset 0x09D5 - PCH Pm Deep Sx Pol
Deep Sx Policy.
$EN_DIS
**/
UINT8 PchPmDeepSxPol;
-/** Offset 0x09BE - PCH Pm Slp S3 Min Assert
+/** Offset 0x09D6 - PCH Pm Slp S3 Min Assert
SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
**/
UINT8 PchPmSlpS3MinAssert;
-/** Offset 0x09BF - PCH Pm Slp S4 Min Assert
+/** Offset 0x09D7 - PCH Pm Slp S4 Min Assert
SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
**/
UINT8 PchPmSlpS4MinAssert;
-/** Offset 0x09C0 - PCH Pm Slp Sus Min Assert
+/** Offset 0x09D8 - PCH Pm Slp Sus Min Assert
SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
**/
UINT8 PchPmSlpSusMinAssert;
-/** Offset 0x09C1 - PCH Pm Slp A Min Assert
+/** Offset 0x09D9 - PCH Pm Slp A Min Assert
SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
**/
UINT8 PchPmSlpAMinAssert;
-/** Offset 0x09C2 - USB Overcurrent Override for VISA
+/** Offset 0x09DA - USB Overcurrent Override for VISA
This option overrides USB Over Current enablement state that USB OC will be disabled
after enabling this option. Enable when VISA pin is muxed with USB OC
$EN_DIS
**/
UINT8 PchEnableDbcObs;
-/** Offset 0x09C3 - PCH Pm Slp Strch Sus Up
+/** Offset 0x09DB - PCH Pm Slp Strch Sus Up
Enable SLP_X Stretching After SUS Well Power Up.
$EN_DIS
**/
UINT8 PchPmSlpStrchSusUp;
-/** Offset 0x09C4 - PCH Pm Slp Lan Low Dc
+/** Offset 0x09DC - PCH Pm Slp Lan Low Dc
Enable/Disable SLP_LAN# Low on DC Power.
$EN_DIS
**/
UINT8 PchPmSlpLanLowDc;
-/** Offset 0x09C5 - PCH Pm Pwr Btn Override Period
+/** Offset 0x09DD - PCH Pm Pwr Btn Override Period
PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
**/
UINT8 PchPmPwrBtnOverridePeriod;
-/** Offset 0x09C6 - PCH Pm Disable Dsx Ac Present Pulldown
+/** Offset 0x09DE - PCH Pm Disable Dsx Ac Present Pulldown
When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
$EN_DIS
**/
UINT8 PchPmDisableDsxAcPresentPulldown;
-/** Offset 0x09C7 - PCH Pm Disable Native Power Button
+/** Offset 0x09DF - PCH Pm Disable Native Power Button
Power button native mode disable.
$EN_DIS
**/
UINT8 PchPmDisableNativePowerButton;
-/** Offset 0x09C8 - PCH Pm ME_WAKE_STS
+/** Offset 0x09E0 - PCH Pm ME_WAKE_STS
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmMeWakeSts;
-/** Offset 0x09C9 - PCH Pm WOL_OVR_WK_STS
+/** Offset 0x09E1 - PCH Pm WOL_OVR_WK_STS
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmWolOvrWkSts;
-/** Offset 0x09CA - PCH Pm Reset Power Cycle Duration
+/** Offset 0x09E2 - PCH Pm Reset Power Cycle Duration
Could be customized in the unit of second. Please refer to EDS for all support settings.
0 is default, 1 is 1 second, 2 is 2 seconds, ...
**/
UINT8 PchPmPwrCycDur;
-/** Offset 0x09CB - PCH Pm Pcie Pll Ssc
+/** Offset 0x09E3 - PCH Pm Pcie Pll Ssc
Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
BIOS override.
**/
UINT8 PchPmPciePllSsc;
-/** Offset 0x09CC - PCH Legacy IO Low Latency Enable
+/** Offset 0x09E4 - PCH Legacy IO Low Latency Enable
Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
$EN_DIS
**/
UINT8 PchLegacyIoLowLatency;
-/** Offset 0x09CD - PCH Sata Pwr Opt Enable
+/** Offset 0x09E5 - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
-/** Offset 0x09CE - PCH Sata eSATA Speed Limit
+/** Offset 0x09E6 - PCH Sata eSATA Speed Limit
When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
$EN_DIS
**/
UINT8 EsataSpeedLimit;
-/** Offset 0x09CF - PCH Sata Speed Limit
+/** Offset 0x09E7 - PCH Sata Speed Limit
Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
**/
UINT8 SataSpeedLimit;
-/** Offset 0x09D0 - Enable SATA Port HotPlug
+/** Offset 0x09E8 - Enable SATA Port HotPlug
Enable SATA Port HotPlug.
**/
UINT8 SataPortsHotPlug[8];
-/** Offset 0x09D8 - Enable SATA Port Interlock Sw
+/** Offset 0x09F0 - Enable SATA Port Interlock Sw
Enable SATA Port Interlock Sw.
**/
UINT8 SataPortsInterlockSw[8];
-/** Offset 0x09E0 - Enable SATA Port External
+/** Offset 0x09F8 - Enable SATA Port External
Enable SATA Port External.
**/
UINT8 SataPortsExternal[8];
-/** Offset 0x09E8 - Enable SATA Port SpinUp
+/** Offset 0x0A00 - Enable SATA Port SpinUp
Enable the COMRESET initialization Sequence to the device.
**/
UINT8 SataPortsSpinUp[8];
-/** Offset 0x09F0 - Enable SATA Port Solid State Drive
+/** Offset 0x0A08 - Enable SATA Port Solid State Drive
0: HDD; 1: SSD.
**/
UINT8 SataPortsSolidStateDrive[8];
-/** Offset 0x09F8 - Enable SATA Port Enable Dito Config
+/** Offset 0x0A10 - Enable SATA Port Enable Dito Config
Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
**/
UINT8 SataPortsEnableDitoConfig[8];
-/** Offset 0x0A00 - Enable SATA Port DmVal
+/** Offset 0x0A18 - Enable SATA Port DmVal
DITO multiplier. Default is 15.
**/
UINT8 SataPortsDmVal[8];
-/** Offset 0x0A08 - Enable SATA Port DmVal
+/** Offset 0x0A20 - Enable SATA Port DmVal
DEVSLP Idle Timeout (DITO), Default is 625.
**/
UINT16 SataPortsDitoVal[8];
-/** Offset 0x0A18 - Enable SATA Port ZpOdd
+/** Offset 0x0A30 - Enable SATA Port ZpOdd
Support zero power ODD.
**/
UINT8 SataPortsZpOdd[8];
-/** Offset 0x0A20 - PCH Sata Rst Raid Alternate Id
+/** Offset 0x0A38 - PCH Sata Rst Raid Alternate Id
Enable RAID Alternate ID.
$EN_DIS
**/
UINT8 SataRstRaidDeviceId;
-/** Offset 0x0A21 - PCH Sata Rst Pcie Storage Remap enable
+/** Offset 0x0A39 - PCH Sata Rst Pcie Storage Remap enable
Enable Intel RST for PCIe Storage remapping.
**/
UINT8 SataRstPcieEnable[3];
-/** Offset 0x0A24 - PCH Sata Rst Pcie Storage Port
+/** Offset 0x0A3C - PCH Sata Rst Pcie Storage Port
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
**/
UINT8 SataRstPcieStoragePort[3];
-/** Offset 0x0A27 - PCH Sata Rst Pcie Device Reset Delay
+/** Offset 0x0A3F - PCH Sata Rst Pcie Device Reset Delay
PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
**/
UINT8 SataRstPcieDeviceResetDelay[3];
-/** Offset 0x0A2A - UFS enable/disable
+/** Offset 0x0A42 - UFS enable/disable
PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
$EN_DIS
**/
UINT8 UfsEnable[2];
-/** Offset 0x0A2C - IEH Mode
+/** Offset 0x0A44 - IEH Mode
Integrated Error Handler Mode, 0: Bypass, 1: Enable
0: Bypass, 1:Enable
**/
UINT8 IehMode;
-/** Offset 0x0A2D - Reserved
+/** Offset 0x0A45 - Reserved
**/
- UINT8 Reserved42;
+ UINT8 Reserved39;
-/** Offset 0x0A2E - Thermal Throttling Custimized T0Level Value
+/** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value
Custimized T0Level value.
**/
UINT16 PchT0Level;
-/** Offset 0x0A30 - Thermal Throttling Custimized T1Level Value
+/** Offset 0x0A48 - Thermal Throttling Custimized T1Level Value
Custimized T1Level value.
**/
UINT16 PchT1Level;
-/** Offset 0x0A32 - Thermal Throttling Custimized T2Level Value
+/** Offset 0x0A4A - Thermal Throttling Custimized T2Level Value
Custimized T2Level value.
**/
UINT16 PchT2Level;
-/** Offset 0x0A34 - Enable The Thermal Throttle
+/** Offset 0x0A4C - Enable The Thermal Throttle
Enable the thermal throttle function.
$EN_DIS
**/
UINT8 PchTTEnable;
-/** Offset 0x0A35 - PMSync State 13
+/** Offset 0x0A4D - PMSync State 13
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
at least T2 state.
$EN_DIS
**/
UINT8 PchTTState13Enable;
-/** Offset 0x0A36 - Thermal Throttle Lock
+/** Offset 0x0A4E - Thermal Throttle Lock
Thermal Throttle Lock.
$EN_DIS
**/
UINT8 PchTTLock;
-/** Offset 0x0A37 - Thermal Throttling Suggested Setting
+/** Offset 0x0A4F - Thermal Throttling Suggested Setting
Thermal Throttling Suggested Setting.
$EN_DIS
**/
UINT8 TTSuggestedSetting;
-/** Offset 0x0A38 - Enable PCH Cross Throttling
+/** Offset 0x0A50 - Enable PCH Cross Throttling
Enable/Disable PCH Cross Throttling
$EN_DIS
**/
UINT8 TTCrossThrottling;
-/** Offset 0x0A39 - DMI Thermal Sensor Autonomous Width Enable
+/** Offset 0x0A51 - DMI Thermal Sensor Autonomous Width Enable
DMI Thermal Sensor Autonomous Width Enable.
$EN_DIS
**/
UINT8 PchDmiTsawEn;
-/** Offset 0x0A3A - DMI Thermal Sensor Suggested Setting
+/** Offset 0x0A52 - DMI Thermal Sensor Suggested Setting
DMT thermal sensor suggested representative values.
$EN_DIS
**/
UINT8 DmiSuggestedSetting;
-/** Offset 0x0A3B - Thermal Sensor 0 Target Width
+/** Offset 0x0A53 - Thermal Sensor 0 Target Width
Thermal Sensor 0 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS0TW;
-/** Offset 0x0A3C - Thermal Sensor 1 Target Width
+/** Offset 0x0A54 - Thermal Sensor 1 Target Width
Thermal Sensor 1 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS1TW;
-/** Offset 0x0A3D - Thermal Sensor 2 Target Width
+/** Offset 0x0A55 - Thermal Sensor 2 Target Width
Thermal Sensor 2 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS2TW;
-/** Offset 0x0A3E - Thermal Sensor 3 Target Width
+/** Offset 0x0A56 - Thermal Sensor 3 Target Width
Thermal Sensor 3 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS3TW;
-/** Offset 0x0A3F - Port 0 T1 Multipler
+/** Offset 0x0A57 - Port 0 T1 Multipler
Port 0 T1 Multipler.
**/
UINT8 SataP0T1M;
-/** Offset 0x0A40 - Port 0 T2 Multipler
+/** Offset 0x0A58 - Port 0 T2 Multipler
Port 0 T2 Multipler.
**/
UINT8 SataP0T2M;
-/** Offset 0x0A41 - Port 0 T3 Multipler
+/** Offset 0x0A59 - Port 0 T3 Multipler
Port 0 T3 Multipler.
**/
UINT8 SataP0T3M;
-/** Offset 0x0A42 - Port 0 Tdispatch
+/** Offset 0x0A5A - Port 0 Tdispatch
Port 0 Tdispatch.
**/
UINT8 SataP0TDisp;
-/** Offset 0x0A43 - Port 1 T1 Multipler
+/** Offset 0x0A5B - Port 1 T1 Multipler
Port 1 T1 Multipler.
**/
UINT8 SataP1T1M;
-/** Offset 0x0A44 - Port 1 T2 Multipler
+/** Offset 0x0A5C - Port 1 T2 Multipler
Port 1 T2 Multipler.
**/
UINT8 SataP1T2M;
-/** Offset 0x0A45 - Port 1 T3 Multipler
+/** Offset 0x0A5D - Port 1 T3 Multipler
Port 1 T3 Multipler.
**/
UINT8 SataP1T3M;
-/** Offset 0x0A46 - Port 1 Tdispatch
+/** Offset 0x0A5E - Port 1 Tdispatch
Port 1 Tdispatch.
**/
UINT8 SataP1TDisp;
-/** Offset 0x0A47 - Port 0 Tinactive
+/** Offset 0x0A5F - Port 0 Tinactive
Port 0 Tinactive.
**/
UINT8 SataP0Tinact;
-/** Offset 0x0A48 - Port 0 Alternate Fast Init Tdispatch
+/** Offset 0x0A60 - Port 0 Alternate Fast Init Tdispatch
Port 0 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP0TDispFinit;
-/** Offset 0x0A49 - Port 1 Tinactive
+/** Offset 0x0A61 - Port 1 Tinactive
Port 1 Tinactive.
**/
UINT8 SataP1Tinact;
-/** Offset 0x0A4A - Port 1 Alternate Fast Init Tdispatch
+/** Offset 0x0A62 - Port 1 Alternate Fast Init Tdispatch
Port 1 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP1TDispFinit;
-/** Offset 0x0A4B - Sata Thermal Throttling Suggested Setting
+/** Offset 0x0A63 - Sata Thermal Throttling Suggested Setting
Sata Thermal Throttling Suggested Setting.
$EN_DIS
**/
UINT8 SataThermalSuggestedSetting;
-/** Offset 0x0A4C - Enable Memory Thermal Throttling
+/** Offset 0x0A64 - Enable Memory Thermal Throttling
Enable Memory Thermal Throttling.
$EN_DIS
**/
UINT8 PchMemoryThrottlingEnable;
-/** Offset 0x0A4D - Memory Thermal Throttling
+/** Offset 0x0A65 - Memory Thermal Throttling
Enable Memory Thermal Throttling.
**/
UINT8 PchMemoryPmsyncEnable[2];
-/** Offset 0x0A4F - Enable Memory Thermal Throttling
+/** Offset 0x0A67 - Enable Memory Thermal Throttling
Enable Memory Thermal Throttling.
**/
UINT8 PchMemoryC0TransmitEnable[2];
-/** Offset 0x0A51 - Enable Memory Thermal Throttling
+/** Offset 0x0A69 - Enable Memory Thermal Throttling
Enable Memory Thermal Throttling.
**/
UINT8 PchMemoryPinSelection[2];
-/** Offset 0x0A53 - Reserved
+/** Offset 0x0A6B - Reserved
**/
- UINT8 Reserved43;
+ UINT8 Reserved40;
-/** Offset 0x0A54 - Thermal Device Temperature
+/** Offset 0x0A6C - Thermal Device Temperature
Decides the temperature.
**/
UINT16 PchTemperatureHotLevel;
-/** Offset 0x0A56 - USB2 Port Over Current Pin
+/** Offset 0x0A6E - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
-/** Offset 0x0A66 - USB3 Port Over Current Pin
+/** Offset 0x0A7E - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
-/** Offset 0x0A70 - Enable xHCI LTR override
+/** Offset 0x0A88 - Enable xHCI LTR override
Enables override of recommended LTR values for xHCI
$EN_DIS
**/
UINT8 PchUsbLtrOverrideEnable;
-/** Offset 0x0A71 - Reserved
+/** Offset 0x0A89 - Reserved
**/
- UINT8 Reserved44[3];
+ UINT8 Reserved41[3];
-/** Offset 0x0A74 - xHCI High Idle Time LTR override
+/** Offset 0x0A8C - xHCI High Idle Time LTR override
Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
**/
UINT32 PchUsbLtrHighIdleTimeOverride;
-/** Offset 0x0A78 - xHCI Medium Idle Time LTR override
+/** Offset 0x0A90 - xHCI Medium Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
**/
UINT32 PchUsbLtrMediumIdleTimeOverride;
-/** Offset 0x0A7C - xHCI Low Idle Time LTR override
+/** Offset 0x0A94 - xHCI Low Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
**/
UINT32 PchUsbLtrLowIdleTimeOverride;
-/** Offset 0x0A80 - Enable 8254 Static Clock Gating
+/** Offset 0x0A98 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -2453,7 +2441,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGating;
-/** Offset 0x0A81 - Enable 8254 Static Clock Gating On S3
+/** Offset 0x0A99 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
@@ -2461,7 +2449,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGatingOnS3;
-/** Offset 0x0A82 - Enable TCO timer.
+/** Offset 0x0A9A - Enable TCO timer.
When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
emulation must be enabled, and WDAT table must not be exposed to the OS.
@@ -2469,101 +2457,101 @@ typedef struct {
**/
UINT8 EnableTcoTimer;
-/** Offset 0x0A83 - Hybrid Storage Detection and Configuration Mode
+/** Offset 0x0A9B - Hybrid Storage Detection and Configuration Mode
Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
Default is 0: Disabled
0: Disabled, 1: Dynamic Configuration
**/
UINT8 HybridStorageMode;
-/** Offset 0x0A84 - Reserved
+/** Offset 0x0A9C - Reserved
**/
- UINT8 Reserved45[4];
+ UINT8 Reserved42[4];
-/** Offset 0x0A88 - BgpdtHash[4]
+/** Offset 0x0AA0 - BgpdtHash[4]
BgpdtHash values
**/
UINT64 BgpdtHash[4];
-/** Offset 0x0AA8 - BiosGuardAttr
+/** Offset 0x0AC0 - BiosGuardAttr
BiosGuardAttr default values
**/
UINT32 BiosGuardAttr;
-/** Offset 0x0AAC - Reserved
+/** Offset 0x0AC4 - Reserved
**/
- UINT8 Reserved46[4];
+ UINT8 Reserved43[4];
-/** Offset 0x0AB0 - BiosGuardModulePtr
+/** Offset 0x0AC8 - BiosGuardModulePtr
BiosGuardModulePtr default values
**/
UINT64 BiosGuardModulePtr;
-/** Offset 0x0AB8 - SendEcCmd
+/** Offset 0x0AD0 - SendEcCmd
SendEcCmd function pointer. \n
@code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
**/
UINT64 SendEcCmd;
-/** Offset 0x0AC0 - EcCmdProvisionEav
+/** Offset 0x0AD8 - EcCmdProvisionEav
Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
**/
UINT8 EcCmdProvisionEav;
-/** Offset 0x0AC1 - EcCmdLock
+/** Offset 0x0AD9 - EcCmdLock
EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
**/
UINT8 EcCmdLock;
-/** Offset 0x0AC2 - Skip Ssid Programming.
+/** Offset 0x0ADA - Skip Ssid Programming.
When set to TRUE, silicon code will not do any SSID programming and platform code
needs to handle that by itself properly.
$EN_DIS
**/
UINT8 SiSkipSsidProgramming;
-/** Offset 0x0AC3 - Reserved
+/** Offset 0x0ADB - Reserved
**/
- UINT8 Reserved47;
+ UINT8 Reserved44;
-/** Offset 0x0AC4 - Change Default SVID
+/** Offset 0x0ADC - Change Default SVID
Change the default SVID used in FSP to programming internal devices. This is only
valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiCustomizedSvid;
-/** Offset 0x0AC6 - Change Default SSID
+/** Offset 0x0ADE - Change Default SSID
Change the default SSID used in FSP to programming internal devices. This is only
valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiCustomizedSsid;
-/** Offset 0x0AC8 - SVID SDID table Poniter.
+/** Offset 0x0AE0 - SVID SDID table Poniter.
The address of the table of SVID SDID to customize each SVID SDID entry. This is
only valid when SkipSsidProgramming is FALSE.
**/
UINT32 SiSsidTablePtr;
-/** Offset 0x0ACC - Number of ssid table.
+/** Offset 0x0AE4 - Number of ssid table.
SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
This is only valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiNumberOfSsidTableEntry;
-/** Offset 0x0ACE - USB2 Port Reset Message Enable
+/** Offset 0x0AE6 - USB2 Port Reset Message Enable
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
be enable for USB2 Port those are paired with CPU XHCI Port
**/
UINT8 PortResetMessageEnable[16];
-/** Offset 0x0ADE - SATA RST Interrupt Mode
+/** Offset 0x0AF6 - SATA RST Interrupt Mode
Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
0:Msix, 1:Msi, 2:Legacy
**/
UINT8 SataRstInterrupt;
-/** Offset 0x0ADF - ME Unconfig on RTC clear
+/** Offset 0x0AF7 - ME Unconfig on RTC clear
0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
2: Cmos is clear, status unkonwn. 3: Reserved
0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
@@ -2571,13 +2559,13 @@ typedef struct {
**/
UINT8 MeUnconfigOnRtcClear;
-/** Offset 0x0AE0 - Enforce Enhanced Debug Mode
+/** Offset 0x0AF8 - Enforce Enhanced Debug Mode
Determine if ME should enter Enhanced Debug Mode. <b>0: disable</b>, 1: enable
$EN_DIS
**/
UINT8 EnforceEDebugMode;
-/** Offset 0x0AE1 - Enable PS_ON.
+/** Offset 0x0AF9 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
target that will be required by the California Energy Commission (CEC). When FALSE,
PS_ON is to be disabled.
@@ -2585,142 +2573,142 @@ typedef struct {
**/
UINT8 PsOnEnable;
-/** Offset 0x0AE2 - Pmc Cpu C10 Gate Pin Enable
+/** Offset 0x0AFA - Pmc Cpu C10 Gate Pin Enable
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
and VccSTG rails instead of SLP_S0# pin.
$EN_DIS
**/
UINT8 PmcCpuC10GatePinEnable;
-/** Offset 0x0AE3 - Pch Dmi Aspm Ctrl
+/** Offset 0x0AFB - Pch Dmi Aspm Ctrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmL1</b>
0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
**/
UINT8 PchDmiAspmCtrl;
-/** Offset 0x0AE4 - PchDmiCwbEnable
+/** Offset 0x0AFC - PchDmiCwbEnable
Central Write Buffer feature configurable and enabled by default
$EN_DIS
**/
UINT8 PchDmiCwbEnable;
-/** Offset 0x0AE5 - OS IDLE Mode Enable
+/** Offset 0x0AFD - OS IDLE Mode Enable
Enable/Disable OS Idle Mode
$EN_DIS
**/
UINT8 PmcOsIdleEnable;
-/** Offset 0x0AE6 - S0ix Auto-Demotion
+/** Offset 0x0AFE - S0ix Auto-Demotion
Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
$EN_DIS
**/
UINT8 PchS0ixAutoDemotion;
-/** Offset 0x0AE7 - Latch Events C10 Exit
+/** Offset 0x0AFF - Latch Events C10 Exit
When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
captured on C10 exit (instead of C10 entry which is default)
$EN_DIS
**/
UINT8 PchPmLatchEventsC10Exit;
-/** Offset 0x0AE8 - Reserved
+/** Offset 0x0B00 - Reserved
**/
- UINT8 Reserved48[12];
+ UINT8 Reserved45[12];
-/** Offset 0x0AF4 - PCIE Eq Ph3 Lane Param Cm
+/** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm
CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
**/
UINT8 CpuPcieEqPh3LaneParamCm[32];
-/** Offset 0x0B14 - PCIE Eq Ph3 Lane Param Cp
+/** Offset 0x0B2C - PCIE Eq Ph3 Lane Param Cp
CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1.
**/
UINT8 CpuPcieEqPh3LaneParamCp[32];
-/** Offset 0x0B34 - Gen3 Root port preset values per lane
+/** Offset 0x0B4C - Gen3 Root port preset values per lane
Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default
for each lane
**/
UINT8 CpuPcieGen3RootPortPreset[20];
-/** Offset 0x0B48 - Pcie Gen4 Root port preset values per lane
+/** Offset 0x0B60 - Pcie Gen4 Root port preset values per lane
Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default
for each lane
**/
UINT8 CpuPcieGen4RootPortPreset[20];
-/** Offset 0x0B5C - Pcie Gen3 End port preset values per lane
+/** Offset 0x0B74 - Pcie Gen3 End port preset values per lane
Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default
for each lane
**/
UINT8 CpuPcieGen3EndPointPreset[20];
-/** Offset 0x0B70 - Pcie Gen4 End port preset values per lane
+/** Offset 0x0B88 - Pcie Gen4 End port preset values per lane
Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default
for each lane
**/
UINT8 CpuPcieGen4EndPointPreset[20];
-/** Offset 0x0B84 - Pcie Gen3 End port Hint values per lane
+/** Offset 0x0B9C - Pcie Gen3 End port Hint values per lane
Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
**/
UINT8 CpuPcieGen3EndPointHint[20];
-/** Offset 0x0B98 - Pcie Gen4 End port Hint values per lane
+/** Offset 0x0BB0 - Pcie Gen4 End port Hint values per lane
Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane
**/
UINT8 CpuPcieGen4EndPointHint[20];
-/** Offset 0x0BAC - CPU PCIe Fia Programming
+/** Offset 0x0BC4 - CPU PCIe Fia Programming
Load Fia configuration if enable. 0: Disable; 1: Enable(Default).
$EN_DIS
**/
UINT8 CpuPcieFiaProgramming;
-/** Offset 0x0BAD - CPU PCIe RootPort Clock Gating
+/** Offset 0x0BC5 - CPU PCIe RootPort Clock Gating
Describes whether the PCI Express Clock Gating for each root port is enabled by
platform modules. 0: Disable; 1: Enable(Default).
$EN_DIS
**/
UINT8 CpuPcieClockGating[4];
-/** Offset 0x0BB1 - CPU PCIe RootPort Power Gating
+/** Offset 0x0BC9 - CPU PCIe RootPort Power Gating
Describes whether the PCI Express Power Gating for each root port is enabled by
platform modules. 0: Disable; 1: Enable(Default).
$EN_DIS
**/
UINT8 CpuPciePowerGating[4];
-/** Offset 0x0BB5 - PCIE Compliance Test Mode
+/** Offset 0x0BCD - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 CpuPcieComplianceTestMode;
-/** Offset 0x0BB6 - PCIE Enable Peer Memory Write
+/** Offset 0x0BCE - PCIE Enable Peer Memory Write
This member describes whether Peer Memory Writes are enabled on the platform.
$EN_DIS
**/
UINT8 CpuPcieEnablePeerMemoryWrite;
-/** Offset 0x0BB7 - PCIE Rp Function Swap
+/** Offset 0x0BCF - PCIE Rp Function Swap
Allows BIOS to use root port function number swapping when root port of function
0 is disabled.
$EN_DIS
**/
UINT8 CpuPcieRpFunctionSwap;
-/** Offset 0x0BB8 - PCI Express Slot Selection
+/** Offset 0x0BD0 - PCI Express Slot Selection
Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default).
$EN_DIS
**/
UINT8 CpuPcieSlotSelection;
-/** Offset 0x0BB9 - Reserved
+/** Offset 0x0BD1 - Reserved
**/
- UINT8 Reserved49[3];
+ UINT8 Reserved46[3];
-/** Offset 0x0BBC - CPU PCIE device override table pointer
+/** Offset 0x0BD4 - CPU PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This
is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
@@ -2728,231 +2716,231 @@ typedef struct {
**/
UINT32 CpuPcieDeviceOverrideTablePtr;
-/** Offset 0x0BC0 - Enable PCIE RP HotPlug
+/** Offset 0x0BD8 - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
**/
UINT8 CpuPcieRpHotPlug[4];
-/** Offset 0x0BC4 - Enable PCIE RP Pm Sci
+/** Offset 0x0BDC - Enable PCIE RP Pm Sci
Indicate whether the root port power manager SCI is enabled.
**/
UINT8 CpuPcieRpPmSci[4];
-/** Offset 0x0BC8 - Enable PCIE RP Transmitter Half Swing
+/** Offset 0x0BE0 - Enable PCIE RP Transmitter Half Swing
Indicate whether the Transmitter Half Swing is enabled.
**/
UINT8 CpuPcieRpTransmitterHalfSwing[4];
-/** Offset 0x0BCC - PCIE RP Access Control Services Extended Capability
+/** Offset 0x0BE4 - PCIE RP Access Control Services Extended Capability
Enable/Disable PCIE RP Access Control Services Extended Capability
**/
UINT8 CpuPcieRpAcsEnabled[4];
-/** Offset 0x0BD0 - PCIE RP Clock Power Management
+/** Offset 0x0BE8 - PCIE RP Clock Power Management
Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
can still be controlled by L1 PM substates mechanism
**/
UINT8 CpuPcieRpEnableCpm[4];
-/** Offset 0x0BD4 - PCIE RP Advanced Error Report
+/** Offset 0x0BEC - PCIE RP Advanced Error Report
Indicate whether the Advanced Error Reporting is enabled.
**/
UINT8 CpuPcieRpAdvancedErrorReporting[4];
-/** Offset 0x0BD8 - PCIE RP Unsupported Request Report
+/** Offset 0x0BF0 - PCIE RP Unsupported Request Report
Indicate whether the Unsupported Request Report is enabled.
**/
UINT8 CpuPcieRpUnsupportedRequestReport[4];
-/** Offset 0x0BDC - PCIE RP Fatal Error Report
+/** Offset 0x0BF4 - PCIE RP Fatal Error Report
Indicate whether the Fatal Error Report is enabled.
**/
UINT8 CpuPcieRpFatalErrorReport[4];
-/** Offset 0x0BE0 - PCIE RP No Fatal Error Report
+/** Offset 0x0BF8 - PCIE RP No Fatal Error Report
Indicate whether the No Fatal Error Report is enabled.
**/
UINT8 CpuPcieRpNoFatalErrorReport[4];
-/** Offset 0x0BE4 - PCIE RP Correctable Error Report
+/** Offset 0x0BFC - PCIE RP Correctable Error Report
Indicate whether the Correctable Error Report is enabled.
**/
UINT8 CpuPcieRpCorrectableErrorReport[4];
-/** Offset 0x0BE8 - PCIE RP System Error On Fatal Error
+/** Offset 0x0C00 - PCIE RP System Error On Fatal Error
Indicate whether the System Error on Fatal Error is enabled.
**/
UINT8 CpuPcieRpSystemErrorOnFatalError[4];
-/** Offset 0x0BEC - PCIE RP System Error On Non Fatal Error
+/** Offset 0x0C04 - PCIE RP System Error On Non Fatal Error
Indicate whether the System Error on Non Fatal Error is enabled.
**/
UINT8 CpuPcieRpSystemErrorOnNonFatalError[4];
-/** Offset 0x0BF0 - PCIE RP System Error On Correctable Error
+/** Offset 0x0C08 - PCIE RP System Error On Correctable Error
Indicate whether the System Error on Correctable Error is enabled.
**/
UINT8 CpuPcieRpSystemErrorOnCorrectableError[4];
-/** Offset 0x0BF4 - PCIE RP Max Payload
+/** Offset 0x0C0C - PCIE RP Max Payload
Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD.
**/
UINT8 CpuPcieRpMaxPayload[4];
-/** Offset 0x0BF8 - DPC for PCIE RP Mask
+/** Offset 0x0C10 - DPC for PCIE RP Mask
Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
One bit for each port, bit0 for port1, bit1 for port2, and so on.
**/
UINT8 CpuPcieRpDpcEnabled[4];
-/** Offset 0x0BFC - DPC Extensions PCIE RP Mask
+/** Offset 0x0C14 - DPC Extensions PCIE RP Mask
Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
for each port, bit0 for port1, bit1 for port2, and so on.
**/
UINT8 CpuPcieRpDpcExtensionsEnabled[4];
-/** Offset 0x0C00 - CPU PCIe root port connection type
+/** Offset 0x0C18 - CPU PCIe root port connection type
0: built-in device, 1:slot
**/
UINT8 CpuPcieRpSlotImplemented[4];
-/** Offset 0x0C04 - PCIE RP Gen3 Equalization Phase Method
+/** Offset 0x0C1C - PCIE RP Gen3 Equalization Phase Method
PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
1: hardware equalization; 4: Fixed Coeficients.
**/
UINT8 CpuPcieRpGen3EqPh3Method[4];
-/** Offset 0x0C08 - PCIE RP Gen4 Equalization Phase Method
+/** Offset 0x0C20 - PCIE RP Gen4 Equalization Phase Method
PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
1: hardware equalization; 4: Fixed Coeficients.
**/
UINT8 CpuPcieRpGen4EqPh3Method[4];
-/** Offset 0x0C0C - PCIE RP Physical Slot Number
+/** Offset 0x0C24 - PCIE RP Physical Slot Number
Indicates the slot number for the root port. Default is the value as root port index.
**/
UINT8 CpuPcieRpPhysicalSlotNumber[4];
-/** Offset 0x0C10 - PCIE RP Aspm
+/** Offset 0x0C28 - PCIE RP Aspm
The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable;
1: CpuPcieAspmL0s; 2: CpuPcieAspmL1; 3:CpuPcieAspmL0sL1(Default)
**/
UINT8 CpuPcieRpAspm[4];
-/** Offset 0x0C14 - PCIE RP L1 Substates
+/** Offset 0x0C2C - PCIE RP L1 Substates
The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL).
Default is CpuPcieL1SubstatesL1_1_2.
**/
UINT8 CpuPcieRpL1Substates[4];
-/** Offset 0x0C18 - PCIE RP Ltr Enable
+/** Offset 0x0C30 - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 CpuPcieRpLtrEnable[4];
-/** Offset 0x0C1C - PCIE RP Ltr Config Lock
+/** Offset 0x0C34 - PCIE RP Ltr Config Lock
0: Disable; 1: Enable.
**/
UINT8 CpuPcieRpLtrConfigLock[4];
-/** Offset 0x0C20 - RpPtmBytes
+/** Offset 0x0C38 - RpPtmBytes
**/
UINT8 RpPtmBytes[4];
-/** Offset 0x0C24 - PCIE RP Detect Timeout Ms
+/** Offset 0x0C3C - PCIE RP Detect Timeout Ms
The number of milliseconds within 0~65535 in reference code will wait for link to
exit Detect state for enabled ports before assuming there is no device and potentially
disabling the port.
**/
UINT16 CpuPcieRpDetectTimeoutMs[4];
-/** Offset 0x0C2C - Multi-VC for PCIE RP Mask
+/** Offset 0x0C44 - Multi-VC for PCIE RP Mask
Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable.
One bit for each port, bit0 for port1, bit1 for port2, and so on.
**/
UINT8 CpuPcieRpMultiVcEnabled[4];
-/** Offset 0x0C30 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+/** Offset 0x0C48 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTranEnable[10];
-/** Offset 0x0C3A - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+/** Offset 0x0C52 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
= 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTran[10];
-/** Offset 0x0C44 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+/** Offset 0x0C5C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTranEnable[10];
-/** Offset 0x0C4E - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+/** Offset 0x0C66 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTran[10];
-/** Offset 0x0C58 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+/** Offset 0x0C70 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTranEnable[10];
-/** Offset 0x0C62 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+/** Offset 0x0C7A - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTran[10];
-/** Offset 0x0C6C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+/** Offset 0x0C84 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTranEnable[10];
-/** Offset 0x0C76 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+/** Offset 0x0C8E - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTran[10];
-/** Offset 0x0C80 - Skip PAM regsiter lock
+/** Offset 0x0C98 - Skip PAM regsiter lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
**/
UINT8 SkipPamLock;
-/** Offset 0x0C81 - EDRAM Test Mode
+/** Offset 0x0C99 - EDRAM Test Mode
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
**/
UINT8 EdramTestMode;
-/** Offset 0x0C82 - Enable/Disable IGFX RenderStandby
+/** Offset 0x0C9A - Enable/Disable IGFX RenderStandby
Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
$EN_DIS
**/
UINT8 RenderStandby;
-/** Offset 0x0C83 - Enable/Disable IGFX PmSupport
+/** Offset 0x0C9B - Enable/Disable IGFX PmSupport
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
$EN_DIS
**/
UINT8 PmSupport;
-/** Offset 0x0C84 - Enable/Disable CdynmaxClamp
+/** Offset 0x0C9C - Enable/Disable CdynmaxClamp
Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp
$EN_DIS
**/
UINT8 CdynmaxClampEnable;
-/** Offset 0x0C85 - GT Frequency Limit
+/** Offset 0x0C9D - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -2966,113 +2954,113 @@ typedef struct {
**/
UINT8 GtFreqMax;
-/** Offset 0x0C86 - Disable Turbo GT
+/** Offset 0x0C9E - Disable Turbo GT
0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
$EN_DIS
**/
UINT8 DisableTurboGt;
-/** Offset 0x0C87 - Enable/Disable CdClock Init
+/** Offset 0x0C9F - Enable/Disable CdClock Init
Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
CD clock if not initialized by Gfx PEIM
$EN_DIS
**/
UINT8 SkipCdClockInit;
-/** Offset 0x0C88 - Enable RC1p frequency request to PMA (provided all other conditions are met)
+/** Offset 0x0CA0 - Enable RC1p frequency request to PMA (provided all other conditions are met)
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 RC1pFreqEnable;
-/** Offset 0x0C89 - Enable TSN Multi-VC
+/** Offset 0x0CA1 - Enable TSN Multi-VC
Enable/disable Multi Virtual Channels(VC) in TSN.
$EN_DIS
**/
UINT8 PchTsnMultiVcEnable;
-/** Offset 0x0C8A - Reserved
+/** Offset 0x0CA2 - Reserved
**/
- UINT8 Reserved50[2];
+ UINT8 Reserved47[2];
-/** Offset 0x0C8C - LogoPixelHeight Address
+/** Offset 0x0CA4 - LogoPixelHeight Address
Address of LogoPixelHeight
**/
UINT32 LogoPixelHeight;
-/** Offset 0x0C90 - LogoPixelWidth Address
+/** Offset 0x0CA8 - LogoPixelWidth Address
Address of LogoPixelWidth
**/
UINT32 LogoPixelWidth;
-/** Offset 0x0C94 - Reserved
+/** Offset 0x0CAC - Reserved
**/
- UINT8 Reserved51[5];
+ UINT8 Reserved48[5];
-/** Offset 0x0C99 - RSR feature
+/** Offset 0x0CB1 - RSR feature
Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
$EN_DIS
**/
UINT8 EnableRsr;
-/** Offset 0x0C9A - Reserved
+/** Offset 0x0CB2 - Reserved
**/
- UINT8 Reserved52[4];
+ UINT8 Reserved49[4];
-/** Offset 0x0C9E - Enable or Disable HWP
+/** Offset 0x0CB6 - Enable or Disable HWP
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
2-3:Reserved
$EN_DIS
**/
UINT8 Hwp;
-/** Offset 0x0C9F - Hardware Duty Cycle Control
+/** Offset 0x0CB7 - Hardware Duty Cycle Control
Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
$EN_DIS
**/
UINT8 HdcControl;
-/** Offset 0x0CA0 - Package Long duration turbo mode time
+/** Offset 0x0CB8 - Package Long duration turbo mode time
Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)
0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
**/
UINT8 PowerLimit1Time;
-/** Offset 0x0CA1 - Short Duration Turbo Mode
+/** Offset 0x0CB9 - Short Duration Turbo Mode
Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PowerLimit2;
-/** Offset 0x0CA2 - Turbo settings Lock
+/** Offset 0x0CBA - Turbo settings Lock
Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
$EN_DIS
**/
UINT8 TurboPowerLimitLock;
-/** Offset 0x0CA3 - Package PL3 time window
+/** Offset 0x0CBB - Package PL3 time window
Package PL3 time window range for this policy from 0 to 64ms
**/
UINT8 PowerLimit3Time;
-/** Offset 0x0CA4 - Package PL3 Duty Cycle
+/** Offset 0x0CBC - Package PL3 Duty Cycle
Package PL3 Duty Cycle; Valid Range is 0 to 100
**/
UINT8 PowerLimit3DutyCycle;
-/** Offset 0x0CA5 - Package PL3 Lock
+/** Offset 0x0CBD - Package PL3 Lock
Package PL3 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit3Lock;
-/** Offset 0x0CA6 - Package PL4 Lock
+/** Offset 0x0CBE - Package PL4 Lock
Package PL4 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit4Lock;
-/** Offset 0x0CA7 - TCC Activation Offset
+/** Offset 0x0CBF - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
@@ -3080,7 +3068,7 @@ typedef struct {
**/
UINT8 TccActivationOffset;
-/** Offset 0x0CA8 - Tcc Offset Clamp Enable/Disable
+/** Offset 0x0CC0 - Tcc Offset Clamp Enable/Disable
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
For all other SKUs the recommended default are <b>0: Disabled</b>.
@@ -3088,319 +3076,319 @@ typedef struct {
**/
UINT8 TccOffsetClamp;
-/** Offset 0x0CA9 - Tcc Offset Lock
+/** Offset 0x0CC1 - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
target; <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetLock;
-/** Offset 0x0CAA - Custom Ratio State Entries
+/** Offset 0x0CC2 - Custom Ratio State Entries
The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
ratio table.Sets the number of custom P-states. At least 2 states must be present
**/
UINT8 NumberOfEntries;
-/** Offset 0x0CAB - Custom Short term Power Limit time window
+/** Offset 0x0CC3 - Custom Short term Power Limit time window
Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128
**/
UINT8 Custom1PowerLimit1Time;
-/** Offset 0x0CAC - Custom Turbo Activation Ratio
+/** Offset 0x0CC4 - Custom Turbo Activation Ratio
Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
**/
UINT8 Custom1TurboActivationRatio;
-/** Offset 0x0CAD - Custom Config Tdp Control
+/** Offset 0x0CC5 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom1ConfigTdpControl;
-/** Offset 0x0CAE - Custom Short term Power Limit time window
+/** Offset 0x0CC6 - Custom Short term Power Limit time window
Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128
**/
UINT8 Custom2PowerLimit1Time;
-/** Offset 0x0CAF - Custom Turbo Activation Ratio
+/** Offset 0x0CC7 - Custom Turbo Activation Ratio
Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
**/
UINT8 Custom2TurboActivationRatio;
-/** Offset 0x0CB0 - Custom Config Tdp Control
+/** Offset 0x0CC8 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom2ConfigTdpControl;
-/** Offset 0x0CB1 - Custom Short term Power Limit time window
+/** Offset 0x0CC9 - Custom Short term Power Limit time window
Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128
**/
UINT8 Custom3PowerLimit1Time;
-/** Offset 0x0CB2 - Custom Turbo Activation Ratio
+/** Offset 0x0CCA - Custom Turbo Activation Ratio
Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
**/
UINT8 Custom3TurboActivationRatio;
-/** Offset 0x0CB3 - Custom Config Tdp Control
+/** Offset 0x0CCB - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom3ConfigTdpControl;
-/** Offset 0x0CB4 - ConfigTdp mode settings Lock
+/** Offset 0x0CCC - ConfigTdp mode settings Lock
Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 ConfigTdpLock;
-/** Offset 0x0CB5 - Load Configurable TDP SSDT
+/** Offset 0x0CCD - Load Configurable TDP SSDT
Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ConfigTdpBios;
-/** Offset 0x0CB6 - PL1 Enable value
+/** Offset 0x0CCE - PL1 Enable value
PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 PsysPowerLimit1;
-/** Offset 0x0CB7 - PL1 timewindow
+/** Offset 0x0CCF - PL1 timewindow
PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16
, 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
**/
UINT8 PsysPowerLimit1Time;
-/** Offset 0x0CB8 - PL2 Enable Value
+/** Offset 0x0CD0 - PL2 Enable Value
PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
1: Enable.
$EN_DIS
**/
UINT8 PsysPowerLimit2;
-/** Offset 0x0CB9 - Enable or Disable MLC Streamer Prefetcher
+/** Offset 0x0CD1 - Enable or Disable MLC Streamer Prefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MlcStreamerPrefetcher;
-/** Offset 0x0CBA - Enable or Disable MLC Spatial Prefetcher
+/** Offset 0x0CD2 - Enable or Disable MLC Spatial Prefetcher
Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 MlcSpatialPrefetcher;
-/** Offset 0x0CBB - Enable or Disable Monitor /MWAIT instructions
+/** Offset 0x0CD3 - Enable or Disable Monitor /MWAIT instructions
Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MonitorMwaitEnable;
-/** Offset 0x0CBC - Enable or Disable initialization of machine check registers
+/** Offset 0x0CD4 - Enable or Disable initialization of machine check registers
Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MachineCheckEnable;
-/** Offset 0x0CBD - AP Idle Manner of waiting for SIPI
+/** Offset 0x0CD5 - AP Idle Manner of waiting for SIPI
AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
1: HALT loop, 2: MWAIT loop, 3: RUN loop
**/
UINT8 ApIdleManner;
-/** Offset 0x0CBE - Control on Processor Trace output scheme
+/** Offset 0x0CD6 - Control on Processor Trace output scheme
Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
0: Single Range Output, 1: ToPA Output
**/
UINT8 ProcessorTraceOutputScheme;
-/** Offset 0x0CBF - Enable or Disable Processor Trace feature
+/** Offset 0x0CD7 - Enable or Disable Processor Trace feature
Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcessorTraceEnable;
-/** Offset 0x0CC0 - Enable or Disable Intel SpeedStep Technology
+/** Offset 0x0CD8 - Enable or Disable Intel SpeedStep Technology
Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Eist;
-/** Offset 0x0CC1 - Enable or Disable Energy Efficient P-state
+/** Offset 0x0CD9 - Enable or Disable Energy Efficient P-state
Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
<b>1: Enable</b>
$EN_DIS
**/
UINT8 EnergyEfficientPState;
-/** Offset 0x0CC2 - Enable or Disable Energy Efficient Turbo
+/** Offset 0x0CDA - Enable or Disable Energy Efficient Turbo
Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 EnergyEfficientTurbo;
-/** Offset 0x0CC3 - Enable or Disable T states
+/** Offset 0x0CDB - Enable or Disable T states
Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TStates;
-/** Offset 0x0CC4 - Enable or Disable Bi-Directional PROCHOT#
+/** Offset 0x0CDC - Enable or Disable Bi-Directional PROCHOT#
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 BiProcHot;
-/** Offset 0x0CC5 - Enable or Disable PROCHOT# signal being driven externally
+/** Offset 0x0CDD - Enable or Disable PROCHOT# signal being driven externally
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DisableProcHotOut;
-/** Offset 0x0CC6 - Enable or Disable PROCHOT# Response
+/** Offset 0x0CDE - Enable or Disable PROCHOT# Response
Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcHotResponse;
-/** Offset 0x0CC7 - Enable or Disable VR Thermal Alert
+/** Offset 0x0CDF - Enable or Disable VR Thermal Alert
Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 DisableVrThermalAlert;
-/** Offset 0x0CC8 - Enable or Disable Thermal Reporting
+/** Offset 0x0CE0 - Enable or Disable Thermal Reporting
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 EnableAllThermalFunctions;
-/** Offset 0x0CC9 - Enable or Disable Thermal Monitor
+/** Offset 0x0CE1 - Enable or Disable Thermal Monitor
Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 ThermalMonitor;
-/** Offset 0x0CCA - Enable or Disable CPU power states (C-states)
+/** Offset 0x0CE2 - Enable or Disable CPU power states (C-states)
Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
-/** Offset 0x0CCB - Configure C-State Configuration Lock
+/** Offset 0x0CE3 - Configure C-State Configuration Lock
Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 PmgCstCfgCtrlLock;
-/** Offset 0x0CCC - Enable or Disable Enhanced C-states
+/** Offset 0x0CE4 - Enable or Disable Enhanced C-states
Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1e;
-/** Offset 0x0CCD - Enable or Disable Package Cstate Demotion
+/** Offset 0x0CE5 - Enable or Disable Package Cstate Demotion
Enable or Disable Package Cstate Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateDemotion;
-/** Offset 0x0CCE - Enable or Disable Package Cstate UnDemotion
+/** Offset 0x0CE6 - Enable or Disable Package Cstate UnDemotion
Enable or Disable Package Cstate UnDemotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateUnDemotion;
-/** Offset 0x0CCF - Enable or Disable CState-Pre wake
+/** Offset 0x0CE7 - Enable or Disable CState-Pre wake
Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CStatePreWake;
-/** Offset 0x0CD0 - Enable or Disable TimedMwait Support.
+/** Offset 0x0CE8 - Enable or Disable TimedMwait Support.
Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 TimedMwait;
-/** Offset 0x0CD1 - Enable or Disable IO to MWAIT redirection
+/** Offset 0x0CE9 - Enable or Disable IO to MWAIT redirection
Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CstCfgCtrIoMwaitRedirection;
-/** Offset 0x0CD2 - Set the Max Pkg Cstate
+/** Offset 0x0CEA - Set the Max Pkg Cstate
Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
**/
UINT8 PkgCStateLimit;
-/** Offset 0x0CD3 - TimeUnit for C-State Latency Control0
+/** Offset 0x0CEB - TimeUnit for C-State Latency Control0
TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl0TimeUnit;
-/** Offset 0x0CD4 - TimeUnit for C-State Latency Control1
+/** Offset 0x0CEC - TimeUnit for C-State Latency Control1
TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl1TimeUnit;
-/** Offset 0x0CD5 - TimeUnit for C-State Latency Control2
+/** Offset 0x0CED - TimeUnit for C-State Latency Control2
TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl2TimeUnit;
-/** Offset 0x0CD6 - TimeUnit for C-State Latency Control3
+/** Offset 0x0CEE - TimeUnit for C-State Latency Control3
TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl3TimeUnit;
-/** Offset 0x0CD7 - TimeUnit for C-State Latency Control4
+/** Offset 0x0CEF - TimeUnit for C-State Latency Control4
Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl4TimeUnit;
-/** Offset 0x0CD8 - TimeUnit for C-State Latency Control5
+/** Offset 0x0CF0 - TimeUnit for C-State Latency Control5
TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
, 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
**/
UINT8 CstateLatencyControl5TimeUnit;
-/** Offset 0x0CD9 - Interrupt Redirection Mode Select
+/** Offset 0x0CF1 - Interrupt Redirection Mode Select
Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:
No change.
**/
UINT8 PpmIrmSetting;
-/** Offset 0x0CDA - Lock prochot configuration
+/** Offset 0x0CF2 - Lock prochot configuration
Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 ProcHotLock;
-/** Offset 0x0CDB - Configuration for boot TDP selection
+/** Offset 0x0CF3 - Configuration for boot TDP selection
Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
Up;0xFF : Deactivate
**/
UINT8 ConfigTdpLevel;
-/** Offset 0x0CDC - Max P-State Ratio
+/** Offset 0x0CF4 - Max P-State Ratio
Max P-State Ratio, Valid Range 0 to 0x7F
**/
UINT8 MaxRatio;
-/** Offset 0x0CDD - P-state ratios for custom P-state table
+/** Offset 0x0CF5 - P-state ratios for custom P-state table
P-state ratios for custom P-state table. NumberOfEntries has valid range between
0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
are configurable. Valid Range of each entry is 0 to 0x7F
**/
UINT8 StateRatio[40];
-/** Offset 0x0D05 - P-state ratios for max 16 version of custom P-state table
+/** Offset 0x0D1D - P-state ratios for max 16 version of custom P-state table
P-state ratios for max 16 version of custom P-state table. This table is used for
OS versions limited to a max of 16 P-States. If the first entry of this table is
0, or if Number of Entries is 16 or less, then this table will be ignored, and
@@ -3409,129 +3397,129 @@ typedef struct {
**/
UINT8 StateRatioMax16[16];
-/** Offset 0x0D15 - Reserved
+/** Offset 0x0D2D - Reserved
**/
- UINT8 Reserved53;
+ UINT8 Reserved50;
-/** Offset 0x0D16 - Platform Power Pmax
+/** Offset 0x0D2E - Platform Power Pmax
PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
Range 0-1024 Watts. Value of 800 = 100W
**/
UINT16 PsysPmax;
-/** Offset 0x0D18 - Interrupt Response Time Limit of C-State LatencyContol1
+/** Offset 0x0D30 - Interrupt Response Time Limit of C-State LatencyContol1
Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF.
0 is Auto.
**/
UINT16 CstateLatencyControl1Irtl;
-/** Offset 0x0D1A - Interrupt Response Time Limit of C-State LatencyContol2
+/** Offset 0x0D32 - Interrupt Response Time Limit of C-State LatencyContol2
Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF.
0 is Auto.
**/
UINT16 CstateLatencyControl2Irtl;
-/** Offset 0x0D1C - Interrupt Response Time Limit of C-State LatencyContol3
+/** Offset 0x0D34 - Interrupt Response Time Limit of C-State LatencyContol3
Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF.
0 is Auto.
**/
UINT16 CstateLatencyControl3Irtl;
-/** Offset 0x0D1E - Interrupt Response Time Limit of C-State LatencyContol4
+/** Offset 0x0D36 - Interrupt Response Time Limit of C-State LatencyContol4
Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF.
0 is Auto.
**/
UINT16 CstateLatencyControl4Irtl;
-/** Offset 0x0D20 - Interrupt Response Time Limit of C-State LatencyContol5
+/** Offset 0x0D38 - Interrupt Response Time Limit of C-State LatencyContol5
Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF.
0 is Auto.
**/
UINT16 CstateLatencyControl5Irtl;
-/** Offset 0x0D22 - Reserved
+/** Offset 0x0D3A - Reserved
**/
- UINT8 Reserved54[2];
+ UINT8 Reserved51[2];
-/** Offset 0x0D24 - Package Long duration turbo mode power limit
+/** Offset 0x0D3C - Package Long duration turbo mode power limit
Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
Valid Range 0 to 4095875 in Step size of 125
**/
UINT32 PowerLimit1;
-/** Offset 0x0D28 - Package Short duration turbo mode power limit
+/** Offset 0x0D40 - Package Short duration turbo mode power limit
Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 PowerLimit2Power;
-/** Offset 0x0D2C - Package PL3 power limit
+/** Offset 0x0D44 - Package PL3 power limit
Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 PowerLimit3;
-/** Offset 0x0D30 - Package PL4 power limit
+/** Offset 0x0D48 - Package PL4 power limit
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 PowerLimit4;
-/** Offset 0x0D34 - Tcc Offset Time Window for RATL
+/** Offset 0x0D4C - Tcc Offset Time Window for RATL
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 TccOffsetTimeWindowForRatl;
-/** Offset 0x0D38 - Short term Power Limit value for custom cTDP level 1
+/** Offset 0x0D50 - Short term Power Limit value for custom cTDP level 1
Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom1PowerLimit1;
-/** Offset 0x0D3C - Long term Power Limit value for custom cTDP level 1
+/** Offset 0x0D54 - Long term Power Limit value for custom cTDP level 1
Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom1PowerLimit2;
-/** Offset 0x0D40 - Short term Power Limit value for custom cTDP level 2
+/** Offset 0x0D58 - Short term Power Limit value for custom cTDP level 2
Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom2PowerLimit1;
-/** Offset 0x0D44 - Long term Power Limit value for custom cTDP level 2
+/** Offset 0x0D5C - Long term Power Limit value for custom cTDP level 2
Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom2PowerLimit2;
-/** Offset 0x0D48 - Short term Power Limit value for custom cTDP level 3
+/** Offset 0x0D60 - Short term Power Limit value for custom cTDP level 3
Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom3PowerLimit1;
-/** Offset 0x0D4C - Long term Power Limit value for custom cTDP level 3
+/** Offset 0x0D64 - Long term Power Limit value for custom cTDP level 3
Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
Range 0 to 4095875 in Step size of 125
**/
UINT32 Custom3PowerLimit2;
-/** Offset 0x0D50 - Platform PL1 power
+/** Offset 0x0D68 - Platform PL1 power
Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
0 to 4095875 in Step size of 125
**/
UINT32 PsysPowerLimit1Power;
-/** Offset 0x0D54 - Platform PL2 power
+/** Offset 0x0D6C - Platform PL2 power
Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
0 to 4095875 in Step size of 125
**/
UINT32 PsysPowerLimit2Power;
-/** Offset 0x0D58 - Race To Halt
+/** Offset 0x0D70 - Race To Halt
Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
through MSR 1FC bit 20)Disable; <b>1: Enable</b>
@@ -3539,340 +3527,340 @@ typedef struct {
**/
UINT8 RaceToHalt;
-/** Offset 0x0D59 - Set Three Strike Counter Disable
+/** Offset 0x0D71 - Set Three Strike Counter Disable
False (default): Three Strike counter will be incremented and True: Prevents Three
Strike counter from incrementing; <b>0: False</b>; 1: True.
0: False, 1: True
**/
UINT8 ThreeStrikeCounterDisable;
-/** Offset 0x0D5A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+/** Offset 0x0D72 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 HwpInterruptControl;
-/** Offset 0x0D5B - Reserved
+/** Offset 0x0D73 - Reserved
**/
- UINT8 Reserved55[4];
+ UINT8 Reserved52[4];
-/** Offset 0x0D5F - Intel Turbo Boost Max Technology 3.0
+/** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0
Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
$EN_DIS
**/
UINT8 EnableItbm;
-/** Offset 0x0D60 - Enable or Disable C1 Cstate Demotion
+/** Offset 0x0D78 - Enable or Disable C1 Cstate Demotion
Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateAutoDemotion;
-/** Offset 0x0D61 - Enable or Disable C1 Cstate UnDemotion
+/** Offset 0x0D79 - Enable or Disable C1 Cstate UnDemotion
Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateUnDemotion;
-/** Offset 0x0D62 - Minimum Ring ratio limit override
+/** Offset 0x0D7A - Minimum Ring ratio limit override
Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MinRingRatioLimit;
-/** Offset 0x0D63 - Maximum Ring ratio limit override
+/** Offset 0x0D7B - Maximum Ring ratio limit override
Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MaxRingRatioLimit;
-/** Offset 0x0D64 - Enable or Disable Per Core P State OS control
+/** Offset 0x0D7C - Enable or Disable Per Core P State OS control
Enable or Disable Per Core P State OS control. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnablePerCorePState;
-/** Offset 0x0D65 - Enable or Disable HwP Autonomous Per Core P State OS control
+/** Offset 0x0D7D - Enable or Disable HwP Autonomous Per Core P State OS control
Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; <b>1:
Enable</b>
$EN_DIS
**/
UINT8 EnableHwpAutoPerCorePstate;
-/** Offset 0x0D66 - Enable or Disable HwP Autonomous EPP Grouping
+/** Offset 0x0D7E - Enable or Disable HwP Autonomous EPP Grouping
Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnableHwpAutoEppGrouping;
-/** Offset 0x0D67 - Enable or Disable EPB override over PECI
+/** Offset 0x0D7F - Enable or Disable EPB override over PECI
Enable or Disable EPB override over PECI. <b>0: Disable;</b> 1: Enable
$EN_DIS
**/
UINT8 EnableEpbPeciOverride;
-/** Offset 0x0D68 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
+/** Offset 0x0D80 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;<b> 1: Enable</b>
$EN_DIS
**/
UINT8 EnableFastMsrHwpReq;
-/** Offset 0x0D69 - Enable Configurable TDP
+/** Offset 0x0D81 - Enable Configurable TDP
Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP;
<b>1: Applies to cTDP</b>
$EN_DIS
**/
UINT8 ApplyConfigTdp;
-/** Offset 0x0D6A - Reserved
+/** Offset 0x0D82 - Reserved
**/
- UINT8 Reserved56;
+ UINT8 Reserved53;
-/** Offset 0x0D6B - Dual Tau Boost
+/** Offset 0x0D83 - Dual Tau Boost
Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0:
Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 DualTauBoost;
-/** Offset 0x0D6C - Reserved
+/** Offset 0x0D84 - Reserved
**/
- UINT8 Reserved57[32];
+ UINT8 Reserved54[32];
-/** Offset 0x0D8C - End of Post message
+/** Offset 0x0DA4 - End of Post message
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
UINT8 EndOfPostMessage;
-/** Offset 0x0D8D - D0I3 Setting for HECI Disable
+/** Offset 0x0DA5 - D0I3 Setting for HECI Disable
Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
HECI devices
$EN_DIS
**/
UINT8 DisableD0I3SettingForHeci;
-/** Offset 0x0D8E - Mctp Broadcast Cycle
+/** Offset 0x0DA6 - Mctp Broadcast Cycle
Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 MctpBroadcastCycle;
-/** Offset 0x0D8F - Enable LOCKDOWN SMI
+/** Offset 0x0DA7 - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
-/** Offset 0x0D90 - Enable LOCKDOWN BIOS Interface
+/** Offset 0x0DA8 - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
-/** Offset 0x0D91 - Unlock all GPIO pads
+/** Offset 0x0DA9 - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x0D92 - PCH Unlock SideBand access
+/** Offset 0x0DAA - PCH Unlock SideBand access
The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
$EN_DIS
**/
UINT8 PchSbAccessUnlock;
-/** Offset 0x0D93 - Reserved
+/** Offset 0x0DAB - Reserved
**/
- UINT8 Reserved58;
+ UINT8 Reserved55;
-/** Offset 0x0D94 - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[28];
-/** Offset 0x0DCC - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x0DE4 - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[28];
-/** Offset 0x0E04 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x0E1C - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 PcieRpSnoopLatencyOverrideMode[28];
-/** Offset 0x0E20 - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x0E38 - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 PcieRpSnoopLatencyOverrideMultiplier[28];
-/** Offset 0x0E3C - PCIE RP Snoop Latency Override Value
+/** Offset 0x0E54 - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 PcieRpSnoopLatencyOverrideValue[28];
-/** Offset 0x0E74 - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x0E8C - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMode[28];
-/** Offset 0x0E90 - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x0EA8 - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28];
-/** Offset 0x0EAC - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x0EC4 - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 PcieRpNonSnoopLatencyOverrideValue[28];
-/** Offset 0x0EE4 - PCIE RP Slot Power Limit Scale
+/** Offset 0x0EFC - PCIE RP Slot Power Limit Scale
Specifies scale used for slot power limit value. Leave as 0 to set to default.
**/
UINT8 PcieRpSlotPowerLimitScale[28];
-/** Offset 0x0F00 - PCIE RP Slot Power Limit Value
+/** Offset 0x0F18 - PCIE RP Slot Power Limit Value
Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
**/
UINT16 PcieRpSlotPowerLimitValue[28];
-/** Offset 0x0F38 - PCIE RP Enable Port8xh Decode
+/** Offset 0x0F50 - PCIE RP Enable Port8xh Decode
This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
1: Enable.
$EN_DIS
**/
UINT8 PcieEnablePort8xhDecode;
-/** Offset 0x0F39 - PCIE Port8xh Decode Port Index
+/** Offset 0x0F51 - PCIE Port8xh Decode Port Index
The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
**/
UINT8 PchPciePort8xhDecodePortIndex;
-/** Offset 0x0F3A - PCH Energy Reporting
+/** Offset 0x0F52 - PCH Energy Reporting
Disable/Enable PCH to CPU energy report feature.
$EN_DIS
**/
UINT8 PchPmDisableEnergyReport;
-/** Offset 0x0F3B - PCH Sata Test Mode
+/** Offset 0x0F53 - PCH Sata Test Mode
Allow entrance to the PCH SATA test modes.
$EN_DIS
**/
UINT8 SataTestMode;
-/** Offset 0x0F3C - PCH USB OverCurrent mapping lock enable
+/** Offset 0x0F54 - PCH USB OverCurrent mapping lock enable
If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
$EN_DIS
**/
UINT8 PchXhciOcLock;
-/** Offset 0x0F3D - LpmStateEnableMask
+/** Offset 0x0F55 - LpmStateEnableMask
**/
UINT8 LpmStateEnableMask;
-/** Offset 0x0F3E - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x0F56 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 CpuPcieRpLtrMaxSnoopLatency[4];
-/** Offset 0x0F46 - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x0F5E - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4];
-/** Offset 0x0F4E - PCIE RP Snoop Latency Override Mode
+/** Offset 0x0F66 - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 CpuPcieRpSnoopLatencyOverrideMode[4];
-/** Offset 0x0F52 - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x0F6A - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4];
-/** Offset 0x0F56 - PCIE RP Snoop Latency Override Value
+/** Offset 0x0F6E - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 CpuPcieRpSnoopLatencyOverrideValue[4];
-/** Offset 0x0F5E - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x0F76 - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4];
-/** Offset 0x0F62 - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x0F7A - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4];
-/** Offset 0x0F66 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x0F7E - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4];
-/** Offset 0x0F6E - PCIE RP Upstream Port Transmiter Preset
+/** Offset 0x0F86 - PCIE RP Upstream Port Transmiter Preset
Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
**/
UINT8 CpuPcieRpGen3Uptp[4];
-/** Offset 0x0F72 - PCIE RP Downstream Port Transmiter Preset
+/** Offset 0x0F8A - PCIE RP Downstream Port Transmiter Preset
Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
**/
UINT8 CpuPcieRpGen3Dptp[4];
-/** Offset 0x0F76 - PCIE RP Upstream Port Transmiter Preset
+/** Offset 0x0F8E - PCIE RP Upstream Port Transmiter Preset
Used during Gen4 Link Equalization. Used for all lanes. Default is 8.
**/
UINT8 CpuPcieRpGen4Uptp[4];
-/** Offset 0x0F7A - PCIE RP Downstream Port Transmiter Preset
+/** Offset 0x0F92 - PCIE RP Downstream Port Transmiter Preset
Used during Gen4 Link Equalization. Used for all lanes. Default is 9.
**/
UINT8 CpuPcieRpGen4Dptp[4];
-/** Offset 0x0F7E - Reserved
+/** Offset 0x0F96 - Reserved
**/
- UINT8 Reserved59[8];
+ UINT8 Reserved56[16];
-/** Offset 0x0F86 - FOMS Control Policy
+/** Offset 0x0FA6 - FOMS Control Policy
Choose the Foms Control Policy, <b>Default = 0 </b>
0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
**/
UINT8 CpuPcieFomsCp[4];
-/** Offset 0x0F8A - PMC C10 dynamic threshold dajustment enable
+/** Offset 0x0FAA - PMC C10 dynamic threshold dajustment enable
Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
$EN_DIS
**/
UINT8 PmcC10DynamicThresholdAdjustment;
-/** Offset 0x0F8B - P2P mode for PCIE RP
+/** Offset 0x0FAB - P2P mode for PCIE RP
Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable.
0: Disable, 1: Enable
**/
UINT8 CpuPcieRpPeerToPeerMode[4];
-/** Offset 0x0F8F - Reserved
+/** Offset 0x0FAF - Reserved
**/
- UINT8 Reserved60[33];
+ UINT8 Reserved57[33];
-/** Offset 0x0FB0 - FspEventHandler
+/** Offset 0x0FD0 - FspEventHandler
<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
**/
UINT32 FspEventHandler;
-/** Offset 0x0FB4 - Enable VMD Global Mapping
+/** Offset 0x0FD4 - Enable VMD Global Mapping
Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
$EN_DIS
**/
UINT8 VmdGlobalMapping;
-/** Offset 0x0FB5 - Reserved
+/** Offset 0x0FD5 - Reserved
**/
- UINT8 Reserved61[3];
+ UINT8 Reserved58[3];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -3891,11 +3879,11 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x0FB8
+/** Offset 0x0FD8
**/
- UINT8 UnusedUpdSpace44[6];
+ UINT8 UnusedUpdSpace41[6];
-/** Offset 0x0FBE
+/** Offset 0x0FDE
**/
UINT16 UpdTerminator;
} FSPS_UPD;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 14:00:41 +0000